JPH04323914A - D/a converter - Google Patents

Abstract

PURPOSE:To reduce the layout area of a D/A converter. CONSTITUTION:Let a power supply voltage of a power supply terminal be VDD and a ground potential be 0, then a connection line 101 to a 3-bit R string type D/A converter 10 is set to a power supply voltage VDD through the switching action of switching elements 1, 2, 3, 4 and 5 corresponding to a logic level H or L of the most significant bit of a digital signal inputted from a digital signal input terminal 52, or a connection line 101 to the 3-bit R string type D/A converter 10 is set to a ground potential. In this case, a potential at a node A is set to VDD/2, the potential of the connection lines 101, 102 is set to a reference voltage and bits of succeeding bit of the digital signal are inputted to the 3-bit R string type D/A converter 10 from digital signal input terminals 53, 54, 55 and D/A-converted and a desired analog conversion signal is outputted from an analog signal output terminal 56.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D/A converter.

0002

2. Description of the Related Art An example of a conventional R string type D/A converter is shown in FIG. In FIG. 3, n (positive integer) resistors 12-1 with the same resistance value are connected between the power supply terminal 57 and the ground potential.
1 to 12-n are connected, and the power supply voltage is connected to the connection point of these resistors, and between the grounding point of the terminal resistor 12-n and the analog signal output terminal 62, n switching elements 11- 1 to 11-n are inserted and connected, and control lines for these switching elements 11-1 to 11-n are individually connected to the decoder 13, respectively. For the decoder 13, digital signal input terminals 58 to
Digital signals to be D/A converted are input from 61, and through a combination of logic levels of these digital signals,
The decoder 13 outputs an "H" level or "L" level logic signal that controls on/off of the switching element. When these switching elements are turned on via the logic signal output of the decoder 13, the divided voltage corresponding to the connection point of the corresponding resistor is outputted to the analog signal output terminal 62 via the switching element. That is, the digital signals input to the decoder 13 from the digital signal input terminals 58 to 61 are D/A converted and output from the analog signal output terminals. In this case, since the number of digital signal input terminals is four, the number of resistance divisions is n=24.

0003

[Problem to be solved by the invention] The above-mentioned conventional D/A
In the converter, 256 resistors are required when the digital input signal is 8 bits, and 16 resistors are required when the digital input signal is 4 bits, as a resistor divider circuit for extracting the desired analog voltage. Therefore, as the number of bits of a digital input signal increases, the number of resistors has to be increased, and the disadvantage is that the proportion of the layout area occupied by the resistors in the D/A converter increases. be.

0004

[Means for Solving the Problems] The D/A converter of the present invention inputs the logic level of the most significant bit of a digital input signal and converts a predetermined reference voltage supplied for D/A conversion to a high level. a reference voltage dividing means for outputting the two divided reference voltages into a reference voltage on the potential side and a reference voltage on the low potential side; and an N-bit R-string type D/A converter that outputs an analog conversion signal corresponding to the digital input signal in accordance with the logic level of the next and subsequent bits.

[0005] Note that the N-bit R string type D/A
The converter may be a 3-bit R string type D/A converter.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. As shown in FIG. 1, in this embodiment, switching elements 1 to 5 are connected to each other corresponding to a power supply terminal 51, digital signal input terminals 52 to 55, and analog signal output terminal 56.
, an inverter 6 , resistors 7 to 9 , and a 3-bit R string type D/A converter 10 .

In FIG. 1, it is assumed that the power supply voltage supplied from the power supply terminal 51 is VDD, the ground potential is 0, and the most significant bit of the digital signal is input from the digital signal input terminal 52. When the input level of the digital signal input terminal 52 is at "L" level, switching elements 3 and 4 are turned on, and switching elements 1, 2, and 5 are turned off. At this time, since the switching element 4 is on, the potential of the connection line 102 between the switching elements 4 and 5 and the 3-bit R string type D/A converter 10 becomes the ground potential. In this case, in order to set the potential at the node A between the power supply voltage VDD and the ground potential to VDD/2, the combined resistance between the power supply terminal 51 and the node A, and the
The combined resistance between the ground point and the ground point must be equal.

Here, the resistance values of resistors 7 and 8 are set to R7.
and R8, and when the input resistance value of the 3-bit R string type D/A converter 10 is R, the following equation is given.

R8 = 1/(1/R+1/
(1) In this case, it corresponds to the "H" level and "L" level logic signals in the next digital signal input from the digital signal input terminals 53, 54, and 55. Then, an analog voltage ranging from 0 to 7VDD/16 is outputted from the analog signal output terminal 56 in steps of VDD/16. In this case, the relationship between the digital input signal and the analog output signal is as clearly shown in the input/output correspondence table of FIG. In FIG. 2, digital signal input terminal 5
Corresponding to the case where the level of 2 is "L" level, the output from the analog signal output terminal 56 corresponds to the level of the next and subsequent digital input signals inputted sequentially from the digital signal input terminals 53, 54, and 55. The voltage level is shown.

Furthermore, when the input level of the digital signal input terminal 52 is "H" level, switching elements 3 and 4 are turned off and switching elements 1, 2 and 5 are turned on, so that switching element 2 and 3 bits R The potential of the connection line 101 with the string type D/A converter 10 becomes the power supply voltage VDD, and the potential of the node A becomes the ground potential. Even in this case, in order to set the potential of node A to VDD/2, the combined resistance between power supply terminal 51 and node A must be equal to the combined resistance between node A and the ground point. Therefore, the following equation is given.

R9 = 1/(1/R+1/
R7 +1/R8) ...... (2) In this case, it corresponds to the "H" level and "L" level logic signals in the next digital signal input from the digital signal input terminals 53, 54 and 55. From the analog signal output terminal 56, VDD/2 to 15VDD/16
Analog voltages reaching VDD/16 are output. In this case, the relationship between the digital input signal and the analog output signal is clearly shown in the input/output correspondence table of FIG. Correspondingly, the voltage level output from the analog signal output terminal 56 is shown with respect to the level of the next and subsequent digital input signals inputted sequentially from the digital signal input terminals 53, 54, and 55.

In the case of this embodiment, the number of resistors in the circuit is reduced by half in the 3-bit R-string type D/A converter compared to the 4-bit R-string type D/A converter. The number of input lines to the decoder is reduced by one, and the number of constituent transistors is also smaller in the 3-bit R string type D/A converter, so the overall layout area is reduced to about half.

[0014]

As explained above, the present invention provides two reference voltages, one for the high potential side and the other for the low potential side, which are divided into two by the logic level of the most significant bit of the digital input signal.
By performing D/A conversion via the next and subsequent bits of the digital input signal, there is an effect that the layout area can be significantly reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram showing an input/output correspondence table of digital signals and analog signals in this embodiment.

FIG. 3 is a block diagram showing a conventional example.

[Explanation of symbols]

1 to 5, 11-1 to 11-n switching element 6 inverter 7 to 9, 12-1 to 12-n resistor 10 3
Bit R string type D/A converter 13 Decoder

Claims (2)

[Claims] Claim 1: By inputting the logic level of the most significant bit of a digital input signal, a predetermined reference voltage supplied for D/A conversion is divided into a high potential side reference voltage and a low potential side reference voltage. a reference voltage dividing means for dividing into two and outputting the divided voltage; A D/A converter comprising: an N (positive integer) bit R string type D/A converter that outputs an analog conversion signal corresponding to a digital input signal. 2. The D/A converter according to claim 1, wherein the N-bit R string type D/A converter is a 3-bit R string type D/A converter.