JPH0831793B2 - Analog / digital (A / D) converter - Google Patents

Description

TECHNICAL FIELD The present invention relates to an analog / digital converter (hereinafter abbreviated as A / D converter), and particularly, when an abnormality occurs in the A / D converter, a malfunction occurs. The present invention relates to an A / D conversion device having a fail-safe function that prevents the

[Conventional technology]

Conventionally, the A / D conversion value output from the A / D converter and the previous time
A fail-safe function that finds the deviation from the A / D-converted value and judges that the A / D conversion was performed normally if this deviation is less than a predetermined value and updates the A / D-converted value. (For example, Japanese Patent Laid-Open No. 55-115102), or an analog reference voltage is digitally converted by an A / D converter, and the digitally converted reference voltage data is stored in advance in the control device. There is one that compares the digital reference voltage data and detects an abnormality in the A / D converter (for example, Japanese Patent Laid-Open No. 1-196919).

[Problems to be Solved by the Invention]

By the way, A / D that receives multiple analog signals and selects analog signals according to the A / D conversion operation command to perform A / D conversion
In the converter, for example, an A / D conversion operation command of a processing system having a high priority may be input to the A / D converter during A / D conversion. In such a case, the A / D conversion that has been performed up to now is interrupted, and the processing is resumed after the A / D conversion of the high-priority processing system is completed. However, at this time, regarding the A / D conversion of the low priority processing system, the A / D conversion of the low priority processing system is performed again after the A / D conversion operation of the high priority processing system is completed.
Unless conversion is executed, the A / D conversion value when returning to a processing system with a lower priority will be the conversion value converted by the processing system with a higher priority. In such a case, it is judged that the analog signal selected by the previously input A / D conversion operation command has been A / D converted even though it has not been A / D converted,
Since the A / D conversion value that has not been updated is output as an updated value, there is a problem that the reliability of the converted data is reduced.

In view of the above problems, it is an object of the present invention to check the A / D conversion operation command before and after A / D conversion to improve the reliability of converted data.

[Means for solving the problem]

As a means for solving the above problems, the present invention is to convert a plurality of input analog signals into corresponding digital data and output the digital data, a first process executed at predetermined timings, and A second process that interrupts the first process is executed, digital data required for the first process is selected when the first process is executed, and digital data required for the second process is selected when the second process is executed. A transmitting unit that transmits an A / D conversion operation command to the converting unit, and an A / D conversion that is provided in the transmitting unit and is transmitted in response to the first process or the second process to be executed. A storage unit for storing the content of the operation command, the storage content being updated every time the A / D conversion operation command is transmitted,
It is provided in the conversion means, receives the A / D conversion operation command transmitted from the transmission means, and stores the contents thereof, and this stored content is stored every time the A / D conversion operation command is received and transmitted. Is updated, and the contents of the latest A / D conversion operation command stored in the storage unit after conversion into digital data by the conversion unit and the latest A stored in the control storage unit. Discrimination means for discriminating whether the contents of the / D conversion operation command match or not, and when the discrimination means judges that they do not coincide, the digital data output from the conversion means is ignored and a predetermined fail Analog / digital (A /
D) Propose a converter.

[Action]

This allows A / P where multiple analog signals are input.
The D converter converts the analog signal into digital data based on the A / D conversion operation command and outputs it. The latest A / D conversion operation command input to the A / D converter is stored in the storage means provided in the A / D converter.

That is, when the second processing system interrupts during A / D conversion by the first processing system and the A / D conversion operation command of the second processing system is input to the A / D converter, the A / D conversion of the first processing system is performed. The D conversion is interrupted, and the contents of the A / D conversion operation command of the first processing system stored in the storage means provided in the A / D converter is the A / D conversion operation command of the second processing system. Will be updated to the contents of.

Therefore, when returning from the A / D conversion of the second processing system to the A / D conversion of the first processing system, the storage means is the latest storage content of the storage means and the A / D conversion of the first processing system when the storage means is started. Different from the stored content, it is determined that the digital data does not originally match the first processing system, and predetermined fail-safe processing is executed by ignoring the digital data.

〔The invention's effect〕

According to the present invention, when there is a change in the A / D conversion operation command before and after the A / D conversion is started and there is a change, that is, when an abnormality is detected in the A / D conversion processing, it is determined that the abnormality has occurred. Since a predetermined fail-safe process that ignores digital data is executed, there is an excellent effect that the reliability of converted data output from the A / D converter is improved.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a vehicle electronic control unit (EC
It is a block diagram showing the composition of U). Reference numeral 1 denotes a sensor group, which includes, for example, an intake sensor, a cooling water temperature sensor, a throttle opening sensor, etc., and has an intake air amount Q and a cooling water temperature TH.
Analog signals such as W and throttle opening TVO are output from each sensor. Reference numeral 2 is an input circuit to which the above-mentioned analog signal is input.
It is input to each channel (CH1, CH2, CH3 ... CH8) of the channel analog-digital converter 3 (hereinafter referred to as A / D converter). Reference numeral 4 is a central processing unit (hereinafter CPU), 5 and 6 are well-known ROMs and RAMs, each of which is connected by a bus 7. CPU4 is A / based on the data stored in ROM5 and RAM6
The conversion operation command is output to the DE converter 3. Further, based on the output signal from the A / D converter 3 and the data and programs in the ROM 5 and RAM 6, the fuel injection amount and the ignition timing according to the operating state are calculated, and the injector 9 and the igniter 10 are output through the output circuit 8. A control signal for controlling is also output.

Further, the A / D converter 3 described above includes a register 31 for storing a conversion operation command parameter (hereinafter abbreviated as a parameter) from the CPU 4, and the A / D converter 3 responds to the parameter stored in the register 31. Perform A / D conversion. And A / D
When the conversion is completed, the A / D converter 3 outputs an end signal to the CPU 4. It also includes A / D registers 32-39 that store the A / D conversion values for each channel.The contents stored in these A / D registers 32-39 are the analog signals input to each channel CH1 to CH8. Updated when / D converted. Then, according to the access signal from the CPU 4, the A / D conversion values stored in the A / D registers 32-39 are transferred to the CPU 4.

Next, the operation of the ECU during A / D conversion will be described with reference to FIG.

First, in step 100, the A / D converter 3 stored in the RAM 5
Parameters to be output to the A / D converter 3 and the operation of the output circuit 8 are initialized.

Next, in step 200, it is determined whether or not it is the A / D conversion timing. When it is determined that the A / D conversion timing is reached, the process proceeds to step 300 to execute the A / D conversion processing described below, and the step 200 Return to.

If it is determined in step 200 that it is not the A / D conversion timing, the A / D conversion is not performed, the process proceeds to step 400, and another process (for example, calculation of the injection amount) is executed, and the step
Return to 200.

The A / D conversion process in step 300 will be described below with reference to FIG.

First, in step 301, parameters are sent to the A / D converter 3.

Here, the parameters will be described with reference to FIGS. 4 and 5. The above-mentioned parameter is 8-bit data, and the instruction item is set by the bit position.

Bit position 7 specifies A / D conversion operation, hit position 6 is A
Specifying the number of times / D conversion is performed, bit position 5 and bit position 4
Specifies the number of channels to be A / D converted,
Bit positions 3 to 0 specify the analog signal input channel number for starting A / D conversion.

For example, when the parameter is "10010000", this parameter means that the channels CH1 to CH4 are A / D converted only once.

Returning to FIG. 3, in step 302, the above-mentioned parameter is set to A.
When sent to the / D converter, the A / D converter 3 stores the input parameters in the register 31, and the A / D converter 3 according to the parameters.
Start D conversion. Further, the CPU 4 stores the output parameter in the register 41.

Next, at step 302, other processing (for example, the calculation amount of the injection amount) is executed using the waiting time required for A / D conversion, and the process proceeds to step 303. At this time, the A / D converter 3 executes A / D conversion and outputs an end signal to the CPU 41 when the A / D conversion is completed.

Next, in step 303, it is determined whether or not the A / D conversion is completed by the above-mentioned end signal.
Proceed to step 4 and check if the parameters that are A / D conversion operation commands have changed before and after conversion. That is, it is determined whether or not the parameter stored in the register 41 in the CPU 4 and the parameter stored in the register 31 in the A / D converter 3 match. The determination method is to transfer the parameter stored in the register 31 to the CPU 4 and
Take the difference from the parameter stored in. When this difference is 0, the two parameters are in agreement.

When the difference is 0, that is, when the two parameters match, it is assumed that the A / D conversion is normally performed.
In step 306, the access signal is sent to the A / D converter 3 and A / D is sent.
Transfer the A / D converted value from registers 32 to 39 to CPU4. A / D
When the converted value is transferred, it is determined in step 307 whether the A / D converted value is normal. This determination determines whether or not the A / D converted value this time is within a preset predetermined range.Normal when the A / D converted value is within the predetermined value range, abnormal when it is outside the predetermined value range. It is what If it is determined to be normal in step 308, the A / D conversion value is stored in a predetermined location on the RAM6, the present routine is terminated, and the process shifts to another process to the RAM6.
The fuel injection amount, ignition timing, etc. are calculated using the A / D conversion value stored above.

If it is determined in step 303 that the A / D conversion has not ended, the process returns to step 303 and waits until the A / D conversion ends. If it is determined in step 304 that the parameters do not match, the process proceeds to step 305, and the digital data when it is determined to be an abnormality, which will be described later, and fail-safe processing for initializing the parameters are executed.

If it is determined to be abnormal in step 307, the current A
The / D conversion value is read out and discarded, the routine is terminated without being stored in a predetermined location on the RAM 6, and another processing is performed. In this case, the fuel injection amount and ignition timing are calculated using the previous A / D conversion value.

FIG. 6 shows the CPU 4 and A in the A / D conversion operation described above.
/ D converter 3 and analog input signal (Q, TH
(W, TVO, etc.), parameter, A / D conversion end signal, and A / D conversion value.

The parameters from the CPU4 are input to the A / D converter 3,
The A / D converter 3 digitally converts the analog input signal according to this parameter. When the A / D conversion is completed, the A / D converter 3 outputs an end signal and the CPU 4 registers 31
When the access signal is output to, the parameters stored in the register 31 are also output. Parameter output from CPU4 (parameter stored in register 41) and register 31
When it matches the parameter stored in, the A / D conversion value is sent to the CPU 4 in response to the access signal from the CPU 4.

Next, the fail-safe processing in step 305 of FIG. 3 will be described.

The fail-safe processing is performed when the parameters do not match in step 304. First, when the parameters do not match will be described with reference to FIG.

Consider a case where there is a first processing system and a second processing system having a higher priority than this processing system. Note that these two processing systems have different A / D of analog signal input channels.
It is assumed that the processing routine for performing the conversion is included.

In step S10 of the first processing system, the A / D conversion timing is generated and the parameters are sent to the A / D converter 3 to execute the A / D conversion. After that, in step S20 of the second processing system with high priority, the A / D conversion timing occurs, and when the parameters are sent, the A / D conversion of the first processing system is interrupted and the A / D conversion of the second processing system is interrupted. D conversion is executed. At this time, the register 31 in the A / D converter 3 is rewritten with the parameters of the second processing system. When the A / D conversion of the second processing system is completed, the A / D conversion value of the second processing system is taken out and the second processing system is completed in step S21.

After that, the interrupted first processing system is restored and the continuation of the A / D conversion processing routine of the first processing system is executed. At this time, the register 31 stores the parameters of the second processing system. . After that, when the end of the A / D conversion of the first processing system is detected, the parameter stored in the register 41 output from the CPU 4 of the first processing system and the register
Check if the parameters stored in 31 match. The parameters issued by the second processing system are stored in the register 31 and do not match. That is, when the parameters are input by executing the A / D conversion processing routine of another processing system during the A / D conversion, they do not match.

Another example where the parameters do not match is A / D
It is possible that the converter 3 breaks down and destroys the parameters of the register 31, or the control program runs out of control.

If the parameters do not match as described above, the A / D conversion is not performed normally, so the A / D converted value cannot be used as normal data. Therefore, if the parameters do not match, fail-safe processing is required.

In the fail-safe process, when the parameters do not match, a system reset (restart) is performed on the CPU 4 and the process returns to step 100 in FIG. 2 to perform initial setting.

In the parameter check in the embodiment described above, it was determined whether or not all 8-bit values match, but it is also possible to compare only predetermined bit positions and determine that they are normal if they match.

For example, the parameter at bit position 6 is for instructing whether to convert only once or multiple times, so even if bit position 6 does not match, if other bit positions match, A /
The D conversion value may be used as a normal value.

In the match determination in this case, first, the bit position 6 of the parameter stored in the register 41 of the CPU 4 is rewritten to 0. Then, the bit position 6 of the parameter transferred to the CPU 4 from the register 31 in the A / D converter 3 is rewritten to 0. Next, take the difference between the respective parameters rewritten as above. If this difference is 0, it is determined that they match.

Also, instead of the fail-safe processing described above, A / D
Of the analog signal input that is determined to be abnormal to the converter 3
The A / D conversion may be restarted or the A / D conversion value may not be updated.

In the present embodiment, the A / D converter 3 has only one register 31, but a plurality of registers may be provided when the number of parameter setting items is large.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention, and FIGS. 2, 3, and 7 are CPU 4 and A / D converter 3.
FIG. 4 is a flow chart for explaining the operation of FIG. 4, FIGS. 4 and 5 are explanatory diagrams for explaining the parameters, and FIG. 6 is a block diagram showing data communication between the A / D converter and the CPU. 3 …… A / D converter, 31 …… Register, 4 …… CPU, 5 …… ROM, 6
……RAM.

Claims (3)

[Claims] 1. A conversion means for converting a plurality of input analog signals into corresponding digital data and outputting the digital data, a first process executed at a predetermined timing, and a ratio for the first process. A / D conversion operation command for selecting the digital data required for the first process when executing the first process and selecting the digital data required for the second process when executing the second process And transmitting means for transmitting to the conversion means, and stores the contents of an A / D conversion operation command which is provided in the transmission means and is transmitted in response to the first process or the second process to be executed. And a storage unit for updating the stored contents each time an A / D conversion operation command is transmitted, and an A / D conversion operation command transmitted from the transmission unit, provided in the conversion unit. To receive A storage unit for storing the contents, the storage contents being updated each time an A / D conversion operation command is received, and the latest data stored in the storage unit after conversion into digital data by the conversion unit. Discriminating means for discriminating whether or not the contents of the A / D conversion operation command and the contents of the latest A / D conversion operation command stored in the control storage means are coincident with each other; Analog / digital (A / D), characterized in that the digital data output from the conversion means is ignored and a predetermined failsafe processing is executed.
Conversion device. 2. The A / D conversion operation command is transmitted in the form of binary data having a bit for selecting an analog signal to be A / D converted among a plurality of analog signals and a bit for setting the operation of the conversion means. The analog / digital (A / D) conversion device according to claim 1, wherein 3. The content of predetermined bits of the latest A / D conversion operation instruction stored in the storage means and the latest A / D conversion operation instruction stored in the control storage means, 3. The analog-to-digital (A / D) conversion device according to claim 2, wherein the contents of the predetermined bits are compared with each other to determine whether they match.