JPH05128065A - Data communication equipment - Google Patents

Abstract

PURPOSE:To rapidly and surely execute data communication in a data communication equipment for transmitting/receiving digital data. CONSTITUTION:In an engine control device for executing engine control by two CPUs 16, 26, both CPUs 16, 26 are mutually connected through a communicating clock signal line A, data lines B, C and a hand-shaking line D and data are exchanged between respective CPUs 16, 26 by synchronizing serial communication under the communication control of the CPU 16. After receiving transmission data from the CPU (master) 16 and executing their processing, the CPU (slave) 26 informs the processed contents to the CPU 16 through the hand- shaking line D to demand the succeeding data transmission.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data communication device for transmitting / receiving digital data by a transmitting / receiving device.

[0002]

2. Description of the Related Art Conventionally, as a data communication apparatus of this type, as disclosed in, for example, Japanese Patent Application Laid-Open No. 2-220167, a handshake line for transmitting a control signal is provided in addition to a data line for transmitting data. A data communication device configured to provide information indicating that data transmission is started from a transmission side to a reception side is known.

[0003]

However, such a conventional data communication apparatus has no problem when the amount of data transmitted from the transmitting side is small and the data transmission interval is long, but the amount of data to be transmitted is large and the data transmission is large. When the interval between
The receiving side sometimes could not process the received data normally.

That is, for example, in an electronic control unit for a vehicle that controls an engine or the like using a plurality of CPUs, it is necessary to process a large amount of data at high speed in order to improve control accuracy. Although it is required to shorten the data communication time for each data in the above, in the above-mentioned conventional device, the transmission side determines the start of data transmission and informs the reception side accordingly. If the transmission interval is shortened, the next data transmission may start on the transmission side before the reception side finishes processing the received data, and normal data communication may not be possible. It was

The present invention has been made in view of these problems, and an object of the present invention is to provide a data communication device capable of performing data communication at high speed and reliably.

[0006]

That is, according to the present invention, which has been made to achieve the above object, a data line for data transmission and a plurality of digital data are provided on the data line as illustrated in FIG. In a data communication device including a transmission device that sequentially transmits and a reception device that receives digital data from the transmission device via the data line, a handshake line is provided between the transmission device and the reception device, The reception device is provided with reception completion signal output means for outputting a reception completion signal indicating the fact on the handshake line when reception of one piece of digital data transmitted from the transmission device is completed, and further the transmission device To
After the transmission of one digital data is completed, when a reception completion signal is received from the receiving device via the handshake line, a transmission start control means for starting the transmission of the next digital data is provided. The main point is data communication equipment.

[0007]

In the data communication apparatus of the present invention configured as above, when the transmitting apparatus transmits digital data on the data line, the receiving apparatus receives the digital data via the data line. Then, when the receiving device completes the reception of the digital data, the receiving completion signal outputting means in the receiving device outputs a reception completion signal indicating that fact on the handshake line. Then, the transmission start control means in the transmitter receives the reception completion signal via the handshake line and starts the transmission of the next digital data.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. First, FIG. 2 is a block diagram showing the configuration of a vehicle engine control apparatus of an embodiment to which the present invention is applied.

As shown in FIG. 2, the vehicle engine control system of this embodiment is an electronic control circuit for performing fuel injection amount control, idle rotation control, fuel pump control, valve drive control, supercharging pressure control, failure diagnosis and the like. (ECU) 10 and an electronic control circuit (ECU) 20 that performs ignition timing control, knock control, boost pressure calculation, and the like.

The ECU 10 includes an input buffer 11 for inputting various switch signals such as a start switch and a clutch switch, a waveform shaping circuit 12 for shaping pulse signals from a rotation speed sensor, a cylinder discrimination sensor and the like and inputting them.
Output driver 14 for outputting drive signals for A / D converter 13, fuel injection valve, idle speed control valve, etc. for converting analog signals from various sensors for detecting intake pipe pressure, cooling water temperature, etc. into digital signals for input , I / O port 15 and I / O port 1 connected to these parts
CPU16 which takes in the switch signal and the sensor signal through 5 and performs the arithmetic processing for engine control, and outputs various drive signals from the output driver 14
ROM 17 in which programs and various data for performing arithmetic processing in 16 are stored in advance, and RAM 1 in which data is temporarily stored when performing arithmetic processing in CPU 16.
The ECU 20, like the ECU 10, includes an input buffer 21, a waveform shaping circuit 22, an A / D converter 23, an output driver 24, an I / O port 25, and a CP.
It is composed of U26, ROM 27, and RAM 28.

Each of the CPUs 16 and 26 has a communication function and bidirectionally performs data communication by synchronous serial communication. That is, in this embodiment, the CPU 16 is defined as the master and the CPU 26 is defined as the slave.
Between the PUs 16 and 26, a communication-dedicated clock line A for supplying a clock signal for communication from the master side to the slave side, a data line B for transmitting digital data from the master side to the slave side, and a slave side to the master side Are connected by a data line C for transmitting digital data, and a handshake line D for notifying completion of data reception from the slave side to the master side.

As shown in FIG. 3, the CPUs 16 and 26 are connected by data lines B and C to simultaneously transmit and receive 8-bit digital data in one communication.
Equipped with bit shift registers 16a and 26a,
Under the communication control by the master side CPU 16, first, the digital data to be transmitted is transferred to each shift register 16a, 26a.
Stored in the shift register 16a and 26a, the transmission data in the shift registers 16a and 26a are shifted by 1 bit by the communication clock signal and transmitted to the respective data lines B and C, thereby transmitting the transmission data to the other shift register. 26a, 16a
The data is transmitted by the procedure of transferring to. Further, after the data is transmitted, the transmission data from the other CPU is stored in the shift register, so that the data (reception data) is fetched in the reception buffer.

As described above, the CPUs 16 and 26 perform data communication by mutually exchanging digital data using the shift registers 16a and 26a. Therefore each E
In the ROMs 17 and 27 of the CUs 10 and 20, a data list indicating the type, order, amount of data, etc. of data for data exchange is stored for each preset type of data communication. That is, in the present embodiment, data that requires high-speed data exchange such as throttle opening, battery voltage, and switch input is exchanged at high speed such as cooling water temperature and atmospheric pressure by data communication every 8 msec. 32m without data
Data communication every sec., intermediate data 16msec.
It is designed to exchange data with each data communication.
For this reason, the ROMs 17 and 27 store a data list indicating the type, order, amount of data, etc. of data for data exchange for each type of data communication. The data communication of this embodiment is performed by the CPU 16 on the master side.
Therefore, the schedule data for determining the type of data communication when starting the data communication is stored in the ROM 17 of the ECU 10.

Data communication executed under the control of the CPU 16 on the master side as described above will be described below with reference to FIGS.
A description will be given along the flowchart shown in FIG. Figure 4
Is a flowchart showing a data transmission start process executed by the master CPU every 4 msec.

As shown in the figure, when this process is started, first in S10, a predetermined time (for example, 4.09) has passed since the last communication.
6 msec.) Or more has passed, and if more than a predetermined time has passed, the process proceeds to S11 to determine whether or not the previous communication has been completed. If the previous communication has affected the communication start timing of this time due to a communication delay or the like, new communication is skipped without starting, and the number of skips is counted in S18. Then, in the subsequent S19, it is determined from the counted number of skips whether or not the communication skips continuously occur a predetermined number of times or more. If the skips occur consecutively a predetermined number of times or more, communication processing between the CPUs is performed. In the case of some abnormality (for example, normal communication cannot be performed due to runaway of the CPU 26 on the slave side), the system is reset, and if not, the processing is ended as it is.

On the other hand, if it is determined in S11 that the previous communication has been completed, the process proceeds to S12, and all the received data on the receive buffer transferred from the slave CPU 26 in the previous communication is added. A well-known checksum calculation is performed, and in S13, an abnormality in the received data is checked from the calculation result and the mirror code which is the final data in the received data. And if the received data is normal,
In S14, the received data on the receive buffer is written in the RAM 18, and the process proceeds to S15. If the received data is abnormal, the data in the receive buffer is discarded and the process proceeds to S15.

Next, in S15, the data communication this time is 8 m.
sec. communication, 16 msec. communication, or 32
Whether it is msec. communication is set in advance based on schedule data stored in the ROM 17, a data list corresponding to the type of communication is read from the ROM 17, and data to be transmitted is sequentially extracted according to the data list. Transmission data is created by the procedure, and the transmission data is set in the transmission buffer in S16. When setting the transmission data in the transmission buffer, the checksum is calculated by adding all the data to be transmitted, and the mirror code is stored in the transmission buffer as the final data of the transmission data.

Then, in step S17, a control code indicating the type of communication this time is written in the shift register 16a, and a clock signal for data communication is generated to start communication, and the processing is temporarily ended. After that, the master side CPU 16 executes another processing program for engine control until the reception completion signal is input from the slave side CPU 26 (edge input from low level to high level) via the handshake line D. , CP on the slave side
When the reception completion signal is input from U26, it is determined that the processing on the slave side has been completed, and the interrupt processing shown in FIG. 5 is executed.

That is, in this interrupt processing, first in S20,
Use the communication continuation flag that is set at the start of communication to determine whether communication is currently in progress.If communication is not ongoing, check whether the interrupt this time is a malfunction due to noise, etc. , S28, handshake line D
Is checked, and after the level of the handshake line D becomes the normal Low level, the processing is ended.

On the other hand, if the communication is continuing, it is judged in S21 whether or not it is immediately after the control code is transmitted in the previous process. If it is not immediately after the control code is transmitted, the process proceeds to S22 and shifts. The reception data in the register 16a is stored in the reception buffer. Then, in subsequent S23, it is determined from the value of the communication counter updated in S25 whether or not all the data is received, and if all the data is not received, S24 is performed.
Confirm that the level of the handshake line D is the normal low level in, and after updating the communication counter in S25, move to S26 and the data to be transmitted next stored in the transmission buffer. Is set in the shift register 16a to generate a clock signal for data communication, data is transmitted, and the process is completed.

If it is determined in S21 that the control code has just been transmitted in the previous processing, the transmission data from the slave CPU 26 is meaningless (the slave CPU 26 sends the control code). After receiving and preparing transmission data and starting data transmission from the next data communication), the process directly proceeds to S24, and the above S
After performing a series of transmission processing of 24 to S26, the processing is ended.

On the other hand, if it is determined in S23 that all the data has been received, the communication continuation flag is reset, and in S28, it is confirmed that the level of the handshake line D is a normal Low level, and then the process is terminated. To do. Next, FIG. 6 is a flowchart showing a communication process executed by the slave CPU 26. Note that this process is an interrupt process by data transmission from the master side CPU 16, and the slave side CPU 26 normally executes another engine control program in the main routine.

As shown in the figure, when this process is started,
First, in S30, the handshake line D is placed in a standby state (that is, at a low level) so that an edge interrupt can be applied to the master side CPU 16, and in S31, the shift register 26 transmitted from the master side CPU 16 this time.
Check if the data in a is a control code.

If the received data is the control code, the communication continuation flag is set in S32, the communication counter is initialized in S33, transmission data is created in S34, and the transmission data is stored in the transmission buffer in S35. Execute a series of processing for communication preparation such as setting.
The processes of S34 and S35 are executed in the same manner as S15 and S16 in the master CPU 16 by identifying the type of communication from the control code in the shift register 26a.

When the preparation for the data communication is completed in this way, the process proceeds to S36, the transmission data to be transmitted this time is extracted from the transmission data stored in the transmission buffer and set in the shift register 26a, and in S37. After updating the communication counter, in S38, the handshake line D is once set to the high level and returned to the low level, thereby edge-interrupting the master side CPU 16 and temporarily ending the processing.

On the other hand, when it is determined in S31 that the received data is not the control code, the process proceeds to S39, the received data in the shift register 26a is stored in the receiving buffer, and S
At 40, it is determined whether or not all data has been received. If all the data has not been received, the process proceeds to S36, and if all the data has been received, the process proceeds to S41 to perform a checksum calculation of all the received data in the reception buffer, and S43.
Check the checksum error. If there is no checksum error, the reception data in the reception buffer is written in the RAM 28 in S43, and the subsequent S4
If there is a checksum error, the received data is discarded and the process proceeds to S44. Then, in step S44, the communication continuation flag is reset, and in step S45, the communication counter is cleared, and then the process ends.

In the engine control device of this embodiment having the above-mentioned structure, as shown in FIG.
When the PU 16 starts the communication process at the base timing of every 4 msec. (Communication process B shown in the figure) and transmits the control code CO, the slave CPU 26 executes the interrupt process I to prepare for the communication. When the communication is completed and the preparation for communication is completed, the CPU 16 on the master side is passed through the handshake line D.
The interrupt process I is executed. When the master side CPU 16 transmits data by this interrupt processing I,
Along with this data transmission, the slave CPU 26 performs the interrupt process I again to process the received data, and when this process is completed, the master CPU transmits the handshake line D.
The digital data DA is sequentially exchanged by a procedure such that an edge interrupt is again applied to 16. Finally, the mirror code CH for checksum error check is exchanged, and the data communication ends.

Therefore, according to this embodiment, the slave side C
After the PU 26 finishes the communication process, the CPU 16 on the master side
The communication process can be executed, and the digital data can be surely transmitted and received. Further, the slave CPU 26 has the handshake line D at the end of the communication process.
Since the master side CPU 16 executes the communication processing by the edge interruption via the, the response time is required until the next data communication is executed after the slave side CPU 26 finishes the communication processing. It can be minimized, and data communication can be performed at high speed.

In this embodiment, an apparatus for performing synchronous serial communication has been described, but the present invention can also be applied to an asynchronous communication system. Further, in this embodiment, a system in which two CPUs perform bidirectional data communication has been described, but the present invention can also be applied to a system in which unidirectional data communication is performed.

[0030]

As described above, in the data communication apparatus of the present invention, when the receiving apparatus completes the reception of the digital data, the receiving apparatus transmits the next digital data to the transmitting apparatus via the handshake line. Since the transmission request is sent, the digital data can be surely transmitted from the transmission device to the reception device.

Further, when the transmission device receives the reception completion signal from the reception device via the handshake line, it starts transmission of the next digital data. Therefore, after the reception device completes the reception of the digital data, the transmission device is started. The response time until the next digital data transmission starts can be suppressed to the necessary minimum, and the data communication can be performed at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a configuration of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a vehicle engine control device according to an embodiment.

FIG. 3 is an explanatory diagram illustrating an operation of exchanging digital data between CPUs.

FIG. 4 is a flowchart showing a data transmission start process executed by a master CPU.

FIG. 5 is a flowchart showing an edge interrupt process executed by a master CPU.

FIG. 6 is a flowchart showing a communication process executed by a slave CPU.

FIG. 7 is a time chart explaining the data communication operation of the embodiment.

[Explanation of symbols]

10, 20 ... Electronic control circuit (ECU) 11, 21 ... Input buffer 12, 22 ... Waveform shaping circuit 13, 23 ... A / D converter 14, 24 ... Output driver 15, 25 ... I / O port 16 ... CPU ( Master) 26 ... CPU (slave) 17, 27 ... ROM 18, 28 ... RAM 16a, 26a ... Shift register A ... Communication dedicated clock line B, C ... Data line D ... Handshake line

Claims (1)

[Claims] 1. A data line for performing data transmission, and a data line.
Number of digital data to be sequentially transmitted on the data line
Signal from the transmitter and the transmitter from the transmitter via the data line.
Data communication with a receiving device for receiving digital data
In the device, a handshake line is installed between the transmitter and the receiver.
And the one sent from the transmitter to the receiver.
When the reception of the digital data of
The reception completion signal is output on the track line to indicate that
End signal output means is provided, and further transmission of one digital data to the transmission device is completed.
Then, from the receiving device via the handshake line
When the reception completion signal is received, the next digital data is transmitted.
A data communication device, comprising: a transmission start control means for starting.