JPH08316737A - Mixer circuit - Google Patents

Abstract

PURPOSE: To obtain the mixer circuit with excellent linearity and less spurious radiation by connecting a capacitor to an integrated circuit between an IF terminal of an integrated mixer circuit and a ground terminal. CONSTITUTION: A circuit part surrounded by a thick line is an integrated circuit and a caption Lp indicates a parasitic inductor produced at mounting. A capacitor C2 is connected between a ground terminal and a drain output terminal on the integrated circuit. Thus, the impedance of a drain at a high frequency is reduced. The impedance of the ground terminal on the integrated circuit is easily decreased by countermeasures such as the use of a lead frame and use of plural bonding wires.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency circuit and provides a receiving mixer circuit suitable for integration.

[0002]

2. Description of the Related Art With the spread of mobile communication, the integration of high frequency circuits has been actively promoted. As one of the high frequency circuits, there is a down converter that converts a high frequency signal into an intermediate frequency signal. Although there are many circuit types in the down converter, one of the typical ones is a single mixer using a dual gate FET (field effect transistor).

FIG. 2 shows this conventional dual gate mixer. The dual gate mixer is a high frequency (RF) signal input matching circuit, a local oscillation (LO) signal input matching circuit, an intermediate frequency (IF) signal output matching circuit, a dual gate FET.
It is composed of The equivalent circuit of the dual gate mixer is 2
It is represented by the cascode connection of two FETs. The operating principle of the dual gate mixer will be described with reference to FIG. An RF signal is input to the lower gate G1. A gate voltage Vg is Vg = vgAC + VgDC between the input terminal and the gate terminal.
If given by, the drain current Id of the lower FET
Is given by Id = gmvgAC + IdDC. Where vg
AC is an AC gate bias voltage, VgDC is a DC gate bias voltage, gm is a small signal transconductance of the FET, and IdDC is a DC bias current. Upper gate G2
A LO signal is applied to. The LO signal is sufficiently large, and the FET in the upper stage performs an operation of switching between two states, an on state and an off state. This switching operation causes frequency conversion. At this time, the drain current is expressed by Equation 1.

[0004]

## EQU1 ## Id = (gm / pi) vgACsin2pi (fRF-fLO) t + (gm / pi) vgACsin2pi (fRF + fLO) t + IdDCsin2pi (fLO) t (Equation 1) where pi represents the circular constant. . The current signal expressed by the equation 1 is output through the IF signal output matching circuit. First
The term is the IF signal and the desired output. The second term is an image signal and the third term is a local signal, which is a signal that needs to be removed. When these signals are transmitted to the subsequent stage, a non-linear circuit such as a second mixer in the subsequent stage generates a spurious signal. It also causes deterioration of the linearity of the mixer circuit itself.

The deterioration is caused by the drain potential being modulated by an unnecessary signal. The conventional dual gate mixer is configured by combining individual components, and there are many circuit formats for the IF output circuit, but basically, it is I
It is designed to match at the F frequency and ground the drain terminal at the image and local frequencies.
Generally, as the RF frequency becomes higher, the local frequency and the image signal frequency also become higher, making it difficult to make the drain terminal a ground impedance, and the unnecessary signal causes characteristic deterioration.

[0006]

SUMMARY OF THE INVENTION An object of the present invention is to provide an RF
It is to realize a high-performance mixer circuit even if the frequency becomes high.

[0007]

The above object is realized by connecting a capacitor on an integrated circuit between an IF output terminal and a ground terminal to reduce unnecessary signals such as local signals mixed in the IF terminal.

[0008]

By grounding the IF output terminal via a capacitor on the integrated circuit, it is possible to lower the impedance of the IF output terminal (drain) at the local frequency and the image frequency as compared with the case where the conventional individual component is used. .

Details will be described with reference to FIG. FIG. 3 is a detailed equivalent circuit of the IF matching circuit when the individual parts are used. The part surrounded by the thick line in the figure is the integrated circuit, and Lp
Indicates a parasitic inductor accompanying mounting. It is difficult to sufficiently reduce the impedance of the drain terminal due to the influence of the parasitic inductor inserted in series with the drain output. By integrating the capacitance and connecting it to the ground terminal in the integrated circuit, these parasitic inductors can be significantly reduced, and unnecessary signals can be easily removed.

[0010]

EXAMPLE A first example of the present invention will be described with reference to FIG. As described in the section of the above action, it is an essential point of the present invention to reduce the parasitic inductor by integrating the capacitance and efficiently remove the unnecessary signal. In FIG. 1, a portion surrounded by a thick line is an integrated circuit, and Lp represents a parasitic inductor associated with mounting. In this embodiment, the capacitance C2 is inserted between the ground terminal on the integrated circuit and the drain output terminal to realize the reduction of the impedance of the drain at a high frequency.

The impedance of the ground terminal on the integrated circuit can be easily lowered by taking measures such as using a lead frame and using a plurality of bonding wires. Although FIG. 1 shows a drawing using a plurality of bonding wires as an example, the present embodiment is not limited to this.

According to the present embodiment, the effect of a parasitic inductor inserted in series with the capacitance (C2) is reduced and a mixer circuit with improved linearity is realized as compared with the conventional mixer circuit composed of individual components. it can. In this embodiment, the matching circuits for RF signals and local signals are also integrated, but these matching circuits may be configured externally.

A second embodiment of the present invention will be described with reference to FIG. In this embodiment, a capacitance is inserted between the source terminal and the drain terminal of the dual gate mixer. A self-bias resistor is connected to the source terminal, and DC
Bias level is determined. In terms of high frequency, the bypass capacitor C1 is grounded and is in a low impedance state. Therefore, the source terminal is regarded as the ground terminal, and the unnecessary high frequency signal at the drain terminal is short-circuited to the ground potential via the source terminal. In this case, the parasitic inductor Lp is also affected, but the impedance of Lp is apparently small because the unwanted signal that sneak from the source and the unwanted signal that is output from the drain are in opposite phases, and there is an improvement effect. Also in the present embodiment, it is possible to reduce the influence of the parasitic inductor inserted in series with the capacitor (C2) and realize a mixer circuit with improved linearity.

A third embodiment of the present invention is shown in FIG. In the present embodiment, the mixer circuit is not limited to the dual gate mixer but is expanded to a general mixer circuit. As described in the first embodiment, the ground terminal on the integrated circuit can easily reduce the parasitic effect by increasing the number of bonding wires as compared with other signal input / output terminals. By connecting a capacitor between the IF output terminal on the integrated circuit and the ground terminal on the integrated circuit, it is possible to easily reduce unnecessary local signals and image signals. Although the capacitance is connected to the ground terminal in FIG. 5, the power supply terminal of the mixer can be used.

A fourth embodiment of the present invention is shown in FIG. In this embodiment, a Gilbert mixer is specifically applied as the mixer of the third embodiment. The fact that the parasitic inductor Lpg associated with the ground terminal can be easily reduced compared to Lp associated with the IF output terminal is utilized.

A fifth embodiment of the present invention is shown in FIG. In this embodiment, a Gilbert mixer is specifically applied as the mixer of the third embodiment, and a capacitor is inserted between the IF output on the integrated circuit and the power supply terminal on the integrated circuit. It utilizes the fact that the parasitic inductor Lpd associated with the power supply terminal can be easily reduced compared to Lp associated with the IF output terminal.

A sixth embodiment of the present invention is shown in FIG. In this embodiment, a parasitic inductance and an integrated capacitor that resonates at a local frequency are connected, and the parasitic inductance is used to suppress the local signal at the IF output. The maximum unnecessary signal at the IF output terminal of a mixer normally used in a down converter is a local signal, and in this embodiment, the local signal removal characteristic is particularly strengthened. Of course, the image signal can be removed by changing the resonance frequency, and it is also possible to apply a plurality of resonators as indicated by the dotted lines in the figure.

A seventh embodiment of the present invention is shown in FIG. In the present embodiment, the parasitic inductor of the sixth embodiment is replaced with a spiral inductor on an integrated circuit, which has the effect of reducing the number of pins as compared with the sixth embodiment.

[0019]

As described in the above embodiments, according to the present invention, unnecessary signals in the IF output section can be eliminated, and a mixer circuit with less spurious and excellent linearity can be realized.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit block diagram showing a conventional dual gate mixer.

FIG. 3 is a detailed equivalent circuit diagram of an IF matching circuit.

FIG. 4 is a circuit block diagram showing a second embodiment of the present invention.

FIG. 5 is a circuit block diagram showing a third embodiment of the present invention.

FIG. 6 is a circuit block diagram showing a fourth embodiment of the present invention.

FIG. 7 is a circuit block diagram showing a fifth embodiment of the present invention.

FIG. 8 is a circuit block diagram showing a sixth embodiment of the present invention.

FIG. 9 is a circuit block diagram showing a seventh embodiment of the present invention.

[Explanation of Codes] Lp, Lpg, Lpd ... Parasitic inductor, S ... Source,
D ... Drain, G1, G2 ... Gate, C1, C2 ... Capacitance.

Claims (7)

[Claims] 1. An integrated mixer circuit having a first terminal for high-frequency grounding, a second terminal for inputting a high-frequency signal, and a third terminal for outputting an intermediate-frequency signal, wherein the third terminal is on the integrated circuit. And a capacitor connected between the first terminal and the first terminal. 2. The mixer circuit according to claim 1, wherein the first terminal for high frequency grounding is a DC grounding terminal. 3. The mixer circuit according to claim 1, wherein the first terminal for high frequency grounding is a terminal for supplying a DC bias. 4. The mixer circuit according to claim 1, wherein a dual gate field effect transistor having a source electrode, a drain electrode, a lower first gate electrode, and an upper second gate electrode is used as the mixer circuit, A second terminal for signal input is directly or via an impedance element connected to the first gate, a local oscillation signal is applied to the second gate, and a source electrode is connected to a DC ground terminal via a resistor, The first capacitor C1 is connected between the source electrode and the ground potential on the integrated circuit or outside the integrated circuit, and the drain electrode is connected to the third terminal for outputting the intermediate frequency signal directly or via an impedance element, A mixer circuit in which a second capacitor C2 is connected between the drain electrode and the first terminal on the integrated circuit. 5. The mixer circuit according to claim 4, wherein the dual gate field effect transistor is replaced with a cascode. 6. The mixer circuit according to claim 4, wherein the connection of the second capacitor C2 between the drain electrode and the source electrode is changed. 7. A mixer circuit according to claim 2 or 3, wherein the mixer circuit is known as a Gilbert-type multiplier.
A mixer circuit using a double actuation circuit.