JP3924177B2 - Integrated circuit for tuner - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a tuner integrated circuit used in a television tuner.
[0002]
[Prior art]
FIG. 4 shows the circuit configuration and terminal arrangement of a conventional tuner integrated circuit (hereinafter referred to as an integrated circuit) and the connection relationship between peripheral circuits. The conventional integrated circuit 60 has 16 terminals on two opposite sides as shown in FIG. 4 (numbers in circles indicate terminal numbers (No.)).
[0003]
No. 1 to No. No. 16 terminals are provided on one side 60a. 17 to No. Up to 32 terminals are provided on the other side 60b. In addition, a plurality of circuits as shown schematically are formed inside, and the UHF mixing circuit 61 has a balanced input terminal No. 31, no. 32, and the VHF mixing circuit 62 has an input terminal No. 29 terminals are connected. The balanced output terminals of the mixing circuits 61 and 62 are No. 26, no. 27 terminals.
[0004]
A local oscillation signal is supplied to the VHF mixing circuit 62 from the two oscillation circuits 63 and 64. The VHF low band oscillating circuit 63 has two differential type oscillating transistors 63a and 63b. 1 is connected to the terminal of the other oscillation transistor 63b. 2 terminals. The VHF high-band oscillation circuit 64 also has two differential oscillation transistors 64a and 64b. 4 is connected to the terminal of the other oscillation transistor 64b. 5 is connected.
[0005]
A local oscillation signal is supplied from the UHF oscillation circuit 65 to the UHF mixing circuit 61. The UHF oscillation circuit 65 also has two differential oscillation transistors 65a and 65b, and the base of one oscillation transistor 64a is No. 6 and its collector is connected to no. 8 terminals. The base of the other oscillation transistor 65b is No. 9 and its collector is No. 9. 7 terminal.
[0006]
No. 17-No. The terminal 19 receives data for selecting a receiving channel from a television receiver main body (not shown). Specifically, a clock signal is input to the No. 17 terminal, channel selection data and band switching data are input to the No. 18 terminal, and address data is input to the No. 19 terminal. These data are input to the PLL circuit 67 and the band switching voltage generation circuit 68 through the interface 66. A local oscillation signal is input to the PLL circuit 67 from each of the oscillation circuits 63, 64 and 65. The error signal output from the PLL circuit 67 is DC-converted by a charge pump 69 having a low-pass filter. The tuning voltage is output to 15 terminals. The reference signal is input from the reference oscillation circuit 71 to the PLL circuit 67. The oscillator connection end of the reference oscillation circuit 71 is No. 16 terminals are connected.
[0007]
The switching voltage generation circuit 68 has a plurality of switch circuits therein, and generates a switching voltage of a high level or a low level, respectively, according to input data. This switching voltage is used for switching the band to be received. 20, no. 23 to No. 25, no. 30 are output to each terminal.
The intermediate frequency amplifier circuit 72 is configured as a balanced type, and its two input terminals are No. 1 and No. 2 respectively. 21, no. The output terminal is connected to the terminal No. 22. 11, no. 12 terminals are connected.
No. 3, no. 10, no. No. 28 terminal is grounded. A power supply voltage B to be supplied to each circuit is applied to 13 terminals.
[0008]
A peripheral circuit connected to the integrated circuit 60 is provided outside. The UHF band television signal passes through the UHF high-frequency amplifier circuit 73 and the UHF tuning circuit 74 and is transmitted through 31, no. The balanced input is made to the 32 terminals. The VHF band television signal passes through the VHF tuning circuit 75 and is No. It is input to 29 terminals. The VHF tuning circuit 75 has a switch diode 75a inside, and is switched to tune to low band or high band by turning on or off the switch diode. The intermediate frequency tuning circuit 76 has an input terminal No. 26, no. 27 and the output terminal is No. 27. 21, no. 22 terminals.
[0009]
The low-band resonance circuit 77 has a varactor diode 77a, and one end of the low-band resonance circuit 77 is connected to each of the No. 1, no. 2 is coupled to the other terminal and grounded at the other end. The high-band resonance circuit 80 also has a varactor diode 80a, one end of which is connected to each of the No. 4, no. 5 is coupled to the terminal. Further, the UHF resonance circuit 83 also has a varactor diode 83a, and one end of the UHF resonance circuit 83 is connected to each of the no. 6, no. 7 is coupled to the terminal. The other end is connected to a No. 8, no. 9 is coupled to the terminal. The oscillation element 88 such as a crystal resonator is No. 16 terminals are connected.
[0010]
In the above configuration, no. The tuning voltage output from the terminal 15 is applied to the cathodes of the varactor diodes 77a, 80a and 83a of the resonance circuits 77, 80 and 83, and the oscillation circuits 63 to 65 oscillate at a frequency required for each reception band. . No. 23 and no. The switching voltage output from the 24 terminals is applied to the VHF tuning circuit 75 to turn on or off the switch diode 75a. When off, the VHF tuning circuit 75 tunes to the low band of the VHF band, and when on, it tunes to the high band. Furthermore, no. The switching voltage output from the terminal 30 is applied to the UHF high-frequency amplifier circuit 73. When a UHF band television signal is received, the switching voltage is set to a high level to operate the UHF high frequency amplifier circuit 73 in an appropriate bias state, and when a VHF band television signal is received, the UHF high frequency amplifier circuit 73 is set to a low level. Stop the operation.
[0011]
As described above, the intermediate frequency signal is output from each of the mixing circuits 61 and 62 corresponding to each reception band, and after passing through the intermediate frequency tuning circuit 76 and the intermediate frequency amplification circuit 72, No. 2 is output. 11, no. 12 terminals are balanced and output. The output intermediate frequency signal IF is processed by a demodulation circuit or the like (not shown).
[0012]
[Problems to be solved by the invention]
In the conventional integrated circuit described above, many terminals are used to couple the resonance circuit to the oscillation circuit. Further, the number of terminals for taking out the switching voltage from the band switching voltage generation circuit is large, and the number of terminals to be grounded is also large. For this reason, connection with peripheral circuits becomes complicated, and the integrated circuit itself cannot be miniaturized. Further, it has been impossible to reduce the size of a television tuner using an integrated circuit.
[0013]
An object of the present invention is to form necessary circuits in an integrated circuit and reduce the number of terminals.
[0014]
[Means for Solving the Problems]
In order to solve the above-described problems, in the present invention, a UHF band television is provided via a switching voltage generation circuit and a UHF high-frequency amplifier circuit that is provided outside and is switched to an operating state when receiving at least a UHF band television signal. A first terminal to which a signal is input, and a second terminal for switching a VHF tuning circuit provided outside to be tuned to a low band or a high band of the VHF band, and the switching voltage generating circuit Has a first switch circuit that generates a switching voltage for switching the operating state of the UHF high-frequency amplifier circuit, and a second switch circuit that generates a switching voltage for switching the band of the VHF tuning circuit, The switching voltage of the first switch circuit is output to the first terminal, and the switching voltage of the second switch circuit is output to the second terminal. It was.
[0015]
A first two oscillation transistors whose emitters are connected to each other; a second two oscillation transistors whose emitters are connected to each other; a third two oscillation transistors whose emitters are connected to each other; A third terminal to which one end of the first resonance circuit provided outside is connected, a fourth terminal and a fifth terminal to which both ends of the second resonance circuit provided outside are respectively connected, and the outside Sixth and seventh terminals respectively connected to both ends of the third resonance circuit provided, and one base and the other collector of the first two oscillation transistors are respectively connected by individual coupling capacitors. Coupled to the third terminal, one base and the other collector of the second two oscillating transistors are coupled to the fourth terminal by respective coupling capacitors, The other base and one collector of the second two oscillation transistors are respectively coupled to the fifth terminal by separate coupling capacitors, and one base and the other collector of the third two oscillation transistors are connected to each other. Each of the second two oscillation transistors is coupled to the sixth terminal by an individual coupling capacitor, and the other base and one collector of the second two oscillation transistors are coupled to the seventh terminal by an individual coupling capacitor.
[0016]
An intermediate frequency amplifier circuit; and an eighth terminal for outputting an intermediate frequency signal. The intermediate frequency amplifier circuit is configured in a balanced input type and an unbalanced output type, and an output terminal of the intermediate frequency amplifier circuit is connected to the output terminal. Connected to the eighth terminal.
[0017]
Also provided outside The A ninth terminal to which a balanced output terminal of an intermediate frequency tuning circuit is connected; and the intermediate frequency tuning circuit includes a trap circuit for attenuating a video intermediate frequency signal or an audio intermediate frequency signal of an adjacent channel, and the trap circuit The switching voltage generation circuit is provided with a third switch circuit for generating a switching voltage for switching the trap frequency, and the switching voltage of the third switch circuit is set to the first switching frequency. Output to 9 terminals.
[0018]
A fourth switch for outputting a high-level or low-level voltage to the switching voltage generation circuit, the analog-digital conversion circuit; and a tenth terminal for inputting an analog voltage to the analog-digital conversion circuit. A circuit, and opening / closing means interposed between the tenth terminal and the fourth switch circuit, and the analog ・ The open / close means is opened when the digital conversion circuit is operated, and the open / close means is closed when the fourth switch circuit is operated.
[0019]
The eleventh terminal includes a PLL circuit, a reference oscillation circuit that supplies a reference signal to the PLL circuit, and an eleventh terminal that connects an externally provided oscillation element to the reference oscillation circuit. Terminals having a low potential in terms of high frequency were provided on both sides.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a tuner integrated circuit according to the present invention will be described with reference to FIGS. Here, FIG. 1 shows a circuit configuration and terminal arrangement of a tuner integrated circuit (hereinafter referred to as an integrated circuit) of the present invention, and the overall connection relationship with its peripheral circuits, and FIGS. 2 and 3 show a detailed configuration. Show.
[0021]
As shown in FIG. 1, the integrated circuit 10 of the present invention has twelve terminals on two opposite sides (numbers in circles indicate terminal numbers (No.)).
No. 1 to No. No. 12 terminals are provided on one side 10a. 13 to No. Up to 24 terminals are provided on the other side 10b. In addition, a plurality of circuits as shown schematically are configured inside. The UHF mixing circuit 11 is No. whose balanced input terminal is the first terminal. No. 23 terminal, 24, and the VHF mixing circuit 12 has an unbalanced input terminal of No. 24. 22 terminals. The balanced output terminals of the mixing circuits 11 and 12 are No. 19, no. It is connected to 20 terminals.
[0022]
A local oscillation signal is supplied to the VHF mixing circuit 12 from two oscillation circuits, that is, a VHF low-band oscillation circuit (hereinafter referred to as a low-band oscillation circuit) 13 and a VHF high-band oscillation circuit (hereinafter referred to as a high-band oscillation circuit) 14. The low-band oscillation circuit 13 is an unbalanced type, and the resonance circuit coupling end is a third terminal. 1 terminal. Further, the high-band oscillation circuit 14 is a balanced type, and the two resonance circuit coupling ends are the fourth terminals, respectively. No. 2 terminal and No. 5 terminal. 3 terminals. A local oscillation signal is supplied from the UHF oscillation circuit 15 to the UHF mixing circuit 11. The UHF oscillation circuit 15 is also of a balanced type, and the two resonance circuit coupling ends are No. 6 each having a sixth terminal. No. 4 terminal and No. 7 terminal. 5 is connected.
[0023]
No. 14 to No. Reception terminal selection data and the like are input to a terminal 16 from a television receiver main body (not shown). Specifically, channel No. 14 data, band switching data, etc. are input to the No. 14 terminal. The clock signal is input to the terminal 15 and the address data is input to the terminal No. 16. These data are input to the PLL circuit 17 and the switching voltage generation circuit 18 through the interface 16. No. 10 as the tenth terminal. An analog / digital conversion circuit (hereinafter referred to as an A / D conversion circuit) 19 is connected to 13 terminals. The A / D conversion circuit 19 transmits / receives data to / from the interface 16.
[0024]
The PLL circuit 17 receives reception channel selection data and local oscillation signals output from the oscillation circuits 13, 14, and 15. The error signal output from the PLL circuit 17 is DC-converted by the charge pump 20 having a low-pass filter. The tuning voltage is output to 10 terminals. The reference signal is input from the reference oscillation circuit 22 to the PLL circuit 17. The resonance element connection end of the reference oscillation circuit 22 is the eleventh terminal No. 11. 7 terminal.
[0025]
The switching voltage generation circuit 18 has a plurality of switch circuits therein, and generates a switching voltage of a high level or a low level according to the input band switching data. This switching voltage is used for switching the band to be received, and the tenth terminal (No. 13), the second terminal (No. 17), the ninth terminal (No. 18), and the first terminal (No. 23).
The intermediate frequency amplifier circuit 23 is configured as a balanced input type or an unbalanced output type. 11 and the other input terminal is connected to the terminal No. 18 which is the eighth terminal.
In addition, No. 6, no. No. 21 terminal is grounded. A power supply voltage B to be supplied to each circuit is applied to the terminal 8.
[0026]
A peripheral circuit provided outside is connected to the integrated circuit 10. The UHF band television signal passes through the UHF high frequency amplifier circuit 24, the UHF tuning circuit 25, etc., and the first terminal (No. 23). The balanced input is made to 24 terminals. At this time, the UHF high-frequency amplifier circuit 24 is controlled to operate by the switching voltage appearing at the first terminal (No. 23). The VHF band television signal passes through the VHF tuning circuit 26 and is No. 22 input. The VHF tuning circuit 26 includes an input tuning circuit and an interstage tuning circuit, and has a switch diode 26a inside. The switch diode 26a is switched on or off by the switching voltage output from the second terminal (No. 17), whereby the VHF tuning circuit 26 is switched to tune to the low band or high band of the VHF band. The intermediate frequency tuning circuit 27 is a balanced type, and its input terminal is No. 19, no. 20 is connected to one of the output terminals, and one of the output terminals is connected to the ninth terminal (No. 18). 11 terminals (indicated by A).
[0027]
The first resonance circuit 28 is used at the time of low band reception in the VHF band, one end of which is coupled to the third terminal (No. 1) and the other end is grounded. The second resonant circuit 29 is VHF band Is connected to the fourth terminal (No. 2) and the other end is connected to the fifth terminal (No. 3). Further, the third resonance circuit 30 is used when receiving the UHF band, and one end thereof is connected to the sixth terminal (No. 4) and the other end is coupled to the seventh terminal (No. 5). Each resonance circuit 28, 29, 30 is provided with a varactor diode for changing the resonance frequency. No. for varactor diodes. A tuning voltage is applied from 10. No. A high voltage (higher than the maximum value of the tuning voltage) V is applied to the 10 terminals via the pull-up resistor 32. The resonant element 31 such as a crystal resonator is connected to the eleventh terminal (No. 7). Therefore, both sides of the seventh terminal (No. 7) to which the resonant element 31 is connected are grounded at high frequency. 6 and no. No. 8 low potential terminal is arranged, and the reference signal radiation appearing at the eleventh terminal (No. 7) is No. 8. 6 and no. The effect which can be prevented by the terminals of 8 is obtained.
[0028]
In the above configuration, the UHF band television signal or the VHF band television signal is converted into an intermediate frequency signal by the UHF mixing circuit 11 and the VHF mixing circuit 12, respectively, and the intermediate frequency signal is converted to the intermediate frequency tuning circuit 27 and the intermediate frequency amplification. An unbalanced output is made to the terminal of the eighth terminal (No. 12) via the circuit 23. The output intermediate frequency signal IF is processed by a demodulation circuit or the like (not shown).
[0029]
Here, a specific configuration of each of the oscillation circuits 13 to 15 and each of the resonance circuits 28 to 30 and a connection relationship with other related circuits will be described with reference to FIG. The low-band oscillation circuit 13 has first differential two oscillation transistors 13a and 13b whose emitters are connected to each other, and the base of one oscillation transistor 13a and the collector of the other oscillation transistor 13b are connected to the resonance circuit coupling end. And coupled to the third terminal (No. 1) via coupling capacitors 13c and 13d, respectively. The base of the other oscillation transistor 13b is grounded in terms of high frequency. The third terminal (No. 1) has a diode 13e. of The cathode is connected and the anode is grounded.
[0030]
The high-band oscillation circuit 14 also has differential second oscillation transistors 14a and 14b whose emitters are connected to each other, and the base of one oscillation transistor 14a and the collector of the other oscillation transistor 14b are in one resonance. It becomes a circuit coupling end and is connected to the fourth terminal (No. 2) via coupling capacitors 14c and 14d, respectively. The base of the other oscillation transistor 14b and the collector of the one oscillation transistor 14a serve as the other resonance circuit coupling end, and are coupled to the fifth terminal (No. 3) via coupling capacitors 14f and 14e, respectively. The cathode of the diode 14g is connected to the fourth terminal (No. 2), and the anode is grounded. The cathode of the diode 14h is connected to the fifth terminal (No. 3), and the anode is grounded.
[0031]
Further, the UHF oscillation circuit 15 also has differential third oscillation transistors 15a and 15b whose emitters are connected to each other, and the base of one oscillation transistor 15a and the collector of the other oscillation transistor 15b are one of them. The resonance circuit coupling end is connected to the sixth terminal (No. 4) via coupling capacitors 15c and 15d, respectively. The base of the other oscillation transistor 15b and the collector of the one oscillation transistor 15a serve as the other resonance circuit coupling end, and are coupled to the seventh terminal (No. 5) via coupling capacitors 15f and 15e, respectively. Further, the cathode of the diode 15g is connected to the sixth terminal (No. 4), and the anode is grounded. The cathode of the diode 15h is connected to the seventh terminal (No. 5), and the anode is grounded.
[0032]
As described above, since the resonance circuit coupling end of each oscillation circuit is connected to each terminal via the coupling capacitor, the number of terminals is greatly reduced.
[0033]
The cathodes of the varactor diodes 28a and 29a30a provided in the first resonance circuit 28, the second resonance circuit 29, and the third resonance circuit 30, respectively, are No. 10 terminals.
[0034]
A tuning voltage generation circuit 21 to which a DC voltage is input from the charge pump 20 has a junction FET 21a and an NPN transistor 21b. The source is connected to the collector of the NPN transistor 21b. The junction FET 21a and the NPN transistor 21b function as variable resistance means. The emitter of the NPN transistor 21b is grounded by the resistor 21d.
[0035]
The impedance ratio between the tuning voltage generation circuit 21 and the pull-up resistor 32 varies depending on the voltage output from the charge pump 20. Ten terminals generate a tuning voltage in the range of approximately 2 volts to 25 volts. This voltage is applied to each varactor diode 28a, 29a, 30a.
[0036]
A temperature compensation circuit 41 is provided between the connection point between the junction FET 21a and the NPN transistor 21b and the cathodes of the diodes 13e, 14h, and 15h provided in the resonance circuits 13, 14, and 15, respectively (shown in FIG. 1). Not) The temperature compensation circuit 41 includes a junction FET 41a, its drain, The source of the junction FET 41a is connected to the collector of the NPN transistor 21b in the tuning voltage generating circuit 21. The junction FET 41a functions as variable resistance means. A voltage obtained by dividing the power supply voltage (here, referred to as a temperature compensation voltage) appears at the connection point between the two resistors 41b and 41c, which are respectively connected to the diodes 13e, 14h, and 15h via the resistors 13f, 14i, and 15i. Applied to the cathode.
[0037]
In the above configuration, the capacitance values of the varactor diodes 28a, 29a, 30a and the diodes 13e, 14h, 15h have a positive temperature coefficient, and the capacitance value increases as the temperature rises. Therefore, the oscillation frequency changes to the lower side. Then, the voltage input from the charge pump 20 to the NPN transistor 21b of the tuning voltage generating circuit 21 is lowered by the action of the PLL circuit 17, and the voltage between the collector and the emitter of the NPN transistor 21b is increased. The tuning voltage appearing at the terminal 10 also rises and works to restore the oscillation frequency. At this time, the voltage at the connection point of the two resistors 41b and 41c in the temperature compensation circuit 41 also increases. Therefore, the voltage applied to the cathodes of the diodes 13e, 14h, and 15h is higher than the conventional voltage.
[0038]
In general, since the capacitance value between terminals of the diode decreases as the reverse bias voltage increases, the diodes 13e, 14h, and 15h also have an effect of suppressing a change in oscillation frequency. Therefore, the change in the tuning voltage for returning the changed oscillation frequency to the original value can be reduced.
[0039]
Next, a specific connection relationship between the switching voltage generation circuit 18 and another circuit to which the switching voltage is applied will be described with reference to FIG.
First, the switching voltage generation circuit 18 in the integrated circuit 10 includes switch circuits 18a to 18e made of transistors (in this example, all NPN transistors), and the emitters of the transistors in the first switch circuit 18a are the first ones. It is connected to a terminal (No. 23) and grounded through a resistor. The base of the transistor 18b is connected to the base of the transistor in the first switch circuit 18a, the collector is connected to the collector of the transistor in the second switch circuit 18c, and the emitter is grounded.
[0040]
The collector of the transistor in the second switch circuit 18c is connected to the second terminal (No. 17), and the emitter is grounded. The emitter of the transistor in the third switch circuit 18d is connected to the ninth terminal (No. 18) and grounded through a resistor. The collector of the transistor in the fourth switch circuit 18e is connected to the tenth terminal (No. 13) via the switching means 18f, and the emitter is grounded. Although the configuration of the opening / closing means 18f is not described in detail, it can be configured by another switch transistor or the like. The collectors of the transistors in the switch circuits 18a and 18d are No. 8 terminals. An ON / OFF control signal is input from each interface 16 to each base. The opening / closing means 18 f is also controlled by the interface 16.
[0041]
Next, the A / D conversion circuit 19 has a No. The power supply voltage is supplied from the terminal 8 through the resistor 51, and the tenth terminal (No. 13) is connected through the resistor 51. 8 terminals. The operation / non-operation of the A / D conversion circuit 19 is controlled by the interface 16. Also, the ninth terminal (No. 18) and No. The 19 terminals are coupled together by a capacitor 52. No. A direct current cut capacitor 53 is interposed between the 18 terminals and the other input terminal of the intermediate frequency amplifier circuit 23. Further, the ninth terminal (No. 18) has No. The power supply voltage is supplied from the terminal 8 through the resistor 54.
[0042]
The UHF high-frequency amplifier circuit 24 is composed of an FET (field effect transistor), and a UHF band television signal is input to the first gate thereof. The amplified television signal is input to the first terminal (No. 23) through the UHF tuning circuit 25 and is also passed through the inductance element 55 for phase inversion. It is input to 24 terminals. Therefore, the first terminal (No. 23) and No. A television signal is balanced between 24 terminals. The first gate is connected to one end of a resonance inductance element 56 and the other end is grounded by a resistor 57. The connection point between the resonant inductance element 56 and the resistor 57 is No. 5 by the resistor 58. 24 terminals are connected.
[0043]
A power supply voltage is supplied to the anode of the switch diode 26a in the VHF tuning circuit 26, and its cathode is connected to the second terminal (No. 17) in a DC manner.
The intermediate frequency tuning circuit 27 is No. 19, no. 20, a parallel tuning circuit 27 a to which an intermediate frequency signal is input to both ends, one end of the parallel tuning circuit 27, and No. 20 terminal. 11 and a second trap circuit 27c interposed between the other end and the ninth terminal (No. 18). The second trap circuit 27c is provided with a varactor diode Dv, and a power supply voltage is applied to its cathode. The anode is connected to the ninth terminal (No. 18). Therefore, the capacitor 52 is connected in parallel to the varactor diode Dv in the second trap circuit 27c. These trap circuits 27b and 27c attenuate the video intermediate frequency signal of one adjacent channel in the intermediate frequency band and attenuate the audio intermediate frequency signal of the other adjacent channel.
[0044]
In the above configuration, when receiving a low-band television signal in the VHF band, the transistors of the first to third switch circuits 18a, 18b, and 18c are turned off. Then, the switching voltage of the first terminal (No. 23) becomes low level, and the UHF high frequency amplifier circuit 24 does not operate because no bias voltage is applied to the first gate. On the other hand, since the switching voltage of the second terminal (No. 17) is at a high level, the VHF tuning circuit 26 is tuned to the low band by turning off the switch diode 26a. When a high-band television signal is received, the transistor of the first switch circuit 18a and the transistor 18b are turned off, and the transistor of the second switch circuit 18c is turned on. Then, the switching voltage of the second terminal (No. 17) becomes low level, and the VHF tuning circuit 26 is tuned to the high band because the switch diode 26a is turned on. When a UHF band television signal is received, the transistor of the first switch circuit 18a and the transistor 18b are turned on, and the transistor of the second switch circuit 18c is turned off. Then, the switching voltage of the first terminal (No. 23) becomes high level, and the UHF high-frequency amplifier circuit 24 operates with a bias voltage applied to the first gate.
[0045]
Therefore, the first terminal (No. 23) is used not only as an input terminal for a UHF band television signal but also as an output terminal for a switching voltage for the switch circuit 18a for switching the operation of the UHF high-frequency amplifier circuit 24. The
Furthermore, the tuning frequency band of the VHF tuning circuit 26 can be switched only by the switching voltage of the second terminal (No. 17).
Therefore, it is possible to reduce the number of terminals that output a switching voltage for switching the reception band.
[0046]
On the other hand, the switching voltage of the ninth terminal (No. 18) is the ON or OFF state of the transistor in the third switch circuit 18d. off To change to high level or low level. Correspondingly, the capacitance value of the varactor diode Dv in the second trap circuit 27c changes to change the trap frequency to high or low. Therefore, an appropriate trap frequency can be selected corresponding to two types of television signals in which the difference between the video intermediate frequency and the audio intermediate frequency is different. Therefore, since the ninth terminal (No. 18) to which the intermediate frequency signal is input can be used as the switching voltage output terminal of the third switch circuit 18d, the trap frequency can be changed without increasing the number of terminals.
[0047]
When the opening / closing means 18f is closed, the switching voltage of the fourth switch circuit 18e can be output to the tenth terminal (No. 13). When an analog voltage such as an AFT (automatic fine tuning) voltage is input to the tenth terminal (No. 13) with the opening / closing means 18f open, a digital signal is output from the A / D conversion circuit 19 to the interface 16. Can send. The digital signal is sent from the interface 16 to the PLL circuit 17, and the oscillation frequency of each oscillation circuit 13, 14, 15 is controlled by the PLL circuit 17. Therefore, the tenth terminal (No . 13) serves not only as an analog voltage input terminal but also as a switching voltage output terminal of the fourth switch circuit 18e. The Can also be shared.
[0048]
【The invention's effect】
As described above, according to the present invention, the UHF band television signal is input via the UHF high-frequency amplifier circuit that is provided outside and is switched to the operation state at least when receiving the UHF band television signal. And a second terminal for switching the VHF tuning circuit provided outside to tune to the low band or high band of the VHF band, and the switching voltage generation circuit changes the operating state of the UHF high frequency amplifier circuit. A first switch circuit that generates a switching voltage for switching and a second switch circuit that generates a switching voltage for switching a band of the VHF tuning circuit; Since the switching voltage of the second switch circuit is output to the second terminal, even if the number of terminals is reduced, the low band of the VHF band You can receive Ibando and UHF band.
[0049]
Also, a third terminal to which one end of the first resonance circuit provided outside is connected, and fourth and fifth terminals to which both ends of the second resonance circuit provided outside are respectively connected, Sixth and seventh terminals to which both ends of a third resonance circuit provided outside are respectively connected, and one base capacitor and the other collector of each of the first two oscillation transistors are individually coupled capacitors. Is coupled to the third terminal, and one base and the other collector of the second two oscillation transistors are coupled to the fourth terminal by respective coupling capacitors, and the other of the second two oscillation transistors is coupled to the other terminal. The base and one collector are respectively coupled to the fifth terminal by individual coupling capacitors, and one base and the other collector of the third two oscillation transistors are coupled to individual coupling capacitors. Since the second base and one collector of the second two oscillation transistors are coupled to the seventh terminal by separate coupling capacitors, respectively, to form three oscillation circuits. The number of terminals can be reduced.
[0050]
An intermediate frequency amplifier circuit; and an eighth terminal for outputting an intermediate frequency signal. The intermediate frequency amplifier circuit is configured as a balanced input type and an unbalanced output type, and the output terminal of the intermediate frequency amplifier circuit is connected to the eighth terminal. Since it is connected to the terminal, the number of terminals can be reduced.
[0051]
In addition, it has a ninth terminal which is provided outside and to which the balanced output terminal of the intermediate frequency tuning circuit is connected, and the intermediate frequency tuning circuit has a trap circuit for attenuating the video intermediate frequency signal or the audio intermediate frequency signal of the adjacent channel. In addition, the trap frequency of the trap circuit is configured to be switched, and the switching voltage generation circuit is provided with a third switch circuit that generates a switching voltage for switching the trap frequency, and the switching voltage of the third switch circuit is Since it is output to the nine terminals, the trap frequency can be switched without increasing the number of terminals.
[0052]
An analog / digital conversion circuit; and a tenth terminal for inputting an analog voltage to the analog / digital conversion circuit; and a fourth voltage switch circuit for outputting a high level or low level voltage to the switching voltage generation circuit; And an open / close means interposed between the tenth terminal and the fourth switch circuit. When the analog / digital conversion circuit is operated, the open / close means is opened and the fourth switch circuit is operated. Since the opening / closing means is sometimes closed, one terminal can be shared by the analog voltage input terminal and the switching voltage output terminal.
[0053]
Further, a PLL circuit, a reference oscillation circuit for supplying a reference signal to the PLL circuit, and an eleventh terminal for connecting an externally provided oscillation element to the reference oscillation circuit are provided, and a high frequency is provided on both sides of the eleventh terminal. Since a terminal having a low potential is provided, the radiation of the reference signal appearing at the eleventh terminal can be prevented by the terminals on both sides.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a tuner integrated circuit according to the present invention.
FIG. 2 is a detailed connection diagram of an oscillation circuit and its peripheral circuits in the tuner integrated circuit of the present invention.
FIG. 3 is a detailed connection diagram of a band switching voltage generation circuit and its peripheral circuits in the tuner integrated circuit of the present invention.
FIG. 4 is a block diagram showing a configuration of a conventional tuner integrated circuit.
[Explanation of symbols]
10 Integrated circuits
10a, 10b side
11 UHF mixing circuit
12 VHF mixing circuit
13 VHF low-band oscillator
i3a, 13b Oscillation transistor
13c, 13d coupling capacitors
13e diode
13f resistance
14 VHF high-band oscillator
14a, 14b Oscillation transistor
14c, 14d, 14e, 14f Coupling capacitors
14g, 14h diode
14i resistance
15 UHF oscillation circuit
15a, 15b Oscillation transistor
15c, 15d, 15e, 15f Coupling capacitor
15g, 15h diode
15i resistance
16 interface
17 PLL circuit
18 Switching voltage generator
18a First switch circuit
18b transistor
18c Second switch circuit
18d Third switch circuit
18e Fourth switch circuit
18f Opening / closing means
19 Analog-digital conversion circuit
20 Charge pump
21 Tuning voltage generator
21a Junction FET
21b NPN transistor
21c, 21d resistance
22 Reference oscillation circuit
23 Intermediate frequency amplifier
24 UHF high frequency amplifier circuit
25 UHF tuning circuit
26 VHF tuning circuit
27 Intermediate Frequency Tuning Circuit
28 First resonant circuit
28a Varactor diode
29 Second resonant circuit
29a Varactor diode
30 Third oscillator circuit
30a Varactor diode
31 Resonator
32 Pull-up resistor
41 Temperature compensation circuit
41a Junction FET
41b, 41c resistance
51, 54, 57, 58 Resistance
52, 53 capacitors
55, 56 Inductance element
No. 23 First terminal
No. 17 Second terminal
No. 1 Third terminal
No. 2 4th terminal
No. 3 Fifth terminal
No. 4 Sixth terminal
No. 5 Seventh terminal
No. 12 Eighth terminal
No. 18 Ninth terminal
No. 13 Tenth terminal
No. 7 Eleventh terminal

Claims (6)

  A switching voltage generating circuit; a first terminal that is provided outside and receives a UHF band television signal via a UHF high-frequency amplifier circuit that is switched to an operating state when receiving at least a UHF band television signal; And a second terminal for switching the band so that the VHF tuning circuit is tuned to a low band or a high band of the VHF band, and the switching voltage generation circuit is for switching the operating state of the UHF high-frequency amplifier circuit. And a second switch circuit that generates a switching voltage for switching the band of the VHF tuning circuit, and the switching voltage of the first switch circuit is set to the first switching circuit. Output to one terminal, and the switching voltage of the second switch circuit is output to the second terminal. .   A first two oscillation transistors whose emitters are connected to each other; a second two oscillation transistors whose emitters are connected to each other; a third two oscillation transistors whose emitters are connected to each other; A third terminal to which one end of the provided first resonance circuit is connected; a fourth and fifth terminal to which both ends of the second resonance circuit provided outside are respectively connected; and an outside. And a sixth terminal and a seventh terminal to which both ends of the third resonance circuit are respectively connected, and one base and the other collector of the first two oscillation transistors are respectively connected to the first resonance circuit by separate coupling capacitors. Three base terminals, one base and the other collector of the second two oscillation transistors are respectively coupled to the fourth terminal by individual coupling capacitors, and the second terminal The other base and one collector of the two oscillation transistors are respectively coupled to the fifth terminal by individual coupling capacitors, and one base and the other collector of the third two oscillation transistors are individually coupled to each other. A coupling capacitor is coupled to the sixth terminal, and the other base and one collector of the second two oscillation transistors are coupled to the seventh terminal by individual coupling capacitors, respectively. Item 12. The tuner integrated circuit according to Item 1.   An intermediate frequency amplifier circuit; and an eighth terminal for outputting an intermediate frequency signal. The intermediate frequency amplifier circuit is configured as a balanced input type and an unbalanced output type, and an output terminal of the intermediate frequency amplifier circuit is connected to the eighth terminal. The tuner integrated circuit according to claim 1, wherein the tuner integrated circuit is connected to a terminal of the tuner. A ninth terminal to which a balanced output terminal of an intermediate frequency tuning circuit provided externally is connected, and the intermediate frequency tuning circuit has a trap circuit for attenuating the video intermediate frequency signal or the audio intermediate frequency signal of the adjacent channel. In addition, the trap frequency of the trap circuit is configured to be switched, and the switching voltage generation circuit is provided with a third switch circuit for generating a switching voltage for switching the trap frequency, tuner integrated circuit according to any one of claims 1 to 3, characterized in that the switching voltage is output to the ninth terminal. An analog / digital conversion circuit; and a tenth terminal for inputting an analog voltage to the analog / digital conversion circuit; and a fourth switch circuit for outputting a high level or low level voltage to the switching voltage generation circuit; An open / close means interposed between the tenth terminal and the fourth switch circuit, and when the analog / digital conversion circuit is operated, the open / close means is opened, and the fourth switch 5. The tuner integrated circuit according to claim 1, wherein the opening / closing means is closed when the circuit is operated.   A PLL circuit, a reference oscillation circuit for supplying a reference signal to the PLL circuit, and an eleventh terminal for connecting an externally provided oscillation element to the reference oscillation circuit are provided on both sides of the eleventh terminal. 6. The tuner integrated circuit according to claim 1, wherein a terminal having a low potential in terms of high frequency is provided.

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