JPH08316315A - Semiconductor device and its production - Google Patents

Abstract

PURPOSE: To suppress the generation of stress by making an etching stopper layer thin. CONSTITUTION: This device has such a multilayer wiring structure that interlayer insulation films 2, 5 and 10 and wiring layers 4, 9a and 9b are piled up alternately, and interlayer insulation films 2 and 5 having etching stopper layers 3 and 6 for etching for a joint hole opening are formed between a wiring layer connecting by joint holes 7 and 11 and a wiring layer thereunder. In addition, the layers 3 and 6 are formed of silicon nitride film, and the films 5 and 10 are etched at a high selectivity against the silicon nitride film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, for example, a highly miniaturized and integrated semiconductor device and a method of manufacturing the same, and in particular, integration of a memory element having advanced fine integration. It can be used for a semiconductor circuit and a manufacturing method thereof.

[0002]

2. Description of the Related Art With the miniaturization of semiconductor devices, multi-layer wiring structures are often used in integrated semiconductor circuits such as memory devices. The conventional multilayer wiring structure is shown in FIG.
As shown in (B), a structure is adopted in which the width of the wiring layer 9 is increased only in the region where the connection hole 11 for connecting the wiring layer 9 and the upper wiring layer is formed. In this type of multilayer wiring structure, even if misalignment occurs in the photolithography patterning for opening the connection hole 11, FIG.
As shown in (C), since the width of the wiring layer 9 in the region where the connection hole 11 is formed is wider than that in other regions, the connection hole 11 is formed in the wiring layer 9 where the connection hole 11 is to be formed. Then, the opening of the connection hole 11 is etched and the lower wiring layer 4 is etched.
There was no problem of reaching.

However, if an attempt is made to bring the width of the wiring layer closer to the diameter of the contact hole in order to increase the degree of integration, and if misalignment occurs in the photolithography patterning for opening the contact hole, the contact hole is formed as shown in FIG. There is a problem that the connection hole 11 reaches the lower wiring layer 4 during overetching of the opening etching, and a short circuit occurs between the wiring layer 9 and the lower wiring layer 4.

Therefore, a multilayer wiring structure has been proposed in which an etching stopper layer for etching the opening of the connection hole is formed between the wiring layer in which the connection hole is to be formed and the wiring layer below the wiring layer (for example, Japanese Unexamined Patent Application Publication No. 2003-242242). 63-136,6
No. 47).

[0005]

However, in the multilayer wiring structure disclosed in Japanese Unexamined Patent Publication No. 63-136,647, the silicon nitride film forming the etching stopper layer is 100 to 500 angstroms (first layer insulation). The film thickness is as thick as about 10% of the film thickness), and there is a problem that stress is generated between the silicon nitride film and the wiring layer formed on the upper side, and the wiring layer is damaged or broken.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a highly integrated semiconductor device capable of suppressing the generation of stress by thinning the etching stopper layer, and a manufacturing method thereof.

[0007]

In order to achieve the above object, a semiconductor device according to the present invention comprises a first etching stopper layer and a first pattern having a predetermined pattern laminated on the first etching stopper layer. Wiring layer, an interlayer insulating film that covers the first etching stopper layer and the first wiring layer, and has a selective ratio with respect to the first etching stopper layer, and is laminated on the interlayer insulating film. A second etching stopper layer, a connection hole formed in the second etching stopper layer and the interlayer insulating film and facing the first wiring layer, a wiring material embedded in the connection hole, and the second etching A second wiring layer formed on the stopper layer and connected to the wiring material,
The width of the first wiring layer is a constant width substantially equal to the width of the connection hole.

It is preferable that the first and second etching stopper layers are made of a silicon nitride film.
In order to achieve the above object, a method for manufacturing a semiconductor according to the present invention comprises a step of forming a first etching stopper layer, and a step of forming a first wiring layer having a predetermined pattern on the first etching stopper layer. And a step of forming an interlayer insulating film having a selection ratio with respect to the first etching stopper layer so as to cover the first etching stopper layer and the first wiring layer, and the interlayer insulating film. A step of forming a second etching stopper layer on the film, and forming a connection hole facing the first wiring layer in the second etching stopper layer and the interlayer insulating film in the first etching stopper layer. On the other hand, under the condition of a high selection ratio, the step of forming by etching, the step of embedding a wiring material in the connection hole, and the wiring on the second etching stopper layer. And forming a second wiring layer connected to the charge.

In this case, at least C ₄ F ₈ gas and CO gas are used as etching gas, and the flow rate ratio of this etching gas is set to CO gas / C ₄ F ₈ gas> 0.5.
The etching is preferably performed under a pressure of 30 Pa or less and a high frequency power of 900 W or more.

In the present invention, when the lower wiring has a high heat resistance, for example, made of a refractory metal, it is preferable to use a silicon nitride film formed by LP (low pressure) CVD as the etching stopper layer, and the wiring is heat resistant. When it is made of aluminum metal, which has a low property, it is preferable to use a silicon nitride film formed by plasma CVD as an etching stopper layer.

Further, it is preferable to use, for the interlayer insulating film, a silicon oxide film or a doped silicon oxide film formed by CVD, for example, as a film having an etching rate faster than that of the silicon nitride film.

[0012]

In the semiconductor device of the present invention, since the etching stopper layer is present when forming the connection hole formed for connecting the second wiring layer and the first wiring layer below the second wiring layer, the connection is made. Even if misalignment occurs in the patterning of the photoresist of the holes, the holes are not etched deeper than the etching stopper layer at the time of overetching in the etching of the connection holes, and the connection holes do not reach the wirings below the etching stopper layer. Therefore, a short circuit between wiring layers can be prevented. In combination with this, in the semiconductor device of the present invention, the width of the lower wiring layer is set to a constant width which is almost equal to the width of the connection hole, so that the wiring interval can be shortened and the degree of integration can be increased. You can

In the method of manufacturing a semiconductor device of the present invention for manufacturing this semiconductor device, the etching stopper layer is made of, for example, a silicon nitride film, and the interlayer insulating film is etched with a high selectivity with respect to the silicon nitride film. Therefore, the etching stopper layer composed of a silicon nitride film or the like can be thinned. As a result, it is possible to suppress the generation of stress caused by the etching stopper layer,
It is possible to prevent the wiring layer formed on the upper part from being damaged or broken.

With the above operation, it is possible to satisfactorily manufacture memory devices such as SRAMs and DRAMs that require a multilayer wiring structure and logic devices such as ASICs.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. 1 is a plan view showing a semiconductor device of this embodiment, and FIG. 3H is a sectional view taken along the line AB in FIG.

In the semiconductor device of this embodiment, although not shown, a transistor is formed on a silicon substrate 1, and a first interlayer insulating film 2 is formed on the substrate 1. A connection hole 7 is formed on the first interlayer insulating film 2.
The first silicon nitride film 3 serving as the etching stopper layer is formed. The first silicon nitride film 3 of this embodiment is formed as a thin film having a thickness of about 0.010 to 0.070 μm. This is because the second interlayer insulating film 5 is etched with a high selectivity with respect to the first silicon nitride film 3 when the second interlayer insulating film 5 to be described later is etched to open the connection hole 7. This makes it possible to reduce the thickness of the first silicon nitride film 3 to about 0.01 to 0.07 μm, and as a result, the first silicon nitride film 3 and the first silicon nitride film 3 can be made thinner.
It is possible to suppress the stress generated between the first wiring layer 4 and the first wiring layer 4 and prevent the first wiring layer 4 from being damaged or broken. The first interlayer insulating film 2 is composed of, for example, a silicon oxide film, a PSG film, a BPSG film formed by a CVD method.

A first wiring layer 4 made of aluminum is formed on the upper part of the first silicon nitride film 3, and the first silicon nitride film 3 other than the upper part of the first wiring layer 4 is formed. A second interlayer insulating film 5 is formed on the upper part of the. A second silicon nitride film 6 similar to the above-mentioned first silicon nitride film 3 is formed on the second interlayer insulating film 5, and the second silicon nitride film 6 and the second silicon nitride film 6 are formed on the second silicon nitride film 6. The inter-layer insulating film 5 of the first wiring layer 4 and the second wiring layer 2 which will be described later.
Connection hole 7 for connecting to the wiring layer 9a of
A wiring material 8 in the connection hole made of tungsten or the like is embedded therein.

On the upper part of the second silicon nitride film 6, the first
Second wiring layers 9a and 9b made of aluminum similar to the second wiring layer 4 are formed, and further, the second wiring layer 9 is formed.
A third interlayer insulating film 10 is formed on the upper portions of a and 9b and on the other portions of the second silicon nitride film 6 other than that.
The second interlayer insulating film 5 and the third interlayer insulating film 10 are composed of, for example, a silicon oxide film, a PSG film, a BPSG film or the like.

In the semiconductor device of this embodiment, in order to shorten the wiring interval and increase the degree of integration, as shown in FIG.
The line width D of the wiring layer 4 and the second wiring layers 9a and 9b,
The widths d of the connection holes 7 and 11 opened in the second interlayer insulating film 5 and the third interlayer insulating film 10 are made substantially equal. Even in this case, in the semiconductor device of the present embodiment, the first and second silicon nitride films 3 and 6 are formed as etching stoppers when opening the connection holes 7 and 11, so that a short circuit occurs between wiring layers. There is no danger of

Next, one embodiment of a method of manufacturing the above semiconductor device will be described step by step with reference to FIGS. 2A to 2D and 3E to 3H are cross-sectional views for explaining the method for manufacturing the semiconductor device of this embodiment. Although not shown, after forming the transistor on the silicon substrate 1, first, the first interlayer insulating film 2 was formed by a CVD method such as a plasma CVD method. In this embodiment, a parallel plate single-wafer plasma CVD apparatus is used and the gas flow rate is TEOS gas / O ₂ gas = 800 sccm / 600.
sccm, pressure 1133.2 Pa, substrate temperature 400
The film was formed at a temperature of ° C and a high frequency power of 700W.

Next, a first silicon nitride film 3 to be an etching stopper layer for the connection hole 7 was formed by plasma CVD. In this embodiment, a parallel flat plate single wafer plasma CV is used.
D device using a gas flow rate of SiH ₄ = 50 sccm, N
H ₃ = 200 sccm, N ₂ = 2000 sccm, pressure was 600 Pa, and temperature was 360 ° C. to form a film.

In FIG. 2A, when the material of the lower layer wiring (not shown) formed on the silicon substrate 1 is a refractory metal such as WSix or MoSix, the silicon serving as the etching stopper layer of the connection hole 7 is formed. The nitride film 3 is LPCV
The film may be formed by the D method. Silicon nitride film 3 in this case
Is an LPCVD apparatus and the gas flow rate ratio is SiH ₂ Cl.
_{2 = 50sccm, NH 3 = 200sccm} , N 2 = 2
The film may be formed at 000 sccm, a pressure of 70 Pa, and a temperature of 760 ° C.

Next, using, for example, aluminum as a wiring material, the first wiring layer 4 was formed by the sputtering method. The sputtering conditions for forming the film of Al-1% Si in the present embodiment are such that a sputtering apparatus is used and the gas flow rate is Ar = 100 sc.
cm, pressure 0.4 Pa, substrate heating temperature 150 ° C,
DC power was 5 kW.

Next, although not shown, photoresist patterning was performed to etch aluminum.
In this embodiment, a parallel plate single-wafer plasma etcher device is used and the gas flow rate is BCl ₃ / Cl ₂ = 60 sccm / 9.
Etching was performed at 0 sccm, a pressure of 2 Pa, and an RF of 1200 W. Next, although not shown, the resist was removed by ashing and washing with concentrated sulfuric acid. Figure 2 up to here
It shows in (A).

Next, the second interlayer insulating film 5 is formed by the CVD method under the same film forming conditions as the first interlayer insulating film 2 described above, and then the second interlayer insulating film 5 to be the etching stopper layer of the connection hole 11 is formed. The silicon nitride film 6 was formed by the plasma CVD method under the same film forming conditions as the first silicon nitride film 3 described above.
The process up to this point is shown in FIG.

Next, although not shown, photoresist patterning for opening contact holes was performed and dry etching was performed. Here, etching was performed so as to obtain a high selection ratio with respect to the silicon nitride film 3 as much as possible. In this embodiment, a single-wafer type magnetron RIE device is used, and the gas flow rate is C ₄ F ₈ = 8 sccm, CO = 60 sccm, Ar =
200sccm, pressure 5.3Pa, RF power 160
Etching was performed at 0 W and a susceptor temperature (substrate temperature) of 30 ° C.

Under this condition, a selection ratio of 10 or more was obtained for the silicon nitride film 3. Further, even if the photoresist patterning misalignment of the connection hole 7 occurred, the etching stopped at the silicon nitride film 3 and the connection hole 7 did not reach the underlying wiring. Figure 2 (C) up to here
Shown in

[0028] In order to interlayer insulating film to the silicon nitride film 3 is etched with a high selectivity ratio, high-density plasma etcher as device - using (1E10cm ³ or more plasma density), at least C ₄ CO gas flow rate F ₈
It is preferable to carry out under the conditions of at least half of the gas, that is, CO / C ₄ F ₈ > 0.5, a low pressure of 30 Pa or less, and a high frequency power of 900 W or more.

Next, a metal material was embedded in the connection hole 7. FIG. 2D shows a case where the wiring material 8 in the connection hole is formed of a tungsten plug. Here, the Ti sputter has a gas flow rate of Ar = 100 sccm, a pressure of 0.4 Pa, a DC power of 5 kW, and a substrate heating temperature of 150 °.
C, and then the gas flow rate is Ar / N ₂ = 30 s
After performing TiN sputtering at ccm / 80 sccm, pressure of 0.4 Pa, DC power of 5 kW and substrate heating temperature of 150 ° C., TiN annealing was performed for 30 minutes at a temperature of 450 ° C. at 100% N ₂ gas. It was Next, blanket tungsten is used, and the gas flow rate is WF ₆ / H ₂ / Ar.
= 75 sccm / 500 sccm / 2800 sccm,
The film was formed under the conditions of a pressure of 10640 Pa and a film forming temperature of 450 ° C. Further, blanket tungsten was etched back under the following conditions. First, the blanket tungsten is etched at a gas flow rate of SF ₆ / Ar /
He = 140 sccm / 110 sccm / 25 scc
m, pressure was 32.0 Pa, high frequency power was 625 W, and Blk-tungsten overetching was performed.
The gas flow rate is SF ₆ / Ar / He = 80 sccm / 40 s
ccm / 25 sccm, pressure 22.0 Pa, high frequency power 250 W, and etching of TiN and Ti was performed with a gas flow rate of Cl ₂ / Ar / He = 30 sc.
cm / 30sccm / 10sccm, pressure 2.5P
a, the high frequency power was 350 W, and the magnetic field was 2E-3T. Up to this point is shown in FIG.

Next, in the same manner as the first wiring layer 4,
After the second wiring material is deposited, the second wiring layers 9a and 9a are formed by photoresist patterning and dry etching.
b was formed. The process up to this point is shown in FIG. further,
Similarly to the first interlayer insulating film 2, the third interlayer insulating film 1
0 was formed by the CVD method. Up to this point is shown in FIG.

Next, under the same etching conditions as described above, photoresist patterning for opening contact holes was performed and dry etching was performed. At this time, as shown in FIG. 3G, even if the photoresist patterning misalignment of the connection hole 11 occurs, the etching is stopped at the silicon nitride film 6, and the connection hole 11 does not reach to the wiring 4 of the lower layer. It was

Next, the metal material is embedded in the contact hole 11 under the same conditions as the above-mentioned embedding conditions, and the contact 1 is formed.
Formed 2. As described above, the wiring could be formed without any problem even if the photoresist misalignment due to the patterning of the connection hole occurs.

[0033]

As described above, according to the semiconductor device of the present invention, the presence of the etching stopper layer allows the connection hole to reach the lower layer wiring even if misalignment occurs in the photoresist patterning of the connection hole. Not,
A short circuit between wiring layers can be prevented. In combination with this, in the semiconductor device of the present invention, the width of the lower wiring layer is set to be substantially the same as the width of the connection hole, so that the wiring interval can be shortened and the degree of integration can be increased. You can

Further, in the method of manufacturing a semiconductor device of the present invention, the etching stopper layer is made of a silicon nitride film, and the second interlayer insulating film with respect to the silicon nitride film is etched at a high selection ratio. Can be converted. As a result, it is possible to suppress the generation of stress caused by the etching stopper layer, and it is possible to prevent damage or disconnection of the wiring layer formed thereabove.

[Brief description of drawings]

FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present invention.

2A to 2D are cross-sectional views for explaining the method for manufacturing a semiconductor device of the present invention.

3 (E) to (H) are cross-sectional views for explaining the method for manufacturing a semiconductor device of the present invention.

FIG. 4A is a plan view showing a conventional semiconductor device,
(B) and (C) are sectional views similarly.

FIG. 5 is a cross-sectional view illustrating a problem of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2 ... 1st interlayer insulation film 3 ... 1st silicon nitride film 4 ... 1st wiring layer 5 ... 2nd interlayer insulation film 6 ... 2nd silicon nitride film 7, 11 ... Connection hole 8 ... Wiring material in connection hole 9a, 9b ... Second wiring layer 10 ... Third interlayer insulating film

Claims (4)

[Claims] 1. A first etching stopper layer, a first wiring layer having a predetermined pattern laminated on the first etching stopper layer, the first etching stopper layer and the first wiring layer. An interlayer insulating film which covers and has a selection ratio with respect to the first etching stopper layer; a second etching stopper layer stacked on the interlayer insulating film; and the second etching stopper layer and the interlayer insulating film. A connection hole formed in the first wiring layer and exposed to the first wiring layer, a wiring material embedded in the connection hole, and a second wiring formed on the second etching stopper layer and connected to the wiring material. And a layer, wherein the width of the first wiring layer is a constant width substantially equal to the width of the connection hole. 2. The semiconductor device according to claim 1, wherein the etching stopper layer is made of a silicon nitride film. 3. A step of forming a first etching stopper layer, a step of forming a first wiring layer having a predetermined pattern on the first etching stopper layer, the first etching stopper layer, and Forming an interlayer insulating film having a selection ratio with respect to the first etching stopper layer so as to cover the first wiring layer; and forming a second etching stopper layer on the interlayer insulating film. And a step of forming a contact hole facing the first wiring layer in the second etching stopper layer and the interlayer insulating film by etching under the condition of a high selection ratio with respect to the first etching stopper layer. And a step of burying a wiring material in the connection hole, and a step of forming a second wiring layer connected to the wiring material on the second etching stopper layer. A method for manufacturing a semiconductor device, comprising: 4. An etching gas for opening the connection hole,
And at least C _Four F₈ Gas containing gas and CO gas
The gas flow rate ratio of this etching gas is
S / C_Four F₈ Gas> 0.5, pressure less than 30 Pa
Force and high frequency power of 900W or more
4. The semiconductor according to claim 3, wherein
Device manufacturing method.