JPH0831455B2 - Semiconductor integrated circuit - Google Patents

Description

The present invention relates to a semiconductor integrated circuit which prevents the occurrence of defects due to interlayer short circuits.

(B) Conventional technology In semiconductor integrated circuits, it is easy to increase the speed,
PolySi (gate electrode) because it is suitable for automatic design
-Al-Al multilayer wiring structures are provided. The wiring width is
It is becoming smaller due to the demand for higher integration and higher density,
For the large current capacity such as the power supply to the output buffer transistor, a wiring having a line width larger than that of a general signal line is necessarily present in the chip. The buffer transistors are often arranged in the peripheral portion of the chip due to the relationship of the input / output pads, and the Nch buffer and the Pch buffer are selectively used depending on the type of the signal, and the CMOS power supply and other requirements make the power supply potentials contradictory to each other. That is, lines for V _DD and V _SS are often placed close together.

An example of such a pattern is shown in FIG. An Nch buffer transistor (3) and a Pch buffer transistor (4), which are individually connected to the output pad (2), are arranged side by side on the peripheral edge of the semiconductor chip (1), and the Nch buffer transistor (3) has a first layer Al. The first wiring (5) consisting of the power supply potential V _SS , and the Pch buffer transistor (4) in the second layer Al.
The second wiring (6) composed of the power supply potential V _DD is applied to each.

Since these wirings are formed to have a large width, a large occupied area is required, which leads to an increase in chip size. Therefore, by arranging the first wiring (5) and the second wiring (6) in an overlapping manner. I was trying to reduce it.

(C) Problems to be Solved by the Invention However, the thicker the line width of the Al wiring is, the more easily hillocks are generated, and the stress caused by the overlapping of the wide Al wirings is more likely to cause cracks in the interlayer insulating film.
Therefore, the first wiring (5) is formed by hillocks and cracks.
The second wiring (6) is short-circuited between layers, and short circuits between V _DD and V _SS often occur. If they are arranged so that they do not overlap, an increase in chip size cannot be avoided.

(D) Means for Solving the Problems The present invention has been made in view of the above-described problems of the related art. The line width is made thin so that they do not overlap each other, and the thinning is made by using a multilayer wiring structure. By extending the spare wiring (20) (21) so as to overlap the portion and connecting the thinned portion and the spare wiring (20) (21) between layers,
A semiconductor integrated circuit capable of preventing a short circuit defect between V _DD and V _SS .

(E) Operation According to the present invention, since the wirings are partially thinned and arranged so as not to overlap each other, hillocks and cracks can be prevented from occurring. On the other hand, since the thinned portion of each wiring and the auxiliary wirings (20, 21) are electrically connected, the same current capacity as the thick portion of each wiring can be secured by both of them.

(F) Embodiment One embodiment of the present invention will be described in detail below with reference to the drawings.

In FIG. 1, (11) is a silicon semiconductor substrate and (1
2) is an external input / output bonding pad, (13) is an Nch buffer transistor, and (14) is a Pch buffer transistor.

In Nch and Pch transistors (13) and (14), a gate electrode made of polysilicon (Poly-Si) is arranged on a silicon semiconductor substrate, and source / drain regions by N or P type diffusion are provided on both sides of the gate electrode. By increasing the channel width, the drive capability according to the load is given. Generally, the gate electrode is meandered to make efficient use of the area.

The power supply line for supplying power to these buffer transistors (13) (14) is formed with a thick line width of about 100 to 300 μm, depending on the model, in order to handle a large current and prevent a potential drop. . Internal signal line (15) is 1.0 to
It is about 3.0 μm.

The formation of each wiring can be obtained by vapor deposition of aluminum (Al) on an insulating film (SiO ₂ or the like) covering the surface of the substrate or deposition by a sputtering method, and patterning the deposited material by a photoresist process. A multi-layer structure is obtained by repeating this process, and an insulating film (CVD-SiO ₂ , SOG, SiN, etc.) on the first Al layer.
Is deposited, through holes are formed, Al is deposited and patterned. In the example of the figure, the first wiring (16) for supplying the power supply potential V _SS to the source of the Nch buffer transistor (13) by the first layer Al is used for the source of the Pch buffer transistor (14) by the second layer Al. Second wirings (17) for supplying the potential V _DD are respectively formed. Source region of Nch buffer transistor (13) and first wiring (16)
Between the source region of the Pch buffer transistor (14) and the second wiring (17) directly through the contact hole.
Since there is a problem of step coverage and a problem of process flow, contact is made with a contact hole through the first Al layer. The drain of each transistor is individually connected to the bonding pad (12). In the case of CMOS type, the problem of latch-up is unavoidable, so Nch is Nch, Pch is P
It is arranged collectively by ch.

In the portion where the first wiring (16) and the second wiring (17) do not need to be overlapped because there is a margin in area or one of them is not necessary, each output buffer transistor (13) (14) is It extends with a thick line width ( 18 ) according to the required current capacity.
On the other hand, in the portion where they are close to each other and extend to each other with the thick line width ( 18 ), the wiring (16) (1)
7) is formed thinner than the thick line width ( 18 ), and extends with a thin line width ( 19 ) to prevent overlapping. If the first wiring (16) to which V _SS is applied and the second wiring (17) to which V _DD is applied do not overlap, an interlayer short circuit due to hillocks or the like does not occur.

In addition, the current capacity of each wiring (16) (17), which cannot be avoided as a result of reducing the line width of each wiring (16) (17), is in the upper or lower layer of each wiring (16) (17). Compensation is performed by forming spare wirings (20) (21). The spare wiring (20) for the first wiring (16) is formed of the second Al layer,
The preliminary wiring (21) for the wiring (17) is formed of the first Al layer. The spare wirings (20) and (21) overlap with substantially the entire portion extending with the narrow line width ( 19 ) and are electrically connected to each other by through holes (22). The through hole (22) may be one elongated shape as a whole, or a plurality of through holes (22) may be provided as shown in FIG.

According to this structure, the spare wires (20) (21) are provided and electrically connected to the spare wires (20) (21), so that the current capacity of the portion extending by the thin line width ( 19 ) can be increased by the thick line width ( 18 ). The current capacity of the extending portion can be made substantially equal. Therefore,
Reduction of current capacity due to thinning, potential drop,
Furthermore, the occurrence of electromigration can be prevented. Since the wirings (16) (17) and the spare wirings (20) (21) have the same potential, there is no problem even if an interlayer short circuit due to hillocks or the like occurs.

(G) Effect of the Invention As described above, according to the present invention, the auxiliary wiring (20)
Since the necessary current capacity can be secured by using (21), the pattern can be arranged so that the first wiring (16) and the second wiring (17) do not overlap by reducing the line width. If they do not overlap, an interlayer short circuit due to a hillock or the like does not occur, so that there is an advantage that a short circuit defect between V _SS and V _DD can be completely prevented, thereby improving the reliability of the multilayer arrangement structure and improving the product yield. Still further, by making the line width narrower to prevent the first and second wirings (16) and (17) from overlapping, there is also an advantage that the chip size does not need to be increased.

[Brief description of drawings]

FIG. 1 is a plan view for explaining the present invention, and FIG. 2 is a plan view for explaining a conventional example.

Claims (5)

[Claims] 1. In a semiconductor integrated circuit in which wirings to which different power supply potentials are applied extend in close proximity to each other in a multilayer wiring structure, the first wiring to which one power supply potential is applied is the other power supply. The thick line extends in a portion not overlapping the second wiring to which the electric potential is applied, and has a certain thick width so as not to overlap the second wiring in a portion likely to overlap the second wiring. The wirings are formed to have a line width smaller than the line width so that both wirings are formed without overlapping, and interlayer connection is formed over the entire upper or lower layer of the first wirings overlapping and overlapping the first wirings. Is provided, and a current capacity substantially equal to the current capacity of the first wire extending with the thick line width is obtained in both the first wire extending with the narrow line width and the spare wire. A semiconductor integrated circuit characterized by the above. 2. The semiconductor integrated circuit according to claim 1, wherein the first wiring and the second wiring are power wirings made of aluminum or a conductive material mainly containing aluminum. 3. The semiconductor integrated circuit according to claim 1, wherein the spare wiring and the second wiring are wiring layers in the same layer. 4. A first wiring to which one power source potential is applied and a second wiring to which another power source potential is applied, which are different from the first wiring, extend in close proximity in a multilayer wiring structure. In the semiconductor integrated circuit, the first and second wirings extend with a thick line width in a portion that does not overlap the other wiring, and do not overlap the other wiring in a portion that is likely to overlap each other. As described above, the wirings are formed so as to extend with a line width smaller than the thick line width so that both wirings are formed without overlapping, and the wirings are overlapped and overlapped with the portions extending with the thin line widths on the upper or lower layers of the individual wirings. A preliminary wiring that is interlayer-connected to the first or second wiring is provided over substantially the entire portion, and both of the portion extending with the thin line width and the portion extending with the thick line width of the preliminary wiring are provided. That the current capacity almost equal to the current capacity was obtained Semiconductor integrated circuit to be butterflies. 5. The semiconductor integrated circuit according to claim 1, wherein the spare wiring is a wiring layer which is the same as a wiring layer opposite to the wiring connected between layers.