JPH08313603A - Test mode setting circuit - Google Patents

Abstract

PURPOSE: To utilize the area effectively while decreasing the number of mode terminals by storing a data in an idle area of an ROM and designating a test mode by decoding the data in the idle area using an address and precharge signal selector and a data input decoder. CONSTITUTION: The test mode setting circuit comprises a selector 108 for selecting the clock of a counter 109 in an ROM address generation circuit where a test mode setting data is stored in an idle area of an ROM 111 and used during normal operation, and the signal at a test clock input terminal 106 at the time of test, a selector 107 for selecting an ROM precharge signal and a precharge signal from a test input terminal 105, decorders 101-104 for decoding ROM data signal 111a, and a selector 112 for outputting the data signal 111a to a terminal. Since no special circuit is employed for setting a test mode and the number of test pins can be decreased, the idle area of ROM can be utilized effectively while testing the ROM simultaneously.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test mode setting using a ROM and a ROM test when testing an LSI.

[0002]

2. Description of the Related Art In recent years, with the increase in the integration density of LSIs, the tests performed in the final inspection process are performed for each functional block, or the properties of the test pattern are changed variously, so that it is becoming more and more diverse. Has become. In the LSI provided with such various kinds of test modes, the test mode is set by using a circuit dedicated to the test such as a register. Further, as the number of LSIs having a ROM therein increases along with the increase in the variety of LSIs, the data in the vacant areas of the ROMs have been LSIs without being used.

The conventional test mode setting circuit and RO
The test of M will be described. In FIG. 7, reference numeral 700 is an input terminal for determining whether the LSI is a normal operation or a test operation, and the test operation is performed by inputting L level. 72
Reference numeral 4 denotes a reset terminal, which resets the LSI by inputting L level. Input terminals 701 and 702 determine the test mode, and four test modes can be set by inputting signals respectively. Reference numeral 703 is a test clock input terminal. 704 is a 2-bit register,
70 at the rising edge of the test clock input at 703
1 and 702, and input signals 705 and 706, respectively.
Latch output to.

Denoted at 707 to 710 are decoders, which decode the signals inputted at the 2-bit outputs 705, 706 and 700 of 704, respectively. The outputs of the decoders 707 to 710 are 707a to 710a, respectively, and when they are H, they are in test mode 0 to test mode 3, respectively. 718
Is a ROM with 4-bit address input and 4-bit data output
12 data of 0 to B (HEX) are stored, and the remaining 4 data are unused. 711-71
Reference numeral 4 is a test input terminal for inputting a ROM address signal in test mode 3, and 715 is a test input terminal for inputting a ROM precharge signal.

A logic circuit unit 717 outputs a 4-bit ROM address signal 717a and a ROM precharge signal 717b during normal operation. 716 is a decoder 710
Of the output signal 710a of 711a to 715 when the test mode 3 is 710a at the H level.
Test input signal and ROM address signal 7 during normal operation
17a, ROM precharge signal 717b is selected, and output signals 716a and 716b of the selector 716 are ROM address signals 711 to 714 and ROM 715, respectively.
Output the precharge signal. 719 is an input terminal 70
A selector that uses the signal input from 0 as a selection signal, and selects the ROM data signal 718a and the normal operation outputs 717c, 717d, 717e, and 717f of the LSI when the signal input from the input terminal 700 is in the L level test. Then, the ROM data signal 718a is output to the test output terminals 720 to 721.

The operation will be described below. When H level is input to the input terminal 700, all outputs of the decoder are L level and normal operation is performed. To set test mode 3, input L level to reset terminal 724
Reset SI. The L level is input to the input terminal 700, the H level is input to the input terminals 701 and 702, and the test clock input from the input terminal 703 is raised to be latched and output to the outputs 705 and 706 of the register 704. Output 710a becomes H level, and the test mode 3 is set.

The test mode 3 is assigned to the ROM test, and the selector 716 selects the ROM address signal and the ROM precharge signal of the test inputs 711 to 715 by the output signal 710a of the decoder 710, and the ROM address signal 716a and the ROM in the ROM 718. By inputting the precharge signal 716b, it is output as the ROM data signal 718a. The selector 719 selects the ROM data signal 718a when the input of the input terminal 700 is L level and outputs the ROM data signal to the test output terminals 720 to 723. Therefore, the ROM test can be performed by observing the test output terminals 720 to 723. Done.

FIG. 8 shows operation waveforms of this conventional example.

[0009]

However, in the above-described conventional configuration, the circuit area increases because the number of registers increases as the number of test modes increases, and the external terminals of the LSI for setting the test mode increase. There is a problem that the free area of the ROM cannot be effectively used.

An object of the present invention is to solve the above-mentioned conventional problems, and it is an object of the present invention to effectively utilize the vacant area of the ROM and test the ROM at the same time to provide a test mode setting circuit and a reduction of the test terminals.

[0011]

In order to achieve this object, the test mode setting circuit of the present invention, as a first means, stores data in a vacant area of the ROM, ROM address signal from the test input terminal, ROM Precharge signal and ROM address signal generated in the circuit during normal operation,
A selector for selecting the ROM precharge signal and RO
A decoder having an M data signal as an input is provided, and the test mode is set by decoding the data signal in the empty area of the ROM.

Next, as a second means, data is stored in a vacant area of the ROM, and a clock of an arbitrary counter 1 inside the LSI is tested at a test clock from an input terminal of the LSI and a clock at the time of normal operation. LSI for selecting selector, selector for selecting output of counter 1 and ROM address signal generated in circuit during normal operation
Has a selector for selecting the ROM precharge signal from the input terminal of the CPU and a ROM precharge signal generated in the circuit at the time of normal operation, and a decoder for receiving the ROM data signal, and the counter 1 at the test clock during the test. In this configuration, the ROM address signal is generated by incrementing by 1, and the test mode is set by decoding the data signal in the empty area of the ROM.

Next, as a third means, data is stored in a vacant area of the ROM, and the clock of the counter 2 for generating the ROM address inside the LSI is the test clock from the input terminal of the LSI and the clock at the time of normal operation. , A ROM precharge signal from an LSI input terminal, and an RO generated in the circuit during normal operation.
It has a selector that selects the M precharge signal and a decoder that receives the ROM data signal, and generates a ROM address signal by incrementing the counter 2 with a test clock at the time of testing, and a data signal of a vacant area of the ROM. The test mode is set by decoding the.

As a fourth means, in the second or third means, when the test mode is incremented by incrementing the counter 1 or the counter 2 in the test, the ROM data signal is selected and output to the outside of the LSI. It has a selector and is configured to simultaneously perform test mode setting and ROM test.

[0015]

With the structure of the first means, the test mode setting circuit is not necessary, and the ROM can be effectively used by using the free area of the ROM.

Next, with the configuration of the second means, the test mode setting circuit is not required, the ROM can be effectively used by using the free area of the ROM, and the counter 1 in the circuit internally stores the ROM address signal. Because it is generated by R
The number of test input terminals for setting the OM address signal can be reduced.

By the third means, the test mode setting circuit is not required, the ROM can be effectively used by using the free area of the ROM, and the counter 2 for generating the ROM address during the normal operation is used. Since the ROM address signal is internally generated by, the number of test input terminals for setting the ROM address signal can be reduced, and the RO in normal operation can be reduced.
Since the M address signal and the ROM address signal at the time of testing are shared, a selector is not required and the circuit area can be reduced.

Next, by the fourth means, it is possible to simultaneously test the ROM by observing the ROM data signal while setting the test mode in the counter 1 or the counter 2 of the second or third means. There is no need for a test mode for ROM.

[0019]

【Example】

(First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings.

In FIG. 5, reference numeral 500 denotes an input terminal that determines whether the LSI is a normal operation or a test operation, and the test operation is performed by inputting the L level. A reset terminal 513 inputs the L level to reset the LSI.
Reference numerals 501 to 504 are decoders for decoding the ROM data signal 512a, and the output signals of the decoders 501 to 504 are 501a to 504a, respectively.
At H level, test mode 0 to test mode 3 are set. Reference numeral 512 denotes a 4-bit address input and 4-bit data output ROM, which is 0 at addresses 0 to B (HEX).
12 pieces of data B to H (HEX) are stored, and test mode setting data C to F (HEX) are stored in unused addresses C to F (HEX) during the remaining normal operation. Reference numerals 505 to 508 are test input terminals for inputting a ROM address signal during a test, and 509 are test input terminals for inputting a ROM precharge signal. 51
Reference numeral 1 denotes a logic circuit section which outputs a 4-bit ROM address signal 511a and a ROM precharge signal 511b during normal operation. Reference numeral 510 denotes a selector which uses the input terminal 500 as a selection signal, and selects the test inputs 505 to 509 and 511a and 511b by inputting the L level to the input terminal 500, and outputs the output signals 510a and 510 of the selector 510.
b to ROM address signals of 505 to 508 and 5 respectively
The ROM precharge signal of 09 is output.

The operation will be described below. 500
When the H level is input to the selector 510, the selector 510 selects the ROM address signal 511a and the ROM precharge signal 511b in the normal operation, the decoders 501 to 504 output the L level to the decoder output signals 501a to 504a, respectively, and the LSI normally operates. It will work.

To set the test mode 3, the L level is input to the reset terminal 513 to reset the LSI.
Input L level to the input terminal 500, and test input terminal 5
05 (508) as a ROM address signal F (HEX)
, And the ROM precharge signal is input to 509, so that the address F of the ROM selected by the selector 510 is selected.
(HEX) data F (HEX) to ROM data signal 5
12a. The decoder 504 sets the test mode 3 by decoding the ROM data signal 512a and outputting an H level to the decoder output signal 504a.

The operation waveforms of the first embodiment are shown in FIG. As described above, according to the first embodiment, the test mode setting data is stored in the empty area of the ROM, and the ROM address signal, the ROM precharge signal from the test input terminal and the ROM address signal in the circuit during the normal operation are stored. , ROM
A selector 510 for selecting a precharge signal and RO
Decoders 501 to Decode the M Data Signal 512a
By providing 504, a special circuit for setting the test mode is not used and the empty area of the ROM can be effectively used.

(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings.

In FIG. 3, reference numeral 300 denotes an input terminal for determining whether the LSI is a normal operation or a test operation, and the test operation is performed by inputting the L level. A reset terminal 312 resets the LSI by inputting L level.
Reference numerals 301 to 304 are decoders for decoding the ROM data signal 311a, and the output signals of the decoders 301 to 304 are 301a to 304a, respectively.
At H level, test mode 0 to test mode 3 are set. Reference numeral 311 denotes a 4-bit address input and 4-bit data output ROM, which is 0 at addresses 0 to B (HEX).
12 pieces of data B to H (HEX) are stored, and test mode setting data C to F (HEX) are stored in unused addresses C to F (HEX) during the remaining normal operation. Reference numeral 305 is a test input terminal for inputting a ROM precharge signal. Reference numeral 310 denotes a logic circuit section, which is a 4-bit ROM address signal 310a and RO for normal operation.
It outputs the M precharge signal 310b. Reference numeral 309 denotes an arbitrary 4-bit counter in the logic circuit unit,
08 is a counter 309 according to the input signal of the input terminal 300.
Is the clock of the counter 309 during the normal operation with the input signal of the test clock input terminal 306.
The selector 6a and 6a output the input signal 306 to 308a by inputting the L level to 300. Three
Reference numeral 07 is a selector which uses the input signal of the input terminal 300 as a selection signal, and is input by inputting an L level to the input terminal 300.
05 input signal and counter 309 output signal 309a are selected, and selector 307 output signals 307a and 307b are selected.
309a for ROM address signal and 305 for R
Output as OM precharge signal.

The operation will be described below. When the H level is input to the input terminal 300, the selector 307 selects the ROM address signal 310a and the ROM precharge signal 310b for normal operation, the decoders 301 to 304 output the L level to the decoder output signals 301a to 304a, respectively, and the LSI Is the normal operation. Test mode 3
To set, the L level is input to the reset terminal 312 to reset the LSI. The L level is input to the input terminal 300, the input of the test clock terminal 306 is selected by the selector 308, and 15 is input to the test clock input terminal 306.
Input the clock of the output and ROM to the test input terminal 305
By inputting the precharge signal, the counter 309 outputs F (HEX) to the output 309a, and the selector 307
Outputs the input signals of 309a and the input terminal 305 to the outputs 307a and 307b, respectively. At this time, ROM31
1 outputs F (HEX) to the ROM data signal 311a. The decoder 304 sets the test mode 3 by decoding the ROM data signal 311a and outputting the decoder output signal 304a at the H level.

The operation waveforms of the second embodiment are shown in FIG. As described above, according to the second embodiment, the data of the test mode setting is stored in the empty area of the ROM 311, and the clock of the counter 309 in the circuit used during the normal operation and the signal from the test clock input terminal 306 during the test are stored. A selector 308 for selecting between, a ROM address signal during normal operation, a ROM precharge signal, and a counter 309.
Output signal 309a, RO from test input terminal 305
A selector 307 for selecting the M precharge signal, and R
Decoder 301 for decoding OM data signal 311a
By providing ~ 304, it is possible to effectively use the free area of the ROM without using a special circuit for setting the test mode and reduce the number of test pins.

(Embodiment 3) A third embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, reference numeral 100 is an input terminal for determining whether the LSI is a normal operation or a test operation, and the test operation is performed by inputting L level. A reset terminal 117 resets the LSI by inputting L level.
Denoted by 101 to 104 are decoders for decoding 111a which is a ROM data signal. The outputs of the decoders 101 to 104 are 101a to 104a, respectively, which are test mode 0 to test mode 3 at H level.

Reference numeral 111 denotes a 4-bit address input and 4-bit data output ROM, which stores 12 pieces of data 0 to B (HEX) at addresses 0 to B (HEX), respectively, and is unused during the rest of the normal operation. Addresses C to F (HE
X) each of the test mode setting data C to F (HE
X) is stored. Reference numeral 105 is a test input terminal for inputting a ROM precharge signal. Reference numeral 110 is a logic circuit unit. Reference numeral 109 is a 4-bit counter for generating an address signal of the ROM 111 in the logic circuit section. Reference numeral 108 is a clock of the counter 109 when the input terminal 100 inputs the signal from the test clock input terminal 106 and the counter 109 in the normal operation. The selector 106a, which is a clock, inputs the L level to the input terminal 100 to output the signal input from the input terminal 106 to the output signal 108a of the selector 108.

Reference numeral 107 denotes a selector which uses the signal input to the input terminal 100 as a selection signal. By inputting an L level to the input terminal 100, a test input signal of the input terminal 105 and a ROM precharge signal 110a during normal operation are provided. To select the output signal 107a of the selector 107 and input terminal 10
The input signal 5 is output as a ROM precharge signal. Reference numeral 112 denotes a selector which uses the signal input from the input terminal 100 as a selection signal, and inputs the L level to the input terminal 100, so that the ROM data signal 111a and the output signals 110b, 110c, 110d and
10e is selected, and the ROM data signal 111a is output to the test output terminals 113 to 116.

The operation will be described below. When an H level is input to the input terminal 100, the selector 107 selects the ROM precharge signal 110a for normal operation, the selector 108 selects the clock 106a for normal operation, and the decoders 101 to 104 respectively output the decoder output signal 101.
The L level is output to a to 104a, and the LSI operates normally. To set test mode 3, reset terminal 1
The L level is input to 17 to reset the LSI.

Inputting the L level to the input terminal 100, selecting the input of the test clock terminal 106 by the selector 108, inputting 15 clocks to the test clock input terminal 106, and inputting the ROM precharge signal to 105. Then, the ROM address generation counter 109 outputs F (HEX) to the output signal 109a, and the selector 107
The input signal of the test input terminal 105 is output to the output signal 107a. The ROM 111 outputs F (HEX) as the ROM data signal 111a. The decoder 104 decodes the ROM data signal 111a and outputs the decoder output signal 10
The test mode 3 is set by outputting the H level to 4a. Further, when the test clock is input to the input terminal 106, the ROM data signal 111a is output by the selector 112 and the test output pins 113 to 116 are observed, so that the ROM test can be performed at the same time.

The operation waveforms of the third embodiment are shown in FIG. As described above, according to the third embodiment, the data of the test mode setting is stored in the empty area of the ROM 111, and the clock of the counter 109 of the ROM address generation circuit used in the normal operation and the test clock input terminal 106 from the test clock input terminal 106 are used in the test. Selector 108 for selecting the signal of, and the ROM precharge signal and the test input terminal 10 in the normal operation.
By providing the selector 107 for selecting the ROM precharge signal from the decoder 5, the decoders 101 to 104 for decoding the ROM data signal 111a, and the selector 112 for outputting the ROM data signal 111a to the terminal at the time of the test, It is possible to reduce the number of test pins without using a special circuit, and to effectively utilize the vacant area of the ROM, and at the same time, to test the ROM.

[0035]

As described above, according to the present invention, the circuit for setting the test mode and the terminal for setting the test mode can be reduced, and since the free area of the ROM is used, the ROM can be effectively used and the test mode setting can be performed. It is possible to simultaneously test the ROM by observing the ROM data at the time.

[Brief description of drawings]

FIG. 1 is a diagram for explaining a third embodiment of a test mode setting circuit of the present invention.

FIG. 2 is an operation waveform diagram of a third embodiment of the test mode setting circuit of the present invention.

FIG. 3 is a diagram for explaining a second embodiment of the test mode setting circuit of the present invention.

FIG. 4 is an operation waveform diagram of a second embodiment of the test mode setting circuit of the present invention.

FIG. 5 is a diagram for explaining the first embodiment of the test mode setting circuit of the present invention.

FIG. 6 is an operation waveform diagram of the first embodiment of the test mode setting circuit of the present invention.

FIG. 7 is a diagram for explaining a conventional test mode setting circuit.

FIG. 8 is an operation waveform diagram of a conventional test mode setting circuit.

[Explanation of symbols]

100 test setting input terminal 101 decoder 102 decoder 103 decoder 104 decoder 101a decoder 101 output signal 102a decoder 102 output signal 103a decoder 103 output signal 104a decoder 104 output signal 105 test input terminal 106 test clock input terminal 106a during normal operation Clock of ROM address generation counter 109 of 107 Selector 107a Output signal of selector 107 108 Selector 108a Output signal of selector 108 109 ROM address generation counter 109a Output signal of ROM address generation counter 109 110 Logic circuit section 110a During normal operation ROM precharge signal 110b Output signal of logic circuit section 110c Output signal of logic circuit section 110d Output of logic circuit section 110e Output signal of the logic circuit section 111 ROM 111a ROM data signal 112 Selector 113 Test output terminal 114 Test output terminal 115 Test output terminal 116 Test output terminal 117 Reset terminal 300 Test setting input terminal 301 Decoder 302 Decoder 303 Decoder 304 Decoder 301a Decoder 301 output signal 302a decoder 302 output signal 303a decoder 303 output signal 304a decoder 304 output signal 305 test input terminal 306 test clock input terminal 306a counter 309 clock during normal operation 307 selector 307a selector 307 output signal 307b selector 307 output signal 308 selector 308a selector 308 output signal 309 counter 309a cow Output signal 310 logic circuit unit 310a ROM address signal during normal operation 310b ROM precharge signal during normal operation 311 ROM 311a ROM data signal 312 reset terminal 500 test setting input terminal 501 decoder 502 decoder 503 decoder 504 decoder 501a decoder Output signal 501 Output signal 502a Decoder 502 Output signal 503a Decoder 503 Output signal 504a Decoder 504 Output signal 505 Test input terminal 506 Test input terminal 507 Test input terminal 508 Test input terminal 509 Test input terminal 510 Selector 510a Selector 510 output signal 510b Output signal of selector 510 511 Logic circuit section 511a ROM address signal during normal operation 511b R during normal operation OM precharge signal 512 ROM 512a ROM data signal 513 reset terminal 700 test setting input terminal 701 test input terminal 702 test input terminal 703 test clock input terminal 704 register 705 register 704 output signal 706 register 704 output signal 707 decoder 708 decoder 709 Decoder 710 Decoder 707a Decoder 707 output signal 708a Decoder 708 output signal 709a Decoder 709 output signal 710a Decoder 710 output signal 711 Test input terminal 712 Test input terminal 713 Test input terminal 714 Test input terminal 715 Test input terminal 716 Selector 716a Output signal of selector 716 716b Output signal of selector 716 717 Logic circuit unit 717a Communication ROM address signal during operation 717b ROM precharge signal during normal operation 717c Output signal of logic circuit unit 717d Output signal of logic circuit unit 717e Output signal of logic circuit unit 717f Output signal of logic circuit unit 718 ROM 718a ROM data signal 719 Selector 720 Test output terminal 721 Test output terminal 722 Test output terminal 723 Test output terminal 724 Reset terminal

Claims (4)

[Claims] 1. A large scale integrated circuit (L) having a ROM therein.
SI) test mode setting circuit, in which a test mode setting signal input from an external terminal
A selector for selecting one of a ROM address signal 1 and a ROM precharge signal 1 input from an external terminal during a test, or a ROM address signal 2 and a ROM precharge signal 2 during a normal operation inside the LSI; A decoder for decoding the data signal corresponding to the address signal 1 selected by the selector among the data signals for setting the test mode stored in the unused area during the normal operation of the ROM; A test mode setting circuit configured to set a predetermined test mode of the LSI. 2. A counter 1 is provided inside the LSI, and the counter 1 is a ROM address signal 1 during a test.
The test mode setting circuit according to claim 1, wherein the test mode setting circuit is used as a generation circuit of the test mode setting circuit. 3. A test mode setting circuit according to claim 1, further comprising a counter 2 used as a circuit for generating a ROM address signal 2 in a normal operation, the counter 2 being also used in a test. . 4. When the counter 1 or the counter 2 is incremented and the test mode is set, the ROM test is simultaneously performed by outputting the ROM data to an external terminal. The test mode setting circuit according to claim 3.