JPH08307818A - Video signal processor - Google Patents

Abstract

PURPOSE: To obtain the video signal processor in which a storage capacity of a frame memory is reduced to delay the video signal by a prescribed frame period. CONSTITUTION: A timing pulse generating circuit 5 discriminates a blanking period and a valid image period of a video signal received from an input terminal 1 and a memory control means 4 writes the video signal for the valid image period in a frame memory on the basis of a discrimination signal and reads the video signal for the valid image period written before by a prescribed frame period. A switch 61 selects an input video signal for the blanking period of a video signal for the valid image period delayed from the frame memory respectively on the basis of the discrimination signal and provides an output of the selected signal to an output terminal 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing device for delaying a video signal for a predetermined number of frame periods.

[0002]

2. Description of the Related Art There is known a device for performing not only processing within a field but also processing along the time axis such as between fields or between frames for the purpose of improving the image quality of a video signal. A typical example of this is a three-dimensional luminance signal /
There are a color signal separation filter and a video signal noise suppression device. In order to configure such a device, a device for delaying a video signal is essential, and for example, a video signal processing device as shown in FIG. 6 is used.

FIG. 6 is a block diagram showing a configuration of a conventional video signal processing apparatus. In the figure, 1 is an input end to which a digitized video signal (hereinafter referred to as a digital video signal) is input, and 2 is a digital video signal. Output terminals for outputting the delayed digital video signal, 31 and 32 are frame memories for storing (storing, holding) digital video signals corresponding to the frame period, and 4 is frame memories 31 and 32.
It is a memory control circuit for controlling writing / reading of.

Next, the operation will be described. First, NT
The digital video signal obtained by digitizing the analog video signal by the SC system is input from the input terminal 1 to the frame memory 3
1 is input and is written and stored in the frame memory 31. The digital video signal delayed and read by the frame memory 31 is input to the next-stage frame memory 32, written and stored in the frame memory 32, and then delayed and read again, and the output terminal 2 Is output from. Here, the frame memories 31 and 32
The writing / reading is controlled by the memory control circuit 4, and each digital video signal is delayed by one frame period, that is, about 1/30 seconds. Therefore, the video signal output to the output terminal 2 is for two frame periods, that is, about 1/1 of the digital video signal input to the input terminal 1.
A digital video signal delayed for 5 seconds is output.

As described above, the input digital video signal is
The case of delaying the frame period has been described, but the case of delaying the digital video signal by one frame period will be described below. FIG. 7 is a block diagram showing the configuration of a conventional video signal processing device for delaying a digital video signal by one frame period. This conventional apparatus has one frame memory 31 as a frame memory, and a digital video signal delayed by 1 frame period, that is, 1/30 seconds with respect to the digital video signal input to the input terminal 1 is output terminal. It is output from 2.

[0006]

Since the conventional video signal processing device is configured as described above, the frame memory needs a storage capacity enough to store the video signal for the delay time in frame units. There was a problem.

The present invention has been made to solve the above problems, and provides a video signal processing apparatus capable of delaying an input video signal for a predetermined frame period by reducing the storage capacity of a frame memory. The purpose is to

[0008]

According to a first aspect of the present invention, there is provided a video signal processing device for delaying an input video signal for a predetermined even frame period, wherein a blanking period and an effective screen period of the input video signal are set. Determination means for determining,
A frame memory for storing the input video signal and an input video signal for the valid screen period are written to the frame memory based on a discrimination signal from the discriminating means, and are written and stored before the predetermined even frame period. Based on the frame memory control means for controlling the frame memory so as to read out the video signal in the effective screen period from the frame memory, and the discrimination signal from the discrimination means, the input video signal is supplied during the blanking period. The effective screen period is provided with selection means for selecting and outputting the video signals of the effective screen period read from the frame memory.

A video signal processing device according to a second aspect is a video signal processing device for delaying an input video signal for a predetermined odd frame period, and a determining means for determining a blanking period and an effective screen period of the input video signal, Based on a frame memory for storing the input video signal and a discrimination signal from the discrimination means, the input video signal in the valid screen period is written in the frame memory and is written before the predetermined odd frame period. Frame memory control means for controlling the frame memory so that the stored video signal in the effective screen period is read out from the frame memory; sync signal separating means for separating a sync signal from the input video signal; and the input video signal. A color signal extracting means for extracting a color signal component from the input color signal component Based on the color signal inverting means for inverting the output, the adding means for adding the output signal of the synchronizing signal separating means and the output signal of the color signal inverting means, and the determination signal from the determining means, the blanking period is The output signal of the addition means and the selection means for selecting and outputting the video signal of the valid screen period read from the frame memory during the valid screen period, respectively.

A video signal processing apparatus according to a third aspect of the invention is a video signal processing apparatus for delaying an input luminance signal and an input color signal by a predetermined odd frame period, and determines a blanking period and an effective screen period of the input luminance signal. Discriminating means,
A first frame memory for storing the luminance signal, a second frame memory for storing the color signal, and the input luminance signal and the input color during the effective screen period based on the discrimination signal from the discrimination means. The signals are written in the first and second frame memories, respectively, and the luminance signal and the color signal in the valid screen period written and stored before the predetermined odd frame period are stored in the first and second frame memories, respectively. Frame memory control means for controlling the first and second frame memories so as to be read out from the frame memory, synchronization signal separation means for separating a synchronization signal from the input video signal, and the input color signal with a DC voltage component thereof. On the basis of the color signal inverting means for inverting to the center and the discrimination signal from the discrimination means, the retrace period is the synchronization separation hand. Of the output signal of the first frame and the luminance signal of the valid screen period read from the first frame memory during the valid screen period, and the discrimination signal from the discrimination unit. Based on the above, during the blanking period, the output signal of the color signal inverting means,
The effective screen period is provided with second selecting means for selecting and outputting the color signals of the effective screen period read from the second frame memory.

[0011]

In the video signal processing device according to claim 1,
The input video signal of the effective screen period is written to the frame memory based on the determination signal that determines the blanking period and the effective screen period of the input video signal, and the effective screen period written and stored before the predetermined even frame period is stored. The frame memory is controlled so that the video signal of is read from the frame memory, and further, based on the discrimination signal,
The input video signal is selected in the blanking period, and the video signal in the valid screen period read from the frame memory is selected and output in the valid screen period. As a result, when the input video signal is delayed by a predetermined even frame period, the video in the effective screen period obtained by delaying the synchronization signal and the color subcarrier in the blanking period of the input video signal by the predetermined even frame period from the frame memory. It can be used as a signal synchronization signal and color subcarrier, etc., and the frame memory can store a video signal delayed by a predetermined frame period by storing only a video signal in an effective screen period in a predetermined frame period. Become.

In the video signal processing device according to the second aspect of the present invention, the input video signal of the effective screen period is written in the frame memory on the basis of the discrimination signal for discriminating the blanking period and the effective screen period of the input video signal, and at the same time. The frame memory is controlled so that the video signal in the effective screen period written and stored before the odd frame period of is read from the frame memory, and further, the sync signal separated from the input video signal and the color signal extracted from the input video signal. The signal with the inverted component is added, and the signal obtained by the addition is selected in the blanking period and the video signal in the valid screen period read from the frame memory is selected in the valid screen period based on the discrimination signal from the discrimination means. And output. Therefore, when the input video signal is delayed by a predetermined odd frame period, the sync signal and the color subcarrier in the blanking period of the input video signal are delayed by a predetermined odd frame period from the frame memory, and the video of the effective screen period is delayed. It can be used as a signal synchronization signal and color subcarrier, etc., and the frame memory can store a video signal delayed by a predetermined frame period by storing only a video signal in an effective screen period in a predetermined frame period. Become.

In the video signal processing device according to the third aspect of the present invention, the input luminance signal and the input color signal in the effective screen period are respectively set to the first based on the discrimination signal for discriminating the blanking period and the effective screen period of the input luminance signal. And writing to the second frame memory, and controlling the frame memory to read out the luminance signal and the color signal of the effective screen period written and stored for a predetermined odd frame period from the first and second frame memories, respectively. And then
Based on the discrimination signal, a synchronizing signal separated from the input luminance signal during the blanking period and a luminance signal during the effective screen period read from the first frame memory during the effective screen period are selected and output, Further, based on the discrimination signal, a signal obtained by inverting the input color signal in the blanking period and a color signal in the valid screen period read from the second frame memory in the valid screen period are selected and output. For this reason,
When delaying the component signal separated into the luminance signal and the chrominance signal for a predetermined odd frame period, the sync signal and the color subcarrier in the retrace line period of the input video signal,
The first and second frame memories can be used as a synchronizing signal and a color subcarrier of the video signal in the effective screen period delayed by the predetermined odd frame period, and the first and second frame memories can be used as predetermined. By only storing only the luminance signal and the color signal in the effective screen period in the frame period, it becomes possible to obtain the luminance signal and the color signal delayed by a predetermined frame period.

[0014]

【Example】

Example 1. FIG. 1 is a block diagram showing the configuration of a video signal processing apparatus which is an embodiment of the present invention. In FIG. 1, 1
Is an input end to which a digital video signal is input, 2 is an output end from which a delayed digital video signal is output, 31 and 32 are frame memories for storing (storing, holding) digital video signals corresponding to respective frame periods, Four
Is a memory control circuit for controlling writing / reading of the frame memories 31 and 32, 5 is a timing pulse generating circuit for generating timing pulses, and 61 is a switch circuit for switching digital video signals from the input terminal 1 and the frame memory 32. Further, FIG. 2 is a diagram showing an outline of operation waveforms of each part. In this embodiment, 2
It is assumed that a video signal delayed by the frame period is obtained.

Next, the operation will be described with reference to the drawings. N
The analog video signal of the TSC system is composed of a vertical blanking period, a horizontal blanking period and an effective screen period. In the present embodiment, as shown in (a) of FIG. 2, the digitized digital video signal input from the input terminal 1 also corresponds to the analog video signal in the vertical blanking period, horizontal blanking period and effective screen. It is assumed that the operation is made up of periods, and the operation in the horizontal period will be described below.

First, the digital video signal digitized by the NTSC system is inputted from the input terminal 1 to the side a of the switch circuit 61, the frame memory 31 and the timing pulse generating circuit 5. The timing pulse generation circuit 5 discriminates (detects and discriminates) the blanking period and the effective screen period from the input digital video signal, and the discrimination signal is determined by the memory control circuit 4 as shown in (b) of FIG. To enter. Here, the discriminating signal for discriminating between the blanking period and the valid screen period represents the blanking period during the "L" period and the valid screen period during the "H" period. Next, the memory control circuit 4 is based on the discrimination signal for discriminating the blanking period and the effective screen period inputted from the timing pulse generation circuit 5, and the discrimination signal is in the "H" period only in FIG. The frame memory control signals for controlling the writing / reading of the frame memories 31 and 32 as shown in (c) are output to the frame memories 31 and 32, respectively, and the frame memory control signal is "L" during the "L" period. The level remains unchanged, and the operations of the frame memories 31 and 32 are stopped.

Here, assuming that the frame number of the currently input digital video signal is A frame, the frame memory 31 receives the digital video signal corresponding to the effective screen period of the A frame digital video signal by the frame memory control signal. A signal (hereinafter referred to as an effective digital video signal) is written and stored, while an already stored effective digital video signal of frame (A-1) (one frame before the A frame) is read. And is output to the frame memory 32 in the subsequent stage. Similarly,
In the frame memory 32, the effective digital video signal of the (A-1) frame from the frame memory 31 is written and stored by the frame memory control signal, while it is already stored as shown in (d) of FIG. The effective digital video signal of the (A-2) frame (the frame two frames before the A frame) is read out and output to the b side of the switch circuit 61.

In this manner, the effective digital video signal of (A-1) frame is read from the frame memory 31 and the effective digital video signal of (A-2) frame is read from the frame memory 32 and output. To be done. As described above, the timing pulse generation circuit 5 discriminates the blanking period and the effective screen period from the input digital video signal, and the discrimination signal is a switch circuit as shown in (e) of FIG. The signal is input to the switch circuit 61 as a switch circuit switching signal for switching 61. The switch circuit 61 uses the switch circuit switching signal to cause the a of 61 during the horizontal blanking period of the input digital video signal.
To the output terminal 2 and the input digital video signal is switched to the b side of 61 in the effective screen period and the effective digital video signal delayed by 2 frame periods which is the output of the frame memory 32 is selected. Output to.

The operation in the horizontal period of the video signal has been described above, but the same operation occurs in the vertical blanking period. That is, the timing pulse generation circuit 5 determines (detects, identifies) the blanking period and the effective screen period from the input digital video signal, and also in the vertical blanking period,
The discrimination signal for discriminating between the blanking period and the effective screen period is at "L" level indicating the blanking period. As described above, during the period when the determination signal for the blanking period and the effective screen period is at the “L” level, the memory control circuit 4 causes the frame memory 3 to operate.
Since the frame memory control signals to 1 and 32 are kept at "L" level, writing / reading to / from the frame memories 31 and 32 is not performed. On the other hand, the switch circuit switching signal output from the timing pulse generating circuit 5 to the switch circuit 61 also becomes "L" level as in the horizontal synchronizing period, and the switch 61 selects the input digital video signal from the a side and outputs the output terminal 2 Output to.

Here, the total number of scanning lines of the NTSC video signal is 525, of which 490 are effective scanning lines excluding the vertical blanking period, and 6 horizontal scanning periods.
Considering that the effective horizontal scanning period is 3.5 μSec and the effective horizontal scanning period excluding the horizontal blanking period is 52.7 μSec, (490 × 52.7) / (525 × 63.5) ≈
Since it is 0.775, according to this embodiment, about 23
% Frame memory storage capacity can be reduced.

As described above, the effective digital video signal delayed by two frame periods and the input digital video signal in the blanking period are switched and output from the output terminal 2.
Therefore, the frame memories 31 and 32 only need to have a storage capacity capable of storing an effective digital video signal, and the storage capacity of the frame memory can be significantly reduced as compared with the conventional device. The cost of the frame memory, which is relatively expensive, can also be significantly reduced.

By the way, in the NTSC system video signal, as shown in FIG. 2, a color burst which is a color subcarrier required for demodulating a color signal is inserted in the horizontal blanking period. Further, the relationship shown in Expression (1) holds for the color subcarrier of the NTSC video signal. fsc = 525 × 455/2 × f _F (1) where fsc is the color subcarrier frequency, and f _{F is the} frame frequency. From the equation (1), the color subcarrier in the video signal of a certain frame has a phase opposite to that of the color subcarrier in the video signal before and after the odd frame, and the color subcarrier in the video signal before and after the odd frame. It turns out that are in the same phase.

Therefore, when the input video signal is delayed by an even number of frame periods, it is sufficient to use an even number of frame memories in the configuration of the first embodiment. However, when the input video signal is delayed by an odd number of frame periods, it is performed. If only an odd number of frame memories are used in the configuration of Example 1, since the delayed digital video signal from the frame memory and the color burst in the blanking period of the input digital video signal have opposite phases. The color signal and the color burst of the digital video signal output by switching between them are also in the opposite phase. An example in which the video signal is delayed for an odd number of frame periods in this way will be described below.

Embodiment 2 FIG. FIG. 3 is a block diagram showing the configuration of a video signal processing device which is another embodiment of the present invention. In FIG. 3, 1 is an input end for inputting a digital video signal, 2 is an output end for outputting a delayed digital video signal, and 31 is a frame for storing (storing) a digital video signal corresponding to a frame period. Memory, 4 is a memory control circuit that controls writing / reading of the frame memory 31, 5 is a timing pulse generation circuit that generates timing pulses, 61 is a switch circuit that switches signals from the adder circuit 10 and the frame memory 32, and 7 is an input A sync signal separation circuit for separating a sync signal from a digital video signal, 8 a color signal extraction filter for extracting a color signal from an input digital video signal, and 9 a color signal extraction filter 8
An inverting circuit for inverting the output signal of 10 is an adding circuit for adding the output signals of the synchronizing signal separating circuit 7 and the inverting circuit 9. Further, FIG. 4 is a diagram showing an outline of operation waveforms of each part. In this embodiment, a video signal delayed by one frame period is obtained.

Next, the operation will be described with reference to the drawings. First, the video signal digitized by the NTSC system is input from the input terminal 1 to the sync signal separation circuit 7, the color signal extraction filter 8, the frame memory 31, and the timing pulse generation circuit 5. Timing pulse generation circuit 5
Is the same as in the first embodiment, the blanking period and the effective screen period are determined (detection, identification) from the input digital video signal.
Then, the discrimination signal is input to the memory control circuit 4 as shown in (b) of FIG. Here, the discrimination signal for discriminating the blanking period and the effective screen period is the "L" period, which is the blanking period,
The “H” period represents an effective screen period.

Next, the memory control circuit 4, based on the discrimination signal for discriminating between the blanking period and the effective screen period inputted from the timing pulse generating circuit 5, the discrimination signal is in the "H" period only, A frame memory control signal for controlling writing / reading of the frame memories 31 and 32 as shown in (c) of FIG. 4 is output to the frame memories 31 and 32, respectively, and the frame memory control signal is output during the “L” period. It remains at "L" level. Here, assuming that the frame number of the currently input digital video signal is the A frame, the frame memory 31 writes and stores the effective digital video signal of the A frame by the frame memory control signal, while the valid digital video signal is already stored. The effective digital video signal of the (A-1) frame (one frame before the A frame) is read and output to the b side of the switch circuit 61.

On the other hand, the sync signal separation circuit 7 separates the sync signal from the input digital video signal and outputs the separated sync signal as shown in (e) of FIG. The color signal extraction filter 8 extracts a color signal component from the input digital video signal, and the extracted color signal component is inverted by the inversion circuit 9 and output as an inverted color signal component. Here, the color signal component means a combination of the color subcarrier and the color signal. Further, as shown in (f) and (g) of FIG. 4, inversion means that the DC voltage level (component) included in the color signal component is 0 (center, reference), and this voltage or more is positive and below. Is a negative, and it means an operation to invert this positive and negative. Therefore, the color subcarrier in the inverted color signal component and the color subcarrier of the input digital video signal have an opposite phase relationship. Further, the synchronizing signal output from the synchronizing signal separation circuit 7 and the inverted color signal component output from the inverting circuit 9 are input to the adding circuit 10. The adder circuit 10 adds the AC voltage component of the inverted color signal component and the DC voltage component of the synchronization signal, and then adds the adder circuit 1 as shown in (h) of FIG.
The output signal of 0 is input to the a side of the switch circuit 61.

As described above, the timing pulse generation circuit 5 discriminates the blanking period and the effective screen period from the input digital video signal, and the discrimination signal is as shown in (i) of FIG. Switch circuit 6 as a switch circuit switching signal for switching the switch circuit 61
Enter 1. As described above, the timing pulse generation circuit 5 discriminates (detects and identifies) the blanking period and the effective screen period from the input digital video signal, and as in the first embodiment, (i) in FIG. A switch circuit switching signal for switching the switch circuit 61 corresponding to the blanking period and the effective screen period as shown in (4) is output to the switch circuit 61. The switch circuit 61 uses the switch circuit switching signal so that the horizontal blanking period of the input digital video signal is 61
Of the digital video signal in which the phase of the color subcarrier is inverted with respect to the input digital video signal, and the effective screen period is switched to the b side and delayed by one frame period which is the output of the frame memory 31. Each effective digital video signal is selected and output to the output terminal 2. Therefore, in the output digital video signal,
The phase relationship between the color burst and the color subcarrier of the effective video signal is never opposite.

The operation in the horizontal period of the video signal has been described above, but the same operation is performed in the vertical blanking period. During the vertical blanking period, there are no color subcarriers, so
Only the synchronizing signal of the input digital video signal is output from the adding circuit 10. Other operations are similar to those described in the first embodiment. Although the case where the input video signal is delayed by one frame period has been described, when the input video signal is delayed by an odd number of frame periods, an odd number of frame memories are used to obtain an effective video signal delayed by an odd number of frames. do it.

As described above, even when the input video signal is delayed for an odd number of frame periods, the frame memory is
As long as it has a storage capacity that can store an effective video signal, the storage capacity can be significantly reduced compared to the conventional device, and the cost of the frame memory, which is generally expensive, is also significantly reduced. can do.

Example 3. The third embodiment is configured to delay the NTSC video signal separated into the luminance signal and the chrominance signal. In FIG. 5, 11 is an input end to which a digital luminance signal is input, 12 is an input end to which a digital color signal is input, 21 is an output end from which a delayed digital luminance signal is output, and 22 is a delayed digital color. An output terminal for outputting a signal, 33 is a frame memory for storing (holding) a digital luminance signal corresponding to a frame period, 34 is a frame memory for storing (holding) a digital color signal corresponding to a frame period, and 4 is a frame memory A memory control circuit for controlling writing / reading of 33 and 34, a timing pulse generating circuit for generating timing pulses, a switch circuit 61 for switching signals from the synchronization signal separation circuit 7 and the frame memory 33,
62 is a switch circuit for switching the signals from the inverting circuit 9 and the frame memory 34, 7 is a synchronizing signal separating circuit for separating the synchronizing signal from the input digital luminance signal, and 9 is an inverting circuit for inverting the input digital color signal. In this embodiment, a video signal delayed by one frame period is obtained.

Next, the operation will be described with reference to the drawings. First, the luminance signal digitized by the NTSC system is input from the input terminal 11 to the synchronization signal separation circuit 7, the frame memory 33 and the timing pulse generation circuit 5. As in the first embodiment, the timing pulse generation circuit 5 determines the blanking period and the effective screen period from the input digital luminance signal, and outputs the determination signal for determining the blanking period and the effective screen period to the memory control circuit 4. To enter.

Next, the memory control circuit 4 controls a frame for controlling writing / reading to / from the frame memory 33 based on the discrimination signal of the blanking period and the effective screen period inputted from the timing pulse generating circuit 5. Outputs a memory control signal. Here, assuming that the frame number of the currently input digital video signal is A frame, the frame memory 31 uses the frame memory control signal to
While the digital luminance signal corresponding to the effective period of the A frame (hereinafter referred to as the effective digital luminance signal) is written and stored, it is already stored (A-1).
The effective digital luminance signal of the frame (one frame before the A frame) is read and output to the b side of the switch circuit 61.

On the other hand, the sync signal separation circuit 7 separates the sync signal from the input digital luminance signal and outputs the sync signal. The timing pulse generation circuit 5 detects (identifies) the blanking period and the effective screen period from the input digital luminance signal, and a switch for switching the switch circuit 61 corresponding to the blanking period and the effective screen period. The circuit switching signal is output to the switch circuit 61. Switch circuit 6
1 is switched to the a side during the horizontal retrace period of the input digital luminance signal by the switch circuit switching signal, switches the synchronization signal input from the synchronization signal separation circuit to the b side during the effective screen period, and stores the frame memory 33. The effective digital luminance signal delayed by one frame period, which is the output of
Each is selected as a delayed luminance signal and output to the output terminal 21.

The color signal digitized by the NTSC system is input from the input terminal 12 to the inverting circuit 9 and the frame memory 34. Similarly to the second embodiment, the inverting circuit 9 inverts the phase of the input color signal component and outputs the inverted color signal component to the b side of the switch circuit 62. Therefore, the color subcarrier in the inverted color signal component and the color subcarrier of the input digital color signal have an opposite phase relationship. The memory control circuit 4 also outputs a frame memory control signal for controlling writing / reading to / from the frame memory 33 to the frame memory 34.
In accordance with the frame memory control signal, a digital color signal corresponding to the effective period of the A frame (hereinafter referred to as an effective digital color signal) is written and stored, while it is already stored (A-1). The effective digital color signal of the frame (one frame before the A frame) is read out and output to the b side of the switch circuit 62.

Similarly to the switch circuit 61, the switch circuit 62 is switched to the side a during the blanking period by the switch circuit switching signal from the timing pulse generation circuit 5, and the color sub signal is input to the input digital color signal input from the inverting circuit 9. The digital color signal in which the phase of the carrier wave is inverted, and the effective screen period is switched to the b side, and the effective digital color signal delayed by one frame period which is the output of the frame memory 34 is selected as each delayed color signal. Output terminal 2
Output to 2. Therefore, in the output digital color signal, the phase relationship between the color burst and the color subcarrier of the effective color signal does not become opposite.

Although the case where the input luminance signal and the color signal are delayed by one frame period has been described, when the input luminance signal and the color signal are delayed by an odd number of frame periods,
The frame memories 33 and 34 may be configured to have an odd number of frame memories so as to obtain an effective luminance signal and an effective color signal delayed for an odd frame period. Further, in the case of delaying the input luminance signal and the chrominance signal for an even frame period, in the configuration of the present embodiment described above, the switch circuit 61
And the a side of the switch circuit 62 are directly connected to the input terminals 11 and 12, respectively.
The frame memories 33 and 34 may each be configured to have an even number of frame memories so as to obtain an effective luminance signal and an effective color signal delayed by an even frame period.

As described above, even when the separated luminance signal and chrominance signal are delayed, the frame memory has only to have a storage capacity for storing the effective luminance signal and the chrominance signal, The storage capacity can be significantly reduced as compared with the conventional device, and accordingly, the cost of the frame memory, which is generally expensive, can be significantly reduced.

[0039]

According to the first aspect of the present invention, when the input video signal is delayed by a predetermined even frame period, the synchronization signal and the color subcarrier in the blanking period of the input video signal are predetermined from the frame memory. It can be used as a sync signal and a color subcarrier of the video signal in the effective screen period delayed by an even frame period, and therefore, it is not necessary to store the signal in the retrace line period in the frame memory, and the storage capacity of the frame memory can be reduced. The cost can be significantly reduced, and the cost can be significantly reduced accordingly.

According to the second aspect of the present invention, when the input video signal is delayed by a predetermined odd frame period, the synchronization signal and the color subcarrier in the blanking period of the input video signal are
It can be used as a sync signal and a color subcarrier of the video signal in the effective screen period delayed by a predetermined odd frame period from the frame memory, and therefore it is not necessary to store the signal in the retrace line period in the frame memory. The storage capacity of the memory can be significantly reduced, and the cost can be significantly reduced accordingly.

According to the third aspect of the present invention, when the component signal separated into the luminance signal and the chrominance signal is delayed for a predetermined odd frame period, the synchronizing signal and the color subcarrier in the blanking period of the input video signal, etc. Can be used as a sync signal and a color subcarrier of the video signal in the effective screen period delayed by a predetermined odd frame period from the first and second frame memories, and therefore, the signal in the blanking period can be used. There is no need to store it in the frame memory, the storage capacity of the frame memory can be significantly reduced,
Along with that, the cost can be reduced significantly.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a video signal processing apparatus that is Embodiment 1 of the present invention.

FIG. 2 is an operation explanatory diagram of the video signal processing device according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a video signal processing device that is Embodiment 2 of the present invention.

FIG. 4 is an operation explanatory diagram of a video signal processing device which is Embodiment 2 of the present invention.

FIG. 5 is a block diagram showing a configuration of a video signal processing device that is Embodiment 3 of the present invention.

FIG. 6 is a block diagram showing a configuration of a conventional video signal processing device.

FIG. 7 is a block diagram showing another configuration of a conventional video signal processing device.

[Explanation of symbols]

31, 32, 33, 34 Frame memory, 4 memory control circuit, 5 timing pulse generation circuit, 61, 62
Switch circuit, 7 sync signal separation circuit, 8 color signal extraction filter, 9 inversion circuit, 10 addition circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuhiro Kurisaki 1 Baba Institute, Nagaokakyo City, Kyoto Prefecture Mitsubishi Electric Corporation Kyoto Factory (72) Masaki Yamakawa 1 Baba Institute, Nagaoka Kyoto Prefecture Mitsubishi Electric Corporation Kyoto Works

Claims (3)

[Claims] 1. A video signal processing apparatus for delaying an input video signal for a predetermined even frame period, a judging means for judging a blanking period and an effective screen period of the input video signal, and a frame memory for storing the input video signal. Based on the discrimination signal from the discrimination means, the input video signal of the valid screen period is written to the frame memory, and the video signal of the valid screen period written and stored before the predetermined even frame period. A frame memory control means for controlling the frame memory so that the frame memory is read out from the frame memory; and, based on a discrimination signal from the discrimination means, the input video signal during the blanking period and the frame memory during the effective screen period. Selecting means for selecting and outputting each of the video signals in the effective screen period read from A video signal processing device comprising: 2. A video signal processing apparatus for delaying an input video signal for a predetermined odd frame period, a determining means for determining a blanking period and an effective screen period of the input video signal, and a frame memory for storing the input video signal. Based on the discrimination signal from the discrimination means, the input video signal of the effective screen period is written in the frame memory, and the image of the effective screen period written and stored before the predetermined odd frame period is stored. A frame memory control means for controlling the frame memory so as to read a signal from the frame memory, a sync signal separating means for separating a sync signal from the input video signal, and a color signal for extracting a color signal component from the input video signal. Extracting means, and color signal inverting means for inverting the input color signal component centering on its DC voltage component Based on the addition means for adding the output signal of the synchronizing signal separation means and the output signal of the color signal inversion means, and the discrimination signal from the discrimination means, the output signal of the addition means during the blanking period A video signal processing device, comprising: a selection unit that selects and outputs the video signal of the valid screen period read from the frame memory during the screen period. 3. A video signal processing device for delaying an input luminance signal and an input color signal for a predetermined odd frame period, a discriminating means for discriminating a blanking period and an effective screen period of the input luminance signal, and storing the luminance signal. A first frame memory for storing the color signal, and a second frame memory for storing the color signal, and the input luminance signal and the input color signal in the effective screen period based on the determination signal from the determination means. While writing to the first and second frame memories, the luminance signal and the color signal of the valid screen period written and stored before the predetermined odd frame period are read from the first and second frame memories, respectively. A frame memory control means for controlling the first and second frame memories, and the same from the input video signal. On the basis of the sync signal separating means for separating the signals, the color signal inverting means for inverting the input color signal centering on the DC voltage component thereof, and the discrimination signal from the discriminating means, the synchronous separating means for the blanking period. And a luminance signal for the effective screen period read from the first frame memory during the effective screen period.
On the basis of the selection signal from the selection means and the discrimination signal from the discrimination means, the output signal of the color signal inversion means during the blanking period, and the valid screen read from the second frame memory during the valid screen period. A second color signal for selecting and outputting each color signal of the period
A video signal processing device, comprising: