JPH08307243A - Current mode semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To facilitate the wiring by not connecting a gate terminal of a 2nd differential transistor(TR) to an external input but connecting it to an output terminal on a 1st differential TR so as to use only one wiring enough for an input line. CONSTITUTION: With an H signal given to an input terminal IN101, a TR 11 is conductive and the same amount of current as that of a constant current source TR flows and an L signal is outputted from an output terminal OUT 105 being a source of a TR 14. Thus, a TR 12 receiving a source voltage of the TR 14 as a gate voltage is nonconductive and the same level H signal as VDD is outputted from an output terminal OUT 106 being a source of a TR 15. Moreover, with an L signal given to the IN 101, the TR 11 is nonconductive and a terminal OUTB being a source of the TR 14 provides an output of an H signal having the same level as the VDD. Then the TR 12 receiving a source voltage of the TR 14 as a gate voltage is made conductive and the output terminal OUT 16 provides an output of an L signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current mode semiconductor integrated circuit used as a buffer or an inverter, and more particularly to a MOS current mode semiconductor integrated circuit.

[0002]

2. Description of the Related Art Conventionally, in a differential amplifier circuit type current mode semiconductor integrated circuit used for a buffer or an inverter,
For example, as in the MOS current mode semiconductor integrated circuit shown in FIG. 2, nMOS transistors 21 and 22 for inputting differential signals from input terminals IN201 and INB202.
And a pMOS transistor 2 used as a load for obtaining a desired amplitude by applying an appropriate voltage to the nMOS transistor 23 and the input terminal RFP204, which are constant current sources by applying an appropriate voltage to the input terminal RFN203.
4 and 25.

Next, the operation will be described. A positive power supply voltage V _DD is supplied to the power supply terminal 207, and a voltage for obtaining a desired constant current and amplitude is input terminal RFN203 and input terminal RFP.
In the state given to 204, first, the input terminal IN20
1 is "High", and the input terminal INB202 is "Lo".
Input the signal of w ". Then, the nMOS transistor 2
1 turns on, the same amount of current flows as the constant current source transistor 23, and a "Low" signal of "V _DD -desired amplitude" is output from the output terminal OUTB205, while the nMOS transistor 22 turns off and from the output terminal OUT206. A "High" signal having the same level as V _DD is output.

In addition, "Low" is applied to the input terminal IN201.
In the case where a "High" signal is input to the input terminal INB202, the nMOS transistor 21 is turned off,
The OS transistor 22 is turned on, and the output terminal OUT2
A “Low” signal is output from the output terminal OUTB205 from 06.
Outputs a "High" signal.

[0005]

In a conventional differential amplifier circuit type current mode semiconductor integrated circuit used for a buffer or an inverter, it is necessary to always input a differential signal to the input terminals. It was necessary to carry out input wiring in. Further, when two pair wirings are carried out, it is necessary to eliminate the skew difference between the differential signals, which makes wiring difficult when the wiring area is restricted.

It is an object of the present invention to provide a current mode semiconductor integrated circuit used for a buffer, an inverter, etc., which has a single differential transistor input line and is easy to wire.

[0007]

The current mode semiconductor integrated circuit of the present invention is a differential amplifier circuit type current mode semiconductor integrated circuit used as a buffer or an inverter.
The gate terminal of the second differential transistor is connected to the output terminal on the side of the first differential transistor without being connected to the external input.

A differential amplifier circuit type current mode semiconductor integrated circuit in which a High or Low signal is input to the gate terminals of the differential transistors and the drains of the pair of differential transistors are used as differential outputs. The amplifier circuit
First pMOS transistor and second pMOS transistor, and first nMOS as differential transistor
A transistor and a second nMOS transistor, and a third nMOS transistor serving as a constant current source,
The first desired external voltage is commonly applied to the gates of the first pMOS transistor and the second pMOS transistor, and the power supply output is applied to the drains of the first pMOS transistor and the second pMOS transistor. NMOS
The sources of the transistors are commonly grounded via the third nMOS transistor, and the drains of the first nMOS transistor and the second nMOS transistor are the first drain.
Sources of the pMOS transistor and the second pMOS transistor are respectively connected to the first external output terminal and the second external output terminal, and the gate of the first nMOS transistor is connected to the external input terminal.
The gate of the transistor may be connected to the drain of the first nMOS transistor, and the second desired external voltage may be applied to the gate of the third nMOS transistor, and the first pMOS transistor and the second pMOS transistor may be connected.
The transistor may be replaced with a first resistor and a second resistor having a predetermined resistance value.

[0009]

[Operation] "High" is applied to the input terminal of the first differential transistor.
When the h "signal is input, the first differential transistor turns on
And the same amount of current flows as the constant current source transistor.
The external output terminal on the differential transistor side outputs a "Low" signal of "V _DD -desired amplitude". Therefore, the second differential transistor that receives the same external output as the gate voltage is turned off, and the external output terminal of the circuit on the second differential transistor side outputs the "High" signal at the same level as V _DD .

When a "Low" signal is input to the input terminal of the first differential transistor, the first differential transistor is turned off and the external output terminal on the side of the first differential transistor is at the same level as V _DD. Output a "High" signal. Therefore, the second differential transistor that inputs the same external output as the gate voltage is turned on, and the external output terminal on the side of the second differential transistor is " _LoD " of "V _DD -desired amplitude".
w "signal is output.

By using the MOS current mode semiconductor integrated circuit, effects such as high input impedance, which is a characteristic of the FET, are obtained, and pM is used as a load to obtain a desired amplitude.
The amplitude of the output can be made variable by using the OS transistor.

[0012]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit configuration diagram of a MOS current mode (hereinafter abbreviated as MCML) semiconductor integrated circuit according to an embodiment of the present invention.

The MCML semiconductor integrated circuit of the present invention is shown in FIG.
As shown in, the nMOS transistor 11 that inputs a signal from the input terminal IN101 and the nMO transistor that becomes a constant current source by applying an appropriate voltage to the input terminal RFN103.
PMOS transistors 14 and 15 used as loads to obtain a desired amplitude by applying an appropriate voltage to the S transistor 13 and the input terminal RFP104, and nM inputting the source of the transistor 14 as a gate voltage.
It has an OS transistor 12.

Next, the operation will be described. A positive power supply voltage V _DD is supplied to the power supply terminal 107, and a voltage for obtaining a desired constant current and amplitude is input terminal RFN103 and input terminal RFP10.
4 is applied to the input terminal IN101,
When the "high" signal is input, the nMOS transistor 11
Is turned on, and the same amount of current as the constant current source transistor 13 flows, and the output terminal OUTB105 which is the source of the pMOS transistor 14 outputs a "Low" signal of "V _DD -desired amplitude". Therefore, the nMOS transistor 12 which inputs the source of the same pMOS transistor 14 as a gate voltage is turned off, and the output terminal OUT106 which is the source of the pMOS transistor 15 outputs the "High" signal at the same level as V _DD .

When a "Low" signal is input to the input terminal IN101, the nMOS transistor 11 is turned off and the output terminal OUTB which is the source of the pMOS transistor 14 outputs the "High" signal at the same level as V _DD . Therefore, the nMOS transistor 12 which inputs the source of the same pMOS transistor 14 as a gate voltage is turned on, and the OUT 106 which is the source output terminal of the pMOS transistor 15 has “Lo of“ V _DD −desired amplitude ”.
w "signal is output.

As described above, "H" is applied to the input terminal IN101.
Output terminal OUTB105 only by inputting the "high" signal
Outputs a "Low" signal, and the output terminal OUT106 outputs a "High" signal. Also, the input terminal IN10
Output terminal OUTB only by inputting "Low" signal to 1.
105 outputs a "High" signal, and the output terminal OUT1
06 outputs a "Low" signal.

In the present embodiment, the pMOS transistor is used as the load for obtaining the desired amplitude, and the load is made variable by the applied voltage. However, if the load can be kept constant, the transistor may be changed to a resistor and the load may be used.

[0019]

As described above, according to the present invention, in the MCML semiconductor integrated circuit used as a buffer or an inverter, the gate of one differential transistor is connected to the output terminal of the other differential transistor side. This has the effect that the number of input signals can be reduced to one while obtaining the same output as in the conventional example.

Further, in order to eliminate the skew difference of the input of the differential signal, it is not necessary to consider the equal length wiring of the two input wirings, and the wiring can be easily implemented.

By using the MCML semiconductor integrated circuit, effects such as high input impedance which is a characteristic of FET can be obtained, and by using a pMOS transistor as a load for obtaining a desired amplitude, the output amplitude can be made variable. .

[Brief description of drawings]

FIG. 1 is a circuit diagram of a MOS current mode semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional MOS current mode semiconductor integrated circuit.

[Explanation of symbols]

11, 21 first nMOS transistor for differential operation 12, 22 second nMOS transistor for differential operation 13, 23 third nMOS transistor for constant current source 14, 24 first pMOS transistor for load 15, 25 Second pMOS transistor for load 101, 201 Input terminal IN 202 Input terminal INB 103, 203 Input terminal RFN 104, 204 Input terminal RFP 105, 205 First output terminal OUTB 106, 206 Second output terminal OUT 107, 207 Power input terminal V _DD

Claims (3)

[Claims] 1. In a differential amplifier circuit type current mode semiconductor integrated circuit used as a buffer or an inverter, the gate terminal of the second differential transistor is not connected to an external input and is connected to the first differential transistor side. A current mode semiconductor integrated circuit characterized in that it is connected to an output terminal. 2. A current mode semiconductor integrated circuit of a differential amplifier circuit type, wherein a High or Low signal is input to a gate terminal of a differential transistor, and a drain of a pair of differential transistors serves as a differential output. The dynamic amplifier circuit includes a first pMOS transistor and a second pMOS transistor, a first nMOS transistor and a second nMOS transistor as a differential transistor, and a third nMOS transistor that serves as a constant current source. , A first desired external voltage is commonly applied to the gates of the first pMOS transistor and the second pMOS transistor, and a power supply output is applied to the drains of the first pMOS transistor and the first nMOS transistor. And a second nMOS
The sources of the transistors are commonly grounded via a third nMOS transistor, and the first nMOS transistor and the second nMOS are connected.
The drains of the transistors are connected to the sources of the first pMOS transistor and the second pMOS transistor and the first external output terminal and the second external output terminal, respectively, and the gate of the first nMOS transistor is the external input terminal. The gate of the second nMOS transistor is connected to the drain of the first nMOS transistor, and the second desired external voltage is applied to the gate of the third nMOS transistor. Current mode semiconductor integrated circuit. 3. The current mode semiconductor integrated circuit according to claim 1, wherein the first pMOS transistor and the second pMOS are provided.
A current mode semiconductor integrated circuit in which a transistor is replaced with a first resistor and a second resistor having a predetermined resistance value.