JPH08306877A - Method of fabricating semiconductor device - Google Patents

Abstract

PURPOSE: To ensure global flattening even for a substrate having a plurality of regions different in the sizes of surface steps by selectively etching back an interlayer insulation film formed on the region having relatively large surface steps, and thereafter forming an interlayer insulation film excellent in reflow effect. CONSTITUTION: In fabricating a logic LSI on which a DRAM is mounted, a first interlayer insulation film 16 is first formed on a memory circuit part 5 having relatively large surface steps and a logic circuit 6 having relatively small surface steps, and then a resist mask 17 is formed for covering a region corresponding to the logic circuit part 6. Thereafter, after anisotropic etching is applied, the resist mask 17 is removed to form a second interlayer insulation film 18. Further, the first and second interlayer insulation films 16, 18 are reflowed. Hereby, a wafer is flattened not only locally but also globally to improve the processing accuracy of wiring.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for globally flattening a substrate having a fine / multilayered circuit pattern.

[0002]

2. Description of the Related Art In recent years, with the miniaturization and high integration of semiconductor devices, circuit patterns are becoming finer and more multilayered. However, when the step of the interlayer insulating film becomes large and steep due to the miniaturization and high integration of the semiconductor device, when the Al-based wiring pattern is formed on this step,
When the film is formed by the sputtering method, the step coverage (step coverage) becomes a problem, the exposure focus is locally deviated during the photolithography, and the etching residue (stringer residue) is generated on the side wall of the step during etching. If the processing accuracy and reliability of the wiring pattern are reduced, the reliability of the semiconductor device itself is also reduced. Therefore, it is necessary to improve the flatness of the interlayer insulating film.

Conventionally, as a technique for flattening an interlayer insulating film, for example, a method of applying SOG (Spin On Glass),
A method is known in which the insulating film is further planarized with a resist material and then these are collectively etched back. Further, tetraethoxysilane (hereinafter referred to as TEOS).
And a method of performing chemical vapor deposition (hereinafter referred to as CVD) at atmospheric pressure using a mixed gas of an organic silicon compound and ozone, using a gas obtained by adding water to the above organic silicon compound. A method of forming an insulating film by utilizing a flow effect at the time of film formation, such as a method of performing plasma CVD by using a plasma CVD method, has attracted attention.

If the heat load that can be applied is sufficient, a method of reflowing the film by heat treatment is effective. For example, it can be obtained by performing CVD in a high temperature atmosphere using a mixed gas of an organosilicon compound, a compound containing boron (B), and a compound containing phosphorus (P), and then reflowing the film by high temperature annealing. It is known that a film made of boron-phosphorus-silicate glass (hereinafter, referred to as BPSG) has excellent flatness.

[0005]

However, although the above-described flattening technique has a certain effect for local flattening, it is difficult to achieve global flattening over the entire surface of the substrate. .

For example, DRAM (Dynamic Random Acces
Logic LSI (Large Scale In)
FIG. 6 shows a state in which the planarization insulating film is formed in the manufacturing process of the integrated circuit). Specifically, p-type Si
At least a polycide layer (hereinafter referred to as 1 poly layer) 102 for forming a word line and the like on a substrate 101.
And a polysilicon layer (hereinafter referred to as a 2 poly layer) 103 for forming a storage node and the like, and a polysilicon layer (hereinafter referred to as a 3 poly layer) 104 for forming a plate electrode and the like are laminated. A flattening insulating film 105 is formed of a BPSG film prior to forming an Al-based wiring (hereinafter referred to as a 1Al layer) for forming a bit line or the like on the base.

In this substrate, 1 poly layer 102
Is provided on the Si substrate 101 via the gate oxide film 106 or on the element isolation region 107. The 2 poly layer 103 is provided on the 1 poly layer 102 via an insulating film 108 having a multi-layer structure, and 3 poly is provided.
The ly layer 104 is provided on the 2 poly layer 103 via a capacitor insulating film 109.

However, in the memory circuit section 111, 1 pol
The y layer 102 is provided as a word line, and 2 p
The y layer 103 and the 3 poly layer 104 are the capacitor insulating film 1.
The capacitor for storing the information of the DRAM is configured by being opposed to each other via 09, whereas only 1 poly layer 102 is formed in the logic circuit portion 112. Therefore, in the base body before the planarization insulating film 105 is formed, the memory circuit portion 111 has a larger surface step than the logic circuit portion 112 by the thickness of the capacitor.

Therefore, the flattening insulating film 105 is formed on the substrate having the regions having different surface step sizes.
If the local flattening such as the filling of the inter-wiring space in the memory circuit unit 111 or the logic circuit 112 is achieved, the global step d is generated between the memory circuit unit 111 and the logic circuit unit 112. Will end up. The global level difference d of the flattening insulating film 105 is caused by the thickness of the capacitor and therefore reaches about 600 nm.

Then, if a 1Al layer is formed to form a bit line or the like on the flattening insulating film 105 having the large global step d as described above, the coverage at the time of film formation and the photolithography at the time of photolithography. Required depth of focus (DO
Increase of F) becomes a problem. Also, usually 1 Al
On the layer, the wiring of the second layer and thereafter (2Al layer, 3Al
Layers, etc.) are laminated through the interlayer insulating film,
The above-mentioned global step is also reflected in the interlayer insulating film between these upper and lower wirings. Therefore, when the tungsten plug is embedded in the via hole connecting the upper and lower wirings, the burden of over-etching becomes large, and the processing accuracy of the 2Al layer and the 3Al layer becomes problematic.

The problem of the global step difference as described above is caused by a bipolar logic LSI or an SRAM (Static
Random Access Memory) • This also occurs in the manufacturing process of logic LSIs and the like.

Especially, in the future, the design rule will be 0.25.
It is considered that global planarization is indispensable in order to secure the reliability of the device in the process of μm or less.

Therefore, the present invention has been proposed in view of such conventional circumstances, and manufacture of a semiconductor device capable of global flattening even for a substrate having a plurality of regions having different surface step sizes. The purpose is to provide a method.

[0014]

A method of manufacturing a semiconductor device according to the present invention has been proposed in order to achieve the above-mentioned object, and is applied to a substrate having a plurality of regions having different surface step sizes. Forming a first interlayer insulating film over the entire surface, covering the first interlayer insulating film on a region where the surface step is relatively small with a resist mask, and The step of selectively etching back the interlayer insulating film to remove a part thereof in the film thickness direction, the step of removing the resist mask, and the step of forming a second interlayer insulating film on the entire surface of the base. The process includes a step and a step of reflowing at least the second interlayer insulating film by heat treatment in this order.

Here, the etch-back to the first interlayer insulating film is performed on the average height of the first interlayer insulating film on the region having a relatively large surface step and on the region having a relatively small surface step. It is preferable that the process is performed until the average height of the first interlayer insulating film becomes substantially the same. For this reason, the first interlayer insulating film on the region where the surface step is relatively large is compared with the “region where the surface step is relatively large” and “the surface step is relatively large” in the substrate before the first interlayer insulating film is formed. It is preferable to etch back by a height corresponding to the difference in the size of the surface step with the "small area".

In the present invention, the second interlayer insulating film is
In addition to being required to exhibit excellent reflow characteristics by heat treatment, the first interlayer insulating film can cover the surface step of the substrate with good step coverage, and
It is required that impurities are not deposited when the etch back is performed. For this reason, the second interlayer insulating film is preferably a film having a high impurity concentration, but the first interlayer insulating film is preferably a film having a lower impurity concentration than the second interlayer insulating film. Is.

Therefore, as the first interlayer insulating film,
Atmospheric pressure CVD using a mixed gas of an organosilicon compound represented by TEOS and ozone, or plasma C using a gas obtained by adding water to the above organosilicon compound.
It is preferable to form a SiO _x film containing no impurities by VD or to add a gas of a compound containing B and a compound of P to form a BPSG film during film formation. Further, as the second interlayer insulating film, it is preferable to form a BPSG film having a higher impurity concentration than the first interlayer insulating film.

The above-mentioned impurity concentration means the total concentration of B and P. The specific numerical value of the impurity concentration may be appropriately selected within a practical range so that the first interlayer insulating film and the second interlayer insulating film exhibit the required characteristics.

Further, the present invention is suitable for application when manufacturing an integrated circuit or the like having a memory element mounted therein, and in this case, a region where the number of laminated wiring patterns is relatively large corresponds to a memory circuit section. An area where the number of laminated wiring patterns is relatively small corresponds to a logic circuit section.

[0020]

In the present invention, by selectively etching back the first interlayer insulating film formed on the region where the surface step is relatively large, the first interlayer insulating film on the region where the surface step is relatively large is formed. The average height of the first interlayer insulating film and the average height of the first interlayer insulating film on the region where the surface step is relatively small can be substantially equalized. If the second interlayer insulating film having an excellent reflow effect is formed after the global level difference is eliminated to some extent in this way, not only local planarization but also global planarization can be achieved.

In particular, when a BPSG film having a relatively low impurity concentration is formed as the first interlayer insulating film, the surface steps of the substrate can be covered with good step coverage, and the precipitation of impurities can be suppressed during the subsequent etch back. BPS having a relatively high impurity concentration as the second interlayer insulating film
When the G film is formed, it exhibits an excellent reflow effect during the subsequent heat treatment, and can be sufficiently flattened.

[0022]

EXAMPLES Specific examples to which the method for manufacturing a semiconductor device according to the present invention is applied will be described below.

In this embodiment, in the manufacturing process of a logic LSI having a DRAM mounted therein, a global step is generated in a memory circuit section having a relatively large surface step and a logic circuit section having a relatively small surface step. An example is shown in which the planarization insulating film is formed without the need.

Specifically, first, as shown in FIG. 1, at least a 1-poly layer 2 for forming a word line and the like, a storage node formation, etc. are formed on a p-type Si substrate 1. A wafer on which the 2poly layer 3 and the 3poly layer 4 for forming the plate electrode and the like were formed was prepared.

In this wafer, 1 poly layers 2 and 2
A region where a DRAM is configured by stacking the poly layers 3 and 3 is a memory circuit unit 5, and 1 poly
The region where only the layer 2 is formed is the logic circuit unit 6.

Here, the 1-poly layer 2 is made of so-called polycide in which a refractory metal silicide layer is laminated on a polysilicon layer, and is provided on the Si substrate 1 via a gate oxide film 8 or an element. It is provided on the separation region 9. In addition, 1 poly layer 2 in the memory circuit unit 5
Among them, the one provided on the Si substrate 1 via the gate oxide film 8 is used as a gate electrode in an nMOS transistor whose source / drain is the n ⁻ type impurity diffusion region 10 in the surface layer portion of the Si substrate 1. , Constitute a word line in the DRAM. Further, the 1-poly layer 2 in the logic circuit portion 6 is provided on the n-well region 11 provided in the Si substrate 1 via the gate oxide film 8 and has a p ⁺ -type conductivity in the surface layer portion of the n-well region 11. It serves as a gate electrode in a pMOS transistor using the impurity diffusion region 12 as a source / drain.

The 2 poly layer 3 is made of polysilicon, and is formed on the 1 poly layer 2 in the memory circuit section 5,
It is provided via an insulating film 14 having a multilayer structure. In addition,
The 2 poly layer 3 is in contact with the impurity diffusion region 10 in the nMOS transistor having the 1 poly layer 2 as the gate electrode, and constitutes a storage node in the DRAM. In the peripheral area of the memory circuit section 5,
In order to reduce the local step difference in the memory circuit section 5, 2p
A dummy pattern 3d is formed using the oly layer 3.

The 3 poly layer 4 is also made of polysilicon, and the capacitor insulating film 1 is formed on the 2 poly layer 3.
5, and forms the plate electrode in the DRAM.

As mentioned above, in this wafer,
In the memory circuit section 5, the 2poly layer 3 and the 3poly layer 4 are arranged opposite to each other on the 1poly layer 2 which is a word line via the capacitor insulating film 15 to form a capacitor for storing DRAM information. Thus, in the logic circuit section 6, only the 1 poly layer 2 is formed. For this reason, the memory circuit portion 5 has a larger surface step than the logic circuit portion 6 by the thickness of the capacitor.

Then, in order to flatten the wafer having the above-mentioned structure prior to forming the 1Al layer for forming the bit lines and the like, first, under the following film forming conditions,
A first interlayer insulating film made of a PSG film was formed.

Film forming conditions for the first interlayer insulating film Introduced gas: TEOS flow rate 60 sccm O ₃ flow rate 950 sccm TEB flow rate 7 sccm TMPO flow rate 15 sccm Pressure: normal pressure Substrate temperature: 520 ° C. Film thickness: 500 nm Note that this film formation is performed under normal pressure. It was performed by a CVD device. TEB is triethyl boric acid: B (OC ₂ H ₅ ) ₃ ,
TMPO represents trimethylphosphoric acid: PO (OCH ₃ ) ₃ .

As a result, as shown in FIG.
The entire surface of the wafer could be covered with good coverage by the interlayer insulating film 16. The composition of the first interlayer insulating film 16 had a relatively low impurity concentration such as B: 3.5% by weight and P: 4.3% by weight.

Subsequently, a resist coating film (manufactured by Tokyo Ohka Kogyo Co., Ltd., trade name: THMR-) is formed on the above-mentioned first interlayer insulating film 16.
iP3000) was applied and patterned by photolithography with i-line to form a resist mask 17 covering a region corresponding to the logic circuit section 6.

Thereafter, the above-mentioned wafer was anisotropically etched under the following conditions, and then the resist mask 17 was removed by ashing.

Etching conditions Etching gas: CHF ₃ flow rate 30 sccm CF ₄ flow rate 30 sccm Ar flow rate 150 sccm Magnetic field magnitude: 6.5 × 10 ⁻³ T RF bias power: 1000 W (13.56 Hz) Pressure: 0.26 Pa Temperature: 5 C. Note that this etching was performed by a magnetron RIE (reactive ion etching) device.

As a result, as shown in FIG. 3, a region not covered with the resist mask 17 described above, that is, the first interlayer insulating film 16 in the memory circuit section 5 is formed.
The film thickness was reduced by about 300 nm. Since the first interlayer insulating film 16 had a relatively low impurity concentration, impurities such as B and P did not precipitate during the above-described etch back.

Next, a second interlayer insulating film made of a BPSG film was formed on the above wafer under the following film forming conditions.

Film forming conditions for the second interlayer insulating film Introduced gas: TEOS flow rate 60 sccm O ₃ flow rate 950 sccm TEB flow rate 15 sccm TMPO flow rate 15 sccm pressure: normal pressure substrate temperature: 520 ° C. film thickness: 500 nm Note that this film formation is performed under normal pressure. It was performed by a CVD device.

As a result, as shown in FIG. 4, the first
The second interlayer insulating film 18 covered the second interlayer insulating film 16 with good coverage. The composition of the second interlayer insulating film 18 is B: 4.6% by weight and P: 4.3% by weight, and the concentration of B is higher than that of the first interlayer insulating film 16. there were.

Subsequently, this wafer is heat-treated at 900 ° C. for 10 minutes in an N ₂ gas atmosphere, whereby the above-mentioned first interlayer insulating film 16 and second interlayer insulating film 18 are formed.
Was reflowed.

Although the first interlayer insulating film 16 has a relatively low impurity concentration, the reflow effect is not great, but
The second interlayer insulating film 18 has a relatively high impurity concentration and exhibits an excellent reflow effect.

As a result, as shown in FIG. 5, the first
The planarizing insulating film 19 including the interlayer insulating film 16 and the second interlayer insulating film 18 planarizes the wafer not only locally but globally, and conventionally, between the memory circuit unit 5 and the logic circuit unit 6. The global step that was occurring has been resolved.

This is because the first interlayer insulating film 16 in the memory circuit portion 5 having a relatively large surface step is etched back, so that the average height of the first interlayer insulating film 16 on the memory circuit portion 5 is increased. And the average height of the first interlayer insulating film 16 on the logic circuit portion 6 are substantially the same.

Although the method of manufacturing the semiconductor device according to the present invention has been described above, it goes without saying that the present invention is not limited to the above-described embodiments. For example, although the BPSG film having a low impurity concentration is formed as the first interlayer insulating film 16 in the above-described embodiments, a SiO _x film containing no impurities may be formed. The film forming conditions are not limited to atmospheric pressure CVD using a gas composed of O ₃ and TEOS, and other alkoxysilanes, chain polysiloxanes, or cyclic polysiloxanes may be used instead of TEOS. Alternatively, plasma CVD using water and the above-mentioned organosilicon compound may be applied.

Further, the first interlayer insulating film 16 may be formed by a conventionally known CVD method using silane. For example, if the film is formed by the bias ECR plasma CVD method,
Since the relatively excellent flattening effect is exhibited, the flattening by the second interlayer insulating film 18 becomes easier.

On the other hand, the film forming conditions of the second interlayer insulating film 18 are not limited to those described above as long as they are films excellent in the reflow effect. Furthermore, the structure of the wafer to which the present invention is applied and which is planarized is not limited to that described above.

[0047]

As is apparent from the above description, when the present invention is applied, a substrate having a plurality of regions having different surface step sizes can be planarized not only locally but globally.

Therefore, the processing accuracy of the wiring formed thereon is improved, and a semiconductor device having a multilayer wiring structure can be manufactured with high reliability and high yield.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing a wafer having a memory circuit section having a relatively large surface step and a logic circuit section having a relatively small surface step.

FIG. 2 is a schematic cross-sectional view showing a state in which a resist mask is provided on the logic circuit portion after forming a first interlayer insulating film on the wafer of FIG.

FIG. 3 is a schematic cross-sectional view showing a state in which the film thickness of the first interlayer insulating film in the memory circuit portion is reduced by performing anisotropic etching on the wafer in FIG.

FIG. 4 is a schematic cross-sectional view showing a state in which a second interlayer insulating film is formed on the wafer of FIG.

5 is a thermal treatment on the wafer of FIG. 4 to reflow the first interlayer insulating film and the second interlayer insulating film,
FIG. 6 is a schematic cross-sectional view showing a state in which a flattening insulating film is formed.

FIG. 6 is a schematic view showing a state in which a global step is formed on the surface of a planarization insulating film formed by a conventional method.

[Explanation of symbols]

 1 Si substrate 2 1poly layer 3 2poly layer 4 3poly layer 5 memory circuit section 6 logic circuit section 16 first interlayer insulating film 18 second interlayer insulating film 19 planarizing insulating film

Claims (4)

[Claims] 1. A step of forming a first interlayer insulating film over an entire surface of a substrate having a plurality of regions having different surface step sizes; A step of covering the first interlayer insulating film with a resist mask; a step of selectively etching back the first interlayer insulating film to remove a part thereof in a film thickness direction; A semiconductor device having a step of removing, a step of forming a second interlayer insulating film on the entire surface of the base, and a step of reflowing at least the second interlayer insulating film by heat treatment in this order. Production method. 2. The second interlayer insulating film is used as the first interlayer insulating film.
2. The method for manufacturing a semiconductor device according to claim 1, wherein a film having a lower impurity concentration than that of the interlayer insulating film is formed. 3. The first interlayer insulating film is a boron-phosphorus-silicate glass film having a relatively low impurity concentration, and the second interlayer insulating film is a boron-phosphorus silicate glass film having a relatively high impurity concentration.
3. A phosphorous silicate glass film.
The manufacturing method of the semiconductor device described in the above. 4. The manufacturing of a semiconductor device according to claim 1, wherein the region where the surface step is relatively large is a memory circuit section, and the region where the surface step is relatively small is a logic circuit section. Method.