JPH08306869A - Semiconductor element - Google Patents

Abstract

PURPOSE: To perform simultaneous stable electrical measurement of a plurality of chips in the same wafer by permitting a specific failure chip to be easily electrically excluded from the measurement object. CONSTITUTION: In the pretest to be performed for a semiconductor element 10, the test pad 31 of a cut-off control circuit 30 is opened. In such a case, a cut-off control signal 40 from the cut-off control circuit 30 is permitted to be at a level 'H', and a current supply circuit 20 is permitted to be conductive. When a failure chip is detected in the pretest, in order to electrically exclude the failure chip from the measurement object and perform post-test, power source voltage is applied to the test pad 31 of the cut-off control circuit 30 of the failure chip by measuring equipment. Thus, a cut-off control signal 40 from the cut-off control circuit 30 is permitted to be at a level 'L', and the current supply circuit 20 is permitted to cut off current.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a semiconductor memory, and more particularly, when a plurality of chips in the same wafer are simultaneously electrically measured, a specific defective chip in the wafer is electrically measured. The present invention relates to a semiconductor device that can be removed from the target.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a configuration of an example of a conventional semiconductor device. This semiconductor device is an SRAM
(Static random access memory), which includes a memory cell array 101 and peripheral circuits 102 such as a control circuit, an address decoder, and an input / output circuit.
It has and. Both the memory cell array 101 and the peripheral circuit 102 are directly connected to the power supply pad 103 and the ground pad 104. And the power supply pad 10
3 is connected to a power source and the ground pad 104 is grounded, so that the memory cell array 101 and the peripheral circuit 1 are connected.
02 is supplied with current. When a down converter circuit or the like is used for the current supply unit, the circuit is the power supply pad 103 and the memory cell array 1.
01 and the peripheral circuit 102.

[0003]

By the way, in a pellet test, which is a test of a semiconductor element in a wafer state, there are cases where electrical measurement is simultaneously performed on a large number of chips in the same wafer. In this case, current is simultaneously supplied to a large number of chips in the same wafer from a measuring device such as a memory tester. At this time, for example, a defective chip that causes an abnormal current flow due to a short circuit between the power supply and the ground , The current supply of the measuring instrument is overloaded,
There was a risk of hindering stable measurement. This becomes a problem especially when a wafer burn-in test is simultaneously performed on many chips in the same wafer. If a specific defective chip is to be electrically removed from the measurement target in order to avoid this problem, the current cannot be interrupted inside the conventional semiconductor device, so it is necessary to deal with it on the measuring instrument side. . However, if the measuring instrument side attempts to deal with it, it will be necessary to take measures such as providing a relay for each of a large number of chips in the current supply section of the measuring instrument, and there are many problems in terms of technical and capital investment of the measuring instrument. .

The present invention has been made in view of the above problems, and an object thereof is to easily detect a specific defective chip in a wafer by electrically measuring a plurality of chips in the same wafer at the same time. The object is to provide a semiconductor element that can be removed from the object of measurement and enables stable measurement.

[0005]

According to a first aspect of the present invention, there is provided a semiconductor element, which comprises a functional circuit section having a predetermined function and a terminal for supplying a current to the functional circuit section. , And a conduction / interruption selection means capable of selecting conduction / interruption of a current supplied to the functional circuit section via this terminal.

According to a second aspect of the present invention, in the semiconductor element according to the first aspect, the conduction interruption selecting means has an input terminal for inputting a signal from the outside, and responds to a signal input from the input terminal. It is configured so as to select conduction or cutoff according to the above.

[0007]

In the semiconductor device according to the first aspect, conduction and interruption of the current supplied to the functional circuit portion can be selected by the conduction interruption selecting means, and the same wafer can be selected by selecting the interruption of the current. In the case where electrical measurement is simultaneously performed on a plurality of chips inside, a specific defective chip can be electrically removed from the measurement target.

According to another aspect of the semiconductor element of the present invention, the conduction / interruption selection means selects conduction / interruption according to a signal from the outside. As a result, it is possible to electrically remove the specific defective chip from the measurement target by external control of the measuring device or the like.

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a semiconductor device according to an embodiment of the present invention. This semiconductor device 10
Is an SRAM in which an n-type substrate is used as a semiconductor wafer, and a memory cell array 11 having a plurality of memory cells and a peripheral circuit 12 such as a control circuit, an address decoder, an input / output circuit, etc. as a functional circuit section. Is equipped with. The semiconductor element 10 further has terminals for supplying current to the memory cell array 11 and the peripheral circuit 12,
A power supply pad 13 and a ground pad 14 are provided. Both the memory cell array 11 and the peripheral circuit 12 are directly connected to the power supply pad 13. When a down converter circuit or the like is used for the current supply unit, the circuit is interposed between the power supply pad 13, the memory cell array 11 and the peripheral circuit 12.

The semiconductor element 10 is further interposed as a conduction / interruption selection means between the memory cell array 11 and the peripheral circuit 12 and the ground pad 14 to conduct the current supplied to the memory cell array 11 and the peripheral circuit 12. It is provided with a current supply circuit 20 which can be selected to be cut off, and a cutoff control circuit 30 which controls the current supply circuit 20.
The current supply circuit 20 is normally in the conductive state, but the state in which the current is cut off can be selected according to the cutoff control signal 40 from the cutoff control circuit 30.

There are n-type substrates and p-type substrates as the types of semiconductor wafers on which the semiconductor element 10 is formed. In the case of performing electrical measurement simultaneously on a plurality of chips in the same wafer, in the case of n-type Is common to the substrates in the case of p-type, and is commonly applied to all chips via the substrate. Therefore, when the current supply to a specific chip is interrupted when a plurality of chips in the same wafer are simultaneously electrically measured, it is necessary to disconnect the ground side for the n-type and the power supply side for the p-type. . FIG.
In the example shown in FIG. 2, since the n-type substrate is used as the semiconductor wafer as described above, the current supply circuit 2 is connected to the ground side.
0 is provided. When a p-type substrate is used as the semiconductor wafer, the current supply circuit 20 is provided on the power supply side.

FIG. 2 is a circuit diagram showing an example of the configuration of the current supply circuit 20 and the cutoff control circuit 30 in FIG.
In this example, the current supply circuit 20 is composed of an nMOS (n-channel MOSFET) 21 having a large size and a large current capacity. The drain of the nMOS 21 is connected to the memory cell array 11 and the peripheral circuit 12, and the source is connected to the ground pad 14. The cutoff control circuit 30 is interposed between a test pad 31, an inverter 32 having an input end connected to the test pad 31 and an output end connected to the gate of the nMOS 21, and an input end of the inverter 32 and the ground pad 14. And a resistor 33 having a high resistance value. The inverter 32 is composed of a depletion type pMOS (p channel MOSFET) 32a and an enhancement type nMOS 32b. The power supply voltage _Vcc is applied to the source of the pMOS 32a. The drain of the pMOS 32a is n
It is connected to the drain of the MOS 32b and the source of the nMOS 32b is connected to the ground pad 14. pM
The gate of the OS 32a and the gate of the nMOS 32b are connected to the test pad 31. One end of the resistor 33 is connected to the gate of the pMOS 32a and the gate of the nMOS 32b, and the other end is connected to the ground pad 14. The connection point between the drain of the pMOS 32a and the drain of the nMOS 32b is connected to the gate of the nMOS 21.

Next, the measurement of the semiconductor device 10 according to this embodiment and the operation of the semiconductor device 10 at the time of this measurement will be described.

A pellet test is performed on the semiconductor device 10 according to this embodiment in a wafer state. In this pellet test, electrical measurement is simultaneously performed on many chips in the same wafer. Further, the pellet test includes a pre-test before the defect relief processing and a post test after the defect relief processing. The post test may include a wafer burn-in test. In the pellet test for the semiconductor device 10 according to the present embodiment, when a defective chip that cannot be repaired is found in the pre-test, the defective chip is electrically removed from the measurement target and the post test is performed.

In the pre-test, a power supply is connected to the power supply pad 13 by the measuring instrument, the ground pad 14 is grounded, and the test pad 31 of the cutoff control circuit 30 is opened. In this case, since the ground level is applied to the input end of the inverter 32 via the resistor 33, the cutoff control signal 40 from the cutoff control circuit 30 becomes "H" level, and the current supply circuit 20 becomes conductive. Current is supplied to the memory cell array 11 and the peripheral circuit 12. When a chip capable of defect relief is found in this pretest, a defect relief process is performed on the chip and a posttest is performed.

When a defective chip that cannot be repaired is found in the pre-test, the defective chip is electrically removed from the measurement target to perform the post test. Therefore, for example, a measuring instrument is used to test the pad 31 of the cutoff control circuit 30. The power supply voltage V _cc is applied to. As a result, the cutoff control signal 40 from the cutoff control circuit 30 is "L".
The current level becomes the level, and the current supply circuit 20 is in the state of cutting off the current. Therefore, according to the semiconductor device 10 of the present embodiment,
When performing electrical measurement on a plurality of chips in the same wafer at the same time, a specific defective chip in the wafer can be easily removed from the measurement target, which causes an abnormal current to flow in the defective chip. Is gone
It becomes possible to perform stable measurement. Further, when the pre-test and the post-test are continuously performed, the measuring device side automatically applies the power supply voltage V _cc to the test pad 31 for the defective chip found in the pre-test to automatically detect the defective chip. It is also possible to perform a post test by electrically removing it from the measurement target.

FIG. 3 is a circuit diagram showing another configuration example of the cutoff control circuit 30 in FIG. In this example, the interruption control circuit 30 includes a resistor 35, a laser fuse 36, and an inverter 32. The power supply voltage V _cc is applied to one end of the resistor 35. The other end of the resistor 35 is connected to one end of a laser fuse 36, and the other end of the laser fuse 36 is connected to the ground pad 14. The connection point between the resistor 35 and the laser fuse 36 is connected to the input end of the inverter 32. Inverter 32
The output terminal of is connected to the gate of the nMOS 21.

In the cutoff control circuit 30 shown in FIG. 3, the laser fuse 36 is not blown at first. Therefore, at the time of the test, the ground level is applied to the input terminal of the inverter 32, so that the cutoff control signal 40 from the cutoff control circuit 30 becomes "H" level and the current supply circuit 20 becomes conductive. On the other hand, when the defective chip is electrically removed from the measurement target to perform the post test, the laser fuse 36 in the defective chip is blown by the laser beam before the post test. As a result, the "H" level is applied to the input terminal of the inverter 32, so that the cutoff control circuit 30
The cutoff control signal 40 from is at "L" level, and the current supply circuit 20 is in the state of cutting off the current.

The present invention is not limited to the above embodiment,
For example, the conduction cutoff selection means is not limited to the configurations of the current supply circuit 20 and the cutoff control circuit 30 shown in the embodiment,
For example, the current supply circuit 20 is a depletion type pM.
It is also possible to use an OS and apply a power supply voltage to the gate from the outside to bring the gate into the cutoff state. Further, the present invention can be applied not only to SRAM but also to other semiconductor elements such as DRAM (dynamic RAM).

[0021]

As described above, according to the semiconductor device of the first aspect, the conduction / interruption selection means can select conduction / interruption of the current supplied to the functional circuit portion. When a plurality of chips in the wafer are simultaneously electrically measured, a specific defective chip in the wafer can be easily removed electrically from the measurement target, and stable measurement can be performed.

Further, according to the semiconductor element of the second aspect, since the conduction / interruption selection means selects conduction / interruption according to a signal from the outside, in addition to the above effects,
There is an effect that a specific defective chip can be electrically removed from the measurement target by external control of the measuring instrument or the like.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a configuration of a current supply circuit and a cutoff control circuit in FIG.

3 is a circuit diagram showing another configuration example of the cutoff control circuit in FIG.

FIG. 4 is a block diagram showing a configuration of an example of a conventional semiconductor element.

[Explanation of symbols]

 10 semiconductor element 11 memory cell array 12 peripheral circuit 13 power supply pad 14 ground pad 20 current supply circuit 30 interruption control circuit

Claims (2)

[Claims] 1. A functional circuit section made of a semiconductor and having a predetermined function, a terminal for supplying a current to the functional circuit section, and a terminal for supplying the functional circuit section through the terminal. A semiconductor element, comprising: a conduction / interruption selection unit capable of selecting conduction / interruption of a current. 2. The conduction cutoff selection means has an input terminal for inputting an external signal, and selects conduction or cutoff in accordance with a signal input from the input terminal. 1. The semiconductor device according to 1.