JPH03189992A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To easily detect the existing location of a memory cell generating the leakage current by interrupting between a selected common power source line and a power source, connecting other common power source to the power source, supplying the power only to the memory cell except the selected row and detecting the presence of the generation of the leakage current. CONSTITUTION:By making the output S3 from a row decoder 12 to high level, and the output to other row to low level, at the point between the common power source line g1 and the power source is interrupted, at the point between other common power source line and the power source is connected. Consequently, the current does not flow to the memory cells M11-M1n arranged to a first row, and the current flows to the other memory cells. In such a manner, by selecting each row in order and measuring on the leakage current value each time, at the selective row when the value is less than the allowable value, the involving of the inferior memory cells is detected. In such a manner, the location of the inferior memory cells is easily detected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor memory device, and particularly to one suitable as a static random access memory (RAM).

(Prior Art) The degree of integration of semiconductor memory devices has improved year by year, and as a result, the probability of occurrence of bit defects due to various causes has increased.

For this reason, a decrease in yield has become a problem. As a means to solve this problem, defective bit relief technology has become indispensable today. This technology prepares extra memory cells arranged in several rows and columns in addition to regular memory cells, and is used as a replacement when the presence of defective bits that do not function normally is revealed during the inspection process. The idea is to do so.

On the other hand, although the device operates normally and there is no functional problem, the leakage current may flow in an amount greater than the allowable value. The presence of even one such memory cell causes an increase in current consumption during standby. In such a case, conventionally, as shown in FIG. 3, the location of the memory cell 33 through which the leakage current flows is discovered using a tester, and the location of the memory cell 33 connected between this memory cell 33 and the power supply terminal 31 is determined. After cutting off the leakage path by blowing out the laser fuse 32, the memory cell was replaced with a spare memory cell.

(Problems to be Solved by the Invention) However, detecting memory cells in which leakage current flows using a tester requires a large amount of testing time because the test pattern is complex. For this reason, there has been a problem in that it is extremely difficult to detect a leakage current flowing in a plurality of memory cells, and it may be virtually impossible to detect it, especially in recent semiconductor memory devices with improved integration.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor memory device that can easily detect the location of a memory cell in which a leakage current is generated.

[Structure of the invention]

(Means for Solving the Problems) A semiconductor memory device of the present invention includes a memory cell array in which memory cells are arranged in a matrix, and a common power supply line that connects the current path of each memory cell in the row direction for each row. , selection means connected between the common power supply line and the power supply and configured to switch the connection between the common power supply line and the power supply in response to a selection signal, and the selection means selects one of the common power supply lines according to the selection signal. Select one of them, cut off the connection between the selected common power line and the power supply, and connect the other common power line to the power supply to supply power only to memory cells other than the selected row to prevent leakage. It is characterized by detecting the presence or absence of current generation.

In addition to the memory cell array and common power supply line, there is a word line that selects memory cells for each row, and a row decoder that receives and decodes a row address signal that selects a row from outside the device and outputs a row selection signal. and a selection circuit that is connected between the common power line and the power source, receives an operation mode switching signal from outside the device, and further receives a row selection signal from the row decoder to switch the connection between the common power line and the power source. and word line switching means connected between the word line and the output side of the row decoder and receiving an operation mode switching signal from outside the device to switch the connection between the word line and the row decoder. When the operation mode switching signal instructs switching to the inspection mode, the selection means selects one of the common power supply lines using the row selection signal and cuts off the connection between the selected common power supply line and the power supply. When the common power supply line of the memory cell is connected to the power supply, power is supplied only to memory cells other than the selected row, and the presence or absence of leakage current is detected, and the operation mode switching signal instructs switching to access mode. All the common power supply lines are connected to the power supply, and the word line switching means cuts off between the word line and the row decoder when the operation mode switching signal instructs switching to the inspection mode. All memory cells are set to a non-selected state to enable detection of memory cells that generate leakage current, and when the operation mode switching signal instructs switching to access mode, the word line and row decoder are connected. Alternatively, the memory cell may be put into a selectable state to enable an access operation.

Conversely, power is supplied only to the memory cells in the selected row by connecting the common power line in the selected row to the power source and cutting off the power from other common power lines. Even in a device, the position of a memory cell where a leakage current occurs can be detected.

Furthermore, fuses are connected between the common power supply line and the power supply, and when the position of a memory cell where a current is generated is detected, the common power supply for the row connected to that memory cell is detected. A fuse connected to the line may be blown to cut off the leak path.

(Operation) A selection signal is given to the selection means to select one of the common power supply lines, the selected common power supply line and the power supply are cut off, and the other common power supply lines are connected to the power supply. . In this way, common power lines are selected one after another, power is supplied only to memory cells connected to unselected common power lines, and if the leakage current becomes small, the memory cells that are selected at this point are It can be seen that among the memory cells connected to the common power supply line, there are memory cells through which leakage current flows.

When a word line, a row decoder, and a word line switching means are further provided, switching between the normal access mode and the inspection mode is performed by applying an operation mode switching signal to the selection means and the word line switching means. be exposed. When the operation mode switching signal instructs switching to the inspection mode, the selection means selects one of the common power supply lines according to the selection signal output from the row decoder, and connects the selected common power supply line and the power supply. 1 2 and connect the other common power supply line to the 1 2 power supply. Then, the word line switching means disconnects the word line and the row decoder to put all memory cells in a non-selected state. In this way, common power lines are selected one after another, power is supplied only to the memory cells connected to the unselected common power lines, and when the leakage current becomes small, the memory cells are connected to the selected common power line. It is detected that there is a memory cell in which a leak current flows among the memory cells that have been leaked. When the operation mode switching signal instructs switching to the access mode, the selection means connects all the common power supply lines to the power supply, and the word line switching means connects between the word line and the row decoder. This makes it possible to select a memory cell, and normal access operations can be performed without any problems.

Conversely, power is supplied only to the memory cells in the selected row by connecting the common power line in the selected row to the power source and cutting off the power from other common power lines. In this case, when the leakage current becomes large, it is detected that there is a memory cell through which leakage current flows among the memory cells connected to the common power supply line selected at this time.

Furthermore, if a fuse is connected between the common power line and the power supply, the common power line of the row to which the memory cell is connected is detected after the location of the memory cell where the leakage current occurs is detected. The leak path can be cut off by blowing the fuse connected to the

(Example) An example of the present invention will be described below with reference to the drawings.

FIG. 1 shows the circuit configuration of a semiconductor memory device according to a first embodiment. Memory cells Mll to Mmn are arranged in m rows and n columns. Each memory cell receives power supply from common power supply lines g1 to gm in each row direction. Taking line g1 as an example, each common power supply line g1 to gm is connected to a laser fuse F1, and further connected to a p-type transistor Q1.
It is connected to the power supply terminal 5 via.

A NOR circuit 3 is connected to the gate of this p-type transistor Q1.
The output S1 of the inverter circuit 4 is connected to one of the input terminals of the NOR circuit 3, and the output S3 of the row decoder 12 is input to the input of the inverter circuit 4 via an n-type transistor Q2. ing. An output S3 of the row decoder 12 is connected to a word line W1 for selecting memory cells row by row via a p-type transistor Q3 and an n-type transistor Q5. Furthermore, this word line W
1 is connected to ground via an n-type transistor Q4. The external input circuit 2 generates two outputs S4 and S5 in response to an operation mode switching signal applied from outside the device via the external input terminal 1. The output S4 is input to the other input terminal of the NOR circuit 3 and the gate of the n-type transistor Q5, and the output S5 is input to the gates of each of the n-type transistor Q2, the p-type transistor Q3, and the n-type transistor Q4.

Here, a resistor R is connected between the input side of the external input circuit 2 and the ground. The selection means is external input terminal 1,
It consists of an external input circuit 2, an n-type transistor Q2, an inverter circuit 4, a NOR circuit 3, and a p-type transistor Q1, and the word line switching means includes an external input terminal 1, an external input circuit 2, a p-type transistor Q3, an n It consists of type transistors Q4 and Q5.

Next, the operation of this embodiment having such a configuration will be explained. First, when the operation mode is the test mode, a row to which a memory cell in which a leakage current occurs is connected is detected in the following manner.

A high-level operation mode switching signal S6 is input from outside the device to the external input circuit 2 via the external input terminal 1.

As a result, the output S4 from the external input circuit 2 becomes low level, and the output S5 becomes high level. The n-type transistor Q2, whose gate receives the high-level output S5, becomes conductive, and the output S3 of the row decoder becomes the output S2 of the N-type transistor Q2.
It is input to one input terminal of the OR circuit 3.

Now, considering the case where the first row shown in this figure is selected, the 5 6 output S3 from the row decoder 12 becomes high level, and the outputs to other rows not shown become low level. . High level output S3 is N0
The high level output S1 is input to the other input terminal of the RIlifl path 3 and is input to the gate of the p-type transistor Q1, which becomes non-conductive.

As a result, the connection between the common power supply line g1 and the power supply in this row is cut off, power is no longer supplied to the memory cells Mll to Min, and the other common power supply lines g2 to gm (not shown) are disconnected from each other.
and the power supply are connected, and the memory cells M21 to Mmn
is supplied with power.

Furthermore, the low level output S4 is output from the n-type transistor Q5.
The output S5 at a noise level is input to the gates of the p-type transistor Q3 and the n-type transistor Q4. The n-type transistor Q5 and the p-type transistor Q3 become non-conductive, and the n-type transistor Q4 becomes conductive, and the word line W1 in this row becomes ground level and is separated from the row decoder output S3.

As a result, the memory cells M arranged in this first row
No current flows through ll to M1m, and other memory cells M21
A current will flow through ~Mmn. In this way, each row is selected in turn and the leakage current value is measured each time, and when this value is less than the allowable value, it is detected that the selected row contains a defective memory cell. . Then, by blowing out the laser fuse F1 in this row, the connection between the common power supply line g1 and the power source is cut off, the leakage path is cut off, and the row is replaced with a prepared spare row.

By testing in this manner, the location of the memory cell in which the leakage current is occurring can be easily detected.

On the other hand, when performing the current access operation, a low-level operation mode switching signal S6 is applied to the external input circuit 2, and a high-level output S4 and a low-level output S5 are output. As a result, the n-type transistor Q2 becomes non-conductive, and a high-level output S4 is input to the NOR circuit 3. A low-level output S1 is input to the gate of the p-type transistor Q1, making it conductive, and a power source is connected to the common power line g1 via the power supply terminal 5, so that power is supplied to each memory cell M. Further, n-type transistor Q5 and p-type transistor Q3 are conductive, and n-type transistor Q4
is in a non-conductive state, so the row decoder 12 is connected to each word line w1 to wm and operates without any problem.

Next, a second embodiment will be described using FIG. 2. Contrary to the first embodiment described above, this embodiment allows current to flow only to memory cells arranged in a selected row, so that when leakage current increases, a defective memory cell is detected in the selected row. It is about finding out that it exists.

In this case as well, the terminals of the respective memory cells Mll-Mmn are connected to the common power supply lines g1-gm of each row. Taking the common power supply line g1 in the first row as an example, it is connected to the power supply terminal 5 via a laser fuse F1 and a p-type transistor Q11. An output S14 from a NOR circuit 14 composed of p-type transistors Q12 and 013 and n-type transistors Q14 and Q15 is input to the gate of this p-type transistor Q11.

Output S] of the row decoder is input to one of the input terminals of this NOR circuit 14 as output S1-6 via an n-type transistor Q16. A supplementary output S12 obtained by inverting the operation mode switching signal S11 by the external input circuit 2 is input to the other terminal via the external input terminal 1. Here, a resistor R is connected between the input side of the external input circuit 2 and the ground.

Further, the output side of the row decoder 12 is connected to the first row word line W1 via a p-type transistor Q17 and an n-type transistor Q18, and an n-type transistor Q
It is connected to ground via 19. Here, the positive output 813 of the external input circuit 2 is input to the gates of the transistors Q17 and Q19, similarly to the n-type transistor Q16, and the supplementary output S12 is input to the gate of the n-type transistor 018. Each row of the memory cell array has
Such circuits are similarly configured.

In this embodiment, the selection means includes external input terminals 1 and 9, external input circuit 2, NOR circuit 14, and p-type transistor Q.
The word line switching means is composed of an external input terminal 1, an external input circuit 2, a p-type transistor Q17, and n-type transistors Q1.6, Q18, and Q19.

The operation of the second embodiment having such a configuration will be described below.

In the case of the test mode, a high-level operation mode switching signal S11 is input to the external input circuit 2 from outside the apparatus, as in the first embodiment. From this external input circuit 2, a high level positive output 313 and a low level supplementary output S
12 is output. As a result, transistor Q15
, Q17 and Q18 are non-conductive, transistor Q1
2, Q16 and Q19 become conductive. The word lines, not only Wl shown in the figure, are all set to low level and placed in a non-selected state.

Then, only in this first row selected by the row decoder 12, the output S1 becomes the /1 level. As a result, the potential of the output S16 becomes high level through the transistor 0 Q16 which is in a conductive state.
The p-type transistor Q13 becomes non-conductive, the n-type transistor Q14 becomes conductive, and the output S1 of the NOR circuit 14
4 is a low level. This output S14 is input to the gate, and the p-type transistor 5 becomes conductive, and power is supplied to the memory cells Mll to MIn in this row via the common power supply line g1.

On the other hand, the output S1 to other unselected rows becomes low level, the p-type transistor Q13 becomes conductive, and the n
type transistor Q14 becomes non-conductive. As a result, the output of the NOR circuit 14 becomes high level, the p-type transistor Q 1' 1 becomes non-conductive, and power is no longer supplied to the other memory cells M21 to Mmn. In this way, each row is selected in turn, and when the leakage current measured each time exceeds a permissible value, it is detected that a defective memory cell exists in the selected row. Then, by blowing out the laser fuse F1 in the selected row, the power supply path is cut off, leakage current is prevented from flowing, and the memory cells are replaced with the memory cells in the spare row. By testing in this way, the location of the memory cell in which the leakage current is occurring can be easily detected, as in the first embodiment.

When performing a normal access operation, a low-level operation mode switching signal S11 is applied to the external input circuit 13,
High level supplementary output 812 and low level positive output 813
is output. As a result, transistor Q16 becomes non-conductive, and row decoder 12 and NOROR circuit 1
The output side of the row decoder 12 and the word line w are turned on, and the transistor Q19 is turned off.
1 is connected, and the memory cell to be accessed can be selected. Further, the high-level complementary output S12 is input to the NOR circuit 14, so that the transistor Q15 becomes conductive and the transistor Q12 becomes non-conductive. As a result,
The output S14 of the NOR circuit 14 becomes low level, the transistor Qll becomes conductive, and all the memory cells Mll~
Power is supplied to Mmn and it can operate without any problems.

The first and second embodiments described above are both examples,
The circuit configurations may be different from those shown in FIGS. 1 and 2, respectively. For example, rows are selected one by one, but if one or more rows are selected in combination and a defective row that causes leakage current is detected by supplying power only to the memory cells connected to that row. good.

〔Effect of the invention〕

As explained above, according to the semiconductor memory device of the present invention,
One of the common power supply lines is selected, and power is supplied only to memory cells connected to common power supply lines other than the selected common power supply line. By sequentially making selections like this, when the leakage current becomes small, it becomes clear that a memory cell through which leakage current flows is connected to the selected common power supply line, making it easy to identify defective memory cells. It is possible to detect the position of As a result, defective memory cells can be easily repaired, which greatly contributes to improving yield. Conversely, power is supplied only to memory cells connected to the selected common power supply line, and when the leakage current becomes large, it is detected that a defective memory cell is connected to this common power supply line. It is also possible to do so, and the same effect can be obtained.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the structure of a semiconductor memory device according to a first embodiment of the present invention, FIG. 2 is a circuit diagram showing the structure of a semiconductor memory device according to a second embodiment of the present invention, and FIG. The figure is a circuit diagram showing the configuration of a conventional semiconductor memory device. 1... External input terminal, 2... External input circuit, 3, 4
...Inverter circuit, 14...NOR circuit, 12.
・・Row decoder, Ml 1, Ml 2 ・・Memory cell,
Wl...Word line, gl...Common power line, Fl...
・Laser fuse, Q1~Q5, Qll~Q19...
transistor.

Claims (1)

[Claims] 1. A memory cell array in which memory cells are arranged in a matrix, a common power line connecting the current paths of the memory cells in the row direction for each row, and the common power line and the power source. a selection means connected between the common power supply lines and the power source and configured to switch the connection between the common power supply line and the power supply in response to a selection signal; By selecting one of them, cutting off the connection between the selected common power line and the power source, and connecting the other common power line to the power source, the connection to the common power line other than the selected common power line can be made. 1. A semiconductor memory device that detects whether or not a leakage current occurs by supplying power only to memory cells that are connected to the memory cell. 2. A memory cell array in which memory cells are arranged in a matrix, a common power supply line that connects the current paths of the memory cells in the row direction for each row, and a word line that selects the previous memory cell for each row; A row decoder is connected between the common power supply line and the power supply, and a row decoder is applied from outside the device to decode a row address signal for selecting a previous row, and outputs a selection signal. , further comprising: a selection means that receives the selection signal from the row decoder and switches the connection between the common power supply line and the power supply; and a selection means connected between the word line and the output side of the row decoder; word line switching means for switching the connection between the word line and the row decoder when an operation mode switching signal is applied from outside the device; When instructing switching, one of the common power supply lines is selected by the selection signal, the connection between the selected common power supply line and the power supply is cut off, and the other common power supply line is connected to the power supply. By connecting, power is supplied only to the memory cells connected to the common power supply line other than the selected common power supply line, and the presence or absence of leakage current is detected, and the operation mode switching signal indicates the switching to the access mode. When the operation mode switching signal instructs to switch to the inspection mode, the first word line switching means connects all the common power supply lines to the power supply when the operation mode switching signal instructs switching to the inspection mode. and the row decoder, all of the memory cells are set to a non-selected state, and a memory cell in which a leakage current occurs can be detected, and the operation mode switching signal instructs switching to an access mode. In some cases, the semiconductor memory device is characterized in that the word line and the row decoder are connected to make the memory cell selectable and access operation possible. 3. a memory cell array in which memory cells are arranged in a matrix; a common power supply line connecting the current paths of the memory cells in the row direction for each row; and a common power supply line connected between the common power supply line and the power supply; a selection means for switching the connection between the common power supply line and the power supply in response to a selection signal; the selection means selects one of the common power supply lines according to the selection signal; By connecting the selected common power line and the power source and cutting off the other common power line and the power source, power is supplied only to the memory cells connected to the selected common power line. A semiconductor memory device that detects the presence or absence of leakage current. 4. A memory cell array in which memory cells are arranged in a matrix, a common power supply line that connects the current paths of the memory cells in the row direction for each row, and a word line that selects a previous memory cell for each row; A row decoder is connected between the common power supply line and the power supply, and a row decoder is applied from outside the device to decode a row address signal for selecting a previous row, and outputs a selection signal. , further comprising: a selection means that receives the selection signal from the row decoder and switches the connection between the common power supply line and the power supply; and a selection means connected between the word line and the output side of the row decoder; word line switching means for switching the connection between the word line and the row decoder when an operation mode switching signal is applied from outside the device; When instructing switching, one of the common power supply lines is selected by the selection signal, the selected common power supply line is connected to the power supply, and the other common power supply line is connected to the power supply. supplying power only to the memory cells connected to the selected common power supply line by cutting off the power supply line, detecting the presence or absence of leakage current, and when the operation mode switching signal instructs switching to the access mode. connects all the common power supply lines to the power supply, and the word line switching means connects the word line and the row decoder when the operation mode switching signal instructs switching to the inspection mode. When the operation mode switching signal instructs switching to access mode, A semiconductor memory device, characterized in that the word line and the row decoder are connected to each other so that the memory cell can be selected and an access operation can be performed. 5. Further comprising a fuse connected between the common power supply line and the power supply, and when the position of the memory cell where the leakage current occurs is detected, the fuse 5. The semiconductor memory device according to claim 1, wherein a portion connected to the common power supply line is fused to cut off a leakage path.