JPH082993A - Production of silicon single crystal of reduced crystal defects - Google Patents

Abstract

PURPOSE:To produce silicon single crystal of high pressure resistance to the oxide layer through the Czochralsky process. CONSTITUTION:In the production of silicon single crystal by the Czochralsky process, the time when a silicon single crystal to be grown passes through the temperature range from the melting point to 1,200 deg.C is set longer than 200 minutes, while from the 1,200 deg.C to 1,000 deg.C less than 150 minutes, when the crystal grows.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for producing a silicon single crystal with a high productivity by the Czochralski method (pulling method) with an improved oxide film withstand voltage.

[0002]

2. Description of the Related Art In recent years, due to the miniaturization of elements accompanying the high integration of semiconductor circuits, the insulating oxide film in the gate electrode portion of a MOS-LSI has been made thinner, and even such a thin insulating oxide film is used. It is required that the dielectric strength is high and the leak current is small when the device element is operating, that is, the reliability of the oxide film is high.

In this respect, the oxide film breakdown voltage of the silicon wafer manufactured from the silicon single crystal by the Czochralski method is measured by the wafer manufactured from the silicon single crystal by the floating zone melting method (FZ method) or the Czochralski method. It is known that the withstand voltage of the oxide film is significantly lower than that of an epitaxial wafer in which a silicon single crystal thin film is grown on the wafer (“Submicron device II, reliability of 3 gate oxide film”, Mitsumasa Koyanagi, Maruzen (shares). ), P70).

In the Czochralski method, it is known that the main cause of deterioration of the oxide film breakdown voltage is a crystal defect introduced during the growth of a silicon single crystal, and the crystal growth rate is extremely lowered (for example, 0.4 mm / It is also known that the breakdown voltage of an oxide film of a silicon single crystal by the Czochralski method can be significantly improved by (min or less) (for example,
(See JP-A-2-267195). However, in order to improve the oxide film breakdown voltage, if the crystal growth rate is simply reduced from 1 mm / min or more to 0.4 mm / min or less, the oxide film breakdown voltage can be improved, but the single crystal productivity is improved. It will be less than half, resulting in a significant cost increase.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of such problems, and an object thereof is to obtain a silicon single crystal by the Czochralski method with improved oxide film withstand voltage with high productivity. To do.

[0006]

Means for Solving the Problems The present inventors have conducted various investigations on the relationship between the thermal history received by a grown single crystal during the growth of a silicon single crystal and the introduced crystal defects by the Czochralski method. As a result of the examination, the present invention has been completed, and the gist thereof is that when a silicon single crystal is manufactured by the Czochralski method, the grown silicon single crystal has a high temperature range from the melting point of silicon to 1,200 ° C. during crystal growth. Make sure the transit time is at least 200 minutes, 1,2
It is a method for producing a silicon single crystal, which is characterized in that the time for passing through a low temperature region from 00 ° C to 1,000 ° C is 150 minutes or less.

The present invention will be described in detail below, but prior to the explanation, each term will be explained in advance. 1) The SC-1 cleaning, a mixed solution of ammonia and hydrogen peroxide _{(NH 4 OH: H 2 O} 2: H 2 O = 1: 1: 5) refers to a washing to remove the organic matter and particles in. Especially, the ability to remove particles is high. 2) COP [Crystal Originated Particles] means that when SC-1 cleaning is performed when cleaning the surface of a silicon wafer after polishing, pits are formed on the wafer surface, and when particles are measured on the wafer with a particle counter,
These pits are also detected as particles together with the original particles. Such a pit is called a COP in order to distinguish it from original particles. When the COP increases, the oxide film breakdown voltage deteriorates. ("Semiconductor manufacturer's wafer cleaning specifications and problems" ULSI Production Technology Emergency Report Editing Committee, P58-70, December 20, 1993, 1st edition, 1st edition, 1st edition
Imprinting) Due to such a phenomenon, the CZ silicon wafer according to the conventional method cannot be used as a wafer for a particle monitor (wafer for knowing the true number of particles) used in a device process or the like. It was 3) FPD [Flow Pattern Defect] means that a wafer is cut out from a grown silicon single crystal, the strained layer on the surface is removed by etching with a mixed solution of hydrofluoric acid and nitric acid, and then K ₂ Cr ₂ O is added.
Pits and ripples are created by etching the surface with a mixture of ₇ with hydrofluoric acid and water. This ripple pattern is referred to as FPD. The higher the FPD density in the wafer surface, the more defective the oxide film withstand voltage. (See Japanese Patent Laid-Open No. 4-192345) COP and FPD have a relationship of approximately 1: 1 as shown in FIG. Therefore, in order to improve the oxide film breakdown voltage of the silicon single crystal by the Czochralski method, this COP,
There is a need to reduce FPD.

[0008] The inventors of the present invention, why C
In order to clarify whether OP and FPD decrease and the oxide film withstand voltage improves, the growth rate was suddenly changed from high speed to low speed during crystal growth. It was found from the growth part) that the density had decreased. This is the process of eliminating crystal defects.
It is suggested that the high temperature range from the melting point of silicon to about 1,200 ℃ influences.

Therefore, during the crystal growth of the silicon single crystal,
The correlation between the FPD and the time required to pass through the high temperature range from the melting point of silicon to 1,200 ° C. was investigated for each pulling furnace having various temperature distributions, and the results shown in FIG. 1 were obtained. As can be seen from Fig. 1, when the transit time in this high temperature region is less than 200 minutes, the FPD rapidly increases. Therefore,
In order to reduce the FPD and obtain a silicon single crystal by the Czochralski method with a good oxide film breakdown voltage, the time for passing through the high temperature region from the melting point of silicon to 1,200 ° C during crystal growth should be 200 minutes or more. I found it necessary.

The time for passing through this high temperature region during crystal growth is
The crystal growth rate is extremely low (0.4 mm /
min or less), but as described above, the productivity is remarkably reduced and the object of the present invention cannot be achieved. Therefore, for example, as shown in Fig. 2 (b), the structure inside the furnace is expanded to the upper part with a heat insulating material to make it an upper heat-insulating type, and the melting point of silicon is 1,200 ℃
By extending the high temperature region up to, the time for the grown silicon single crystal to pass through was increased to 200 minutes or more.

However, the silicon single crystal pulled up from such an upper heat-retention type furnace has a COP of a small size of 0.16 μm or less, which can be reduced to half as compared with the conventional method, but is as slow as when grown at a low speed. Not diminishing, plus 0.16
It was observed that COPs with a large size of μm or more tended to increase as compared with the conventional method (see FIG. 4). To analyze this phenomenon,
When the crystal temperature when the crystal actually grew was investigated,
Fig. 3 curve (III) even in the upper heat insulation type (hereinafter referred to as slow cooling product)
As described above, it was found that the time required to pass through the high temperature range from the melting point of silicon to 1,200 ° C was 200 minutes or longer as intended, as in the case of the low speed product, but the above result was obtained. Therefore, it has been found that it is not possible to control the high temperature region alone in order to reduce the COP as much as a low speed product and improve the breakdown voltage of the oxide film.

Then, looking at the crystal cooling curve of FIG. 3 focusing on the low temperature region, the slow cooling product has a longer transit time in the low temperature region from 1,200 ° C. to 1,000 ° C. than the conventional product (quenched product: curve I). However, it is understood that the low speed product (curve II) having an extremely low COP density passes through the low temperature region after a longer time.

From these facts, the reason why the COP density is extremely low in the low speed product is that the point defect which is the core of COP itself is extinguished because it has passed through a high temperature region of 1,200 ° C. or higher for a long time. It was speculated that the material might have reacted with oxygen, etc., grown, aggregated, and decreased in density because it passed through a low-temperature region up to about ℃ for a long time. In fact, at the tip of the FPD,
Generally, pits of 2 to 5 μm size are observed at 300 to 700 pcs / cm ² , whereas low speed products have 20 μm at the tip of FPD.
A huge pit is observed. But its density is
It is extremely low at 100 cells / cm ² or less, and it is considered that the breakdown voltage of the oxide film itself does not decrease. Therefore, FP
Crystal defects such as D and COP are in the state of point defects in a high temperature range of about 1,200 ° C. or higher, and disappear due to paired annihilation reaction that occurs depending on the degree of supersaturation between slopes and slope diffusion, which have recently been reported at academic conferences. After going through the process, 1,200 ℃
It is considered that a huge defect is formed by the defect growth entangled with impurities such as oxygen in the low temperature range of about 1,000 ° C. (Jpn. J. Appl. Phys. Vol.32 (1993) P1740〜175
8, J. Eectorochem. Soc. Vol.140 No.11 November 199
That is, COP of low-speed products is extremely small only because there are few pits of 0.2 μm or less size detected as COP by particle counter, and they are more aggregated and grown. It forms a large pit.

Therefore, the present inventors have found that the passage time in the high temperature range from the melting point of silicon to 1,200 ° C. is 200
By making it more than a minute, the point defect which is the core of COP itself disappears (this point is also the case with slow-cooled products), and then the passage time in the low temperature range from 1,200 ° C to 1,000 ° C is 1
It was found that if the cooling time is 50 minutes or less, rapid cooling similar to the conventional product does not cause defect growth entangled with oxygen and the like, and a crystal without both the COP and the FPD having a huge pit at the tip can be grown. The present invention has been completed. The crystal cooling process in the present invention is as shown by the curve IV in FIG.
The crystal growth rate is the same as that of the conventional product or only about 10% lower. Therefore, the breakdown voltage of the oxide film can be improved with almost no decrease in productivity as compared with the conventional product. When a silicon single crystal is manufactured by the Czochralski method, the crystal temperature is gradually cooled from the melting point of silicon, 1,412 ° C, to room temperature.
Since this temperature distribution can be changed depending on the shape and position of the structure mainly composed of carbon installed in the furnace, the present invention is implemented by changing the structure inside the furnace as shown in FIG. 2C, for example. It is possible. Various methods can be considered for the method of changing the internal structure of the furnace, and the method is not limited to the method shown in FIG. In short, the crystal cooling process should be as shown by the curve IV in FIG.

[0015]

According to the present invention, since the passing time in the high temperature region from the melting point of silicon to 1,200 ° C. is about 1.5 times longer than that of the conventional method, the point defect density undergoes an annihilation process and the absolute density of crystal defect nuclei is increased. In addition, it is possible to prevent the defect growth or aggregation process by shortening the transit time in the low temperature range from 1,200 ℃ to 1,000 ℃ to 150 minutes or less.

[0016]

[Example] 18 "φ quartz crucible by Czochralski method,
50 kg of polycrystalline silicon as a raw material was charged, and crystals of 6 ″ φ, orientation <100> were pulled in four modes. The relationship between these in-furnace structures and the crystal cooling process is as shown in Table 1. I) Quenched product by the conventional method (Comparative Example 1), (II)
Low-speed product with the same furnace structure as the quenched product, growth rate 0.4 mm / m
in (Comparative Example 2), (III) Slowly cooled product from the melting point of silicon to 1,000 ° C (Comparative Example 3), (IV) Slow cooling from the melting point of silicon to 1,200 ° C, rapid cooling from 1,200 ° C to 1,000 ° C This is the present invention (Example).

[0017]

[Table 1]

After crystal growth, PW processing (mirror polishing) was performed, and then the liquid temperature was adjusted with a SC-1 cleaning liquid having a liquid composition of NH ₄ OH: H ₂ O ₂ : H ₂ O = 1: 1: 5. Washing was performed while maintaining the temperature at 77 ° C. After that, the number of particles was counted by a particle measuring instrument LS-6030. Note that SC-1 cleaning and particle measurement were repeated 5 times in order to distinguish them from exogenous particles. The results are shown in FIG. 4 for each COP size distribution after SC-1 washing was repeated 5 times. (I) is
The defect nucleus density is high because it is rapidly cooled in the high temperature range of 1,200 ° C or higher, but it is also rapidly cooled even at 1,200 ° C or lower, so there is only a large amount of COPs with a small size of 0.10 to 0.16 μm without going through the growth process. . In (II), it is considered that the defect nucleus density is low because the high temperature region of 1,200 ° C or higher is of the slow cooling type.
Since it is an extremely slow cooling type in the low temperature range of 1,200 ° C or less, defects are extremely grown and aggregated and become huge, so it is considered that COP is not counted. (III) is
As in (II), the high temperature region above 1,200 ° C is a slow cooling type, so the defect nucleus density is considered to be low. The low temperature range below 1,200 ° C is not as slow as low-speed products, but since it is a slow cooling type, C
It is considered that a size-up tendency occurred in the quenched product (I) as seen in the OP size distribution. In (IV), the point defect disappearance process is performed in the high temperature range of 1,200 ° C or higher, and the defect growth process in the low temperature range of 1,200 ° C to 1,000 ° C is not performed.
It is considered that P can be reduced. The growth rate of (IV) was only about 10% lower than that of (I).

[0019]

According to the present invention, it is possible to reduce COP and FPD of a silicon single crystal produced by the Czochralski method and improve the withstand voltage of an oxide film without lowering the crystal growth rate and thus improving the productivity. It can be done without significantly lowering. Moreover, the obtained silicon single crystal does not include FPDs having huge pits such as those having a reduced crystal growth rate. Moreover, since the COP is small, the silicon wafer for particle monitor, which has been difficult to manufacture by the conventional Czochralski method,
The present invention enables supply. Therefore, it is possible to provide a silicon single crystal by the Czochralski method which is as good as the conventional cost and is high in quality, and its utility value in the industrial field is extremely high.

[Brief description of drawings]

FIG. 1 is a diagram showing a relationship between a high temperature passage time and FPD.

FIG. 2 (a) is a schematic view showing a furnace internal structure of a quenched product according to a conventional method. (B) It is the schematic which showed the furnace internal structure of the slow cooling product by an upper heat retention type. (C) It is the schematic which showed an example of the furnace internal structure at the time of implementing this invention.

FIG. 3 is a diagram showing a crystal cooling process for each in-furnace structure.

FIG. 4 is a diagram showing the results of COP for each crystal cooling process.

FIG. 5 is a diagram showing a relationship between COP and FPD.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Chamber 2 ... Silicon single crystal 3 ... Crucible 4 ... Carbon heater 5 ... Thermal insulation material 6 ... Upper extension thermal insulation material 7 ... Thermal insulation material for this invention

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hirotoshi Yamagishi, inventor Hirotoshi Yamagishi, 2-13-1, Isobe, Annaka-shi, Gunma, Shin-Etsu Semiconductor Co., Ltd., Semiconductor Isobe Research Laboratory (72) Masahiro Sakurada Odakura, Nishigomura, Nishishirakawa-gun, Fukushima Prefecture No. 150 Taihei, Shin-Etsu Semiconductor Co., Ltd. Shirakawa factory

Claims (1)

[Claims] 1. When manufacturing a silicon single crystal by the Czochralski method, the time during which the grown silicon single crystal passes through a high temperature range from the melting point of silicon to 1,200 ° C. during crystal growth is 200 minutes or more. And then 1,2
A method for producing a silicon single crystal, wherein the time for passing through a low temperature range from 00 ° C to 1,000 ° C is 150 minutes or less.