JPH08297644A - Competitive operation testing system for computer system - Google Patents

Abstract

PURPOSE: To perform a high-accuracy test by simultaneously executing the competitive operation test with plural processors in a computer system composed of multiplex processors. CONSTITUTION: Initial setting required for a test instruction is performed with respective instruction processors 20, 21...2n and when the test instruction is issued, an execution control and monitor part 50 stops the instruction processors and reports the stop of instruction processors through a control interface to an inter-processor control part 6. When all the instruction processors are turned to the stop state, the processor control part 6 outputs a start request to execution control and monitor parts 50, 51...5n of all the processors 20, 21...2n. Thus, all the instruction processors 20, 21...2n simultaneously restart operation and execute instructions to be tested. Thus, since the plural processors efficiently execute the competitive operation test at the same timing without fail, high test accuracy can be secured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a competitive operation test method for a computer system having a multiprocessor structure, and particularly, to reliably and easily create a state in which access requests for devices shared by a plurality of instruction processors simultaneously compete. The present invention relates to a competitive operation test of a computer system capable of performing a highly accurate test under that environment.

[0002]

2. Description of the Related Art In a conventional competitive operation test method for a computer system having a multiprocessor configuration, a test program of a specific instruction processor starts another instruction processor, and thereafter, an instruction under test is issued to realize a competitive operation test. are doing.

As a conventional technique relating to the competitive operation test of this type of computer system, for example, the technique described in Japanese Patent Laid-Open No. 05-265793 is known.

The conventional competitive operation test method will be described below with reference to FIG. 9 showing a configuration using two instruction processors of the multiple processors.

In the instruction processor 0, the test program initialization section 10a and the test program tested instruction section 10
b and the test program result judgment unit 10d are executed, the instruction processor 1 executes the test program tested instruction unit 1
0c is executed. First, the initial setting unit 10a of the instruction processor 0 sets the data of the shared storage device and buffer required for the competitive operation test. Next, the instruction part under test 10
At b and 10c, the instruction processors 0 and 1 issue a test instruction to perform a competitive operation test on a shared storage device or buffer. At this time, the instruction processor 0 sends a start request to the instruction processor 1, activates the instruction processor 1 and prepares an environment in which the instruction processors 0 and 1 compete and execute, and issues a command under test to perform a competitive operation test. To do. When the execution of the instruction under test is completed in the instruction under test section, the instruction processor 0 sends a stop request to the instruction processor 1 to bring the instruction processor 1 into the stopped state. Next, in the test program result determination unit 10d, the instruction unit under test 10
The data of the storage device and the buffer tested by b and 10c are collected and the test result is determined.

[0006]

In order to simultaneously execute the instruction under test among a plurality of instruction processors in the above-mentioned conventional technique, it is necessary for the test program to perform processing for timing with other instruction processors. There is a problem that it is not possible to judge whether the competitive operation test by execution has been surely executed.

Further, in the above-mentioned prior art, there is a problem that a test program has a narrow utilization range because only one competing operation occurs each time.

An object of the present invention is to solve the above problems of the prior art and to execute a highly accurate competitive operation test by surely executing instructions under test among a plurality of instruction processors at the same timing.

[0009]

In order to achieve the above object, a test program is provided in a competitive operation test of a computer system under test including a plurality of instruction processors and a storage device and a buffer shared by each instruction processor. Execute by each instruction processor, stop the instruction processor running the test program at the end of the initial setting processing of each test program, and all at once when the initial setting processing of all the test programs ends Run the instruction processor.

This makes it possible to reliably and easily carry out a competitive operation test of simultaneous execution.

Further, when an instruction to access an arbitrary area of the storage device shared by each instruction processor is detected in the test program, the instruction is treated as an instruction to be tested, thereby expanding the range of use of the test program. Is possible. Furthermore, by changing the method of accessing the memory device for the instruction under test and the timing of execution of the instruction under test of any instruction processor, it becomes possible to expand the range of use of the test program.

[0012]

In the present invention, the test program is executed by a plurality of instruction processors in the computer system under test,
By issuing the instruction under test at the same timing, a high load is applied to the shared storage device and buffer, so that it is possible to carry out a highly accurate test.

[0013]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a diagram showing a typical system configuration of the present invention. A multiprocessor computer system 1 includes n instruction processors 0, 1, n (20, 21, 2n), buffers 30, 31, 3n, and a system. It is composed of a control device 8 and a storage device 9. Instruction processor 0, 1, n (2
0,21,2n) are the execution control monitoring units 50, 51, 5n.
The system control unit 8 includes an inter-processor control unit 6, control interface units 70, 71, 7n and a storage control unit 8A.

A test program 1 shown in FIG. 2 in which the multiprocessor computer system 1 is the computer system to be tested.
0 is executed. The test program 10 is the initial setting unit 10.
0, control command A110, tested command part 120, control command B130, and result determination part 140. next,
Processing of a competitive operation test by the test program 10 in a computer system having three instruction processor configurations will be described with reference to FIG.

The instruction processor 20, 21, 22 of the computer system under test is provided with an environment in which the test program 10 can be executed, and the instruction processor 20, 21, 22 starts executing the test program 10. At this time, the plurality of test programs 10 may be the same, and the timing of starting the test programs 10 may be processed independently for each instruction processor. In the instruction processor 0 (20), when the initialization processing 100 of the test program 10 is completed and the control instruction A110 is detected, the instruction processor 0 (20) causes the execution control monitoring unit 50 to stop the instruction processor 0 (20), It reports to the interprocessor control unit 6 via the control interface unit 70 that it has stopped. When the inter-processor control device 6 receives the stop reports from all the instruction processors 20, 21, 22,
The start instruction is given to all the instruction processors 20, 21, 22 via the control interface units 70, 71, 72. By this control, the instruction part 120 to be tested is simultaneously executed in all the instruction processors 20, 21, 22 to carry out the competitive operation test. Continuously, each instruction processor 20, 2
When the instruction-under-test section 120 ends in 1 and 22, the result judging section 140 confirms the validity of the competitive operation test result and ends the test.

According to this embodiment, all instruction processors 2
It is possible to realize reliable simultaneous execution of the instruction under test in 0, 21, and 22 and to carry out a highly accurate competitive operation test.

Next, a detailed method for realizing the simultaneous execution of the instruction unit under test 120 will be described with reference to FIGS. 4, 5, 6, and 7.

FIG. 4 is a diagram showing the functions of the execution control monitoring units 50, 51, 5n incorporated in the instruction processors 20, 21, 2n. The execution of the control instruction A110 by the instruction processors 20, 21, 2n operates. It will be a trigger for the start. The execution control monitoring units 50, 51, and 5n stop the instruction processor that has executed the control instruction A110 by the instruction processor stopping unit 500, and subsequently monitor information (530) creating unit 510.
5, the monitoring information 530 having the instruction processor number information 531 and the restart condition monitoring information shown in FIG. 5 is created. However, it is not limited to a simple competing operation by simultaneously executing the instruction immediately after the control instruction A110. The monitoring memory information 533 is also created in order to make it possible to realize the conflicting operation by simultaneously executing the instructions of the memory address and the access type (fetch type, store type, and both) specified in 1. Subsequently, the monitoring information (530) output unit 520 reports the created monitoring information 530 to the inter-processor control unit 6 via the control interface units 70 to 7n.

The inter-processor control section 6 shown in FIG. 6 performs processor restart processing based on the monitoring information 530 sent from the control interface sections 70, 71 and 7n. FIG. 7 shows a detailed flow of the processing. First, in process 600, it is determined whether the monitoring information 530 is received first, and if it is not the first, the processes in and after the process 603 are processed. If it is the first, the monitoring information 530 is processed in process 601. The restart condition information 532 is taken in to create the restart condition information 62 as internal information, and in step 602 the instruction processor state information 61 is initialized. The restart condition information 62 and the instruction processor status information 61
Is data 620 to 62n and 610 showing the state of each of the instruction processors 20, 21 and 2n.
It has 61n and is represented by "0" during operation and by "1" during stop. Subsequently, in process 603, the monitoring information 5
The instruction processor status information 61 corresponding to the instruction processor number information 531 of 30 is updated, and in step 604, the restart determination unit 66 sends a restart signal 68 to all the instruction processors 2 via the control interface units 70, 71, and 7n.
It is sent to 0, 21, 2n at the same time. At this time, if the restart signal 68 indicates "1", all the instruction processors 20, 2
1 and 2n are activated at the same time, and an arbitrary instruction causes a conflicting operation.

Simultaneous execution of an arbitrary access address and access type instruction to the storage device 9 can be realized by the method described below. The control interface units 70, 71, and 7n include the instruction processors 20, 21 and 2, respectively.
Since it is located on the signal line from n to the storage control device 8A via the system control device 8, it is possible to suppress access to the storage device 9 and obtain access address and access type information.
The monitoring memory information 533 created by 0, 51, and 5n is processed by the inter-processor control device 6 by the entire control interface unit 7
0, 71, 7n, and the control interface units 70, 71, 7n have a function of suppressing an access request of a specified address and type, a function of notifying the inter-processor control device 6 of the suppression, and a function between processors. The control device 6 has a function of canceling the access inhibition to the storage device 9 by a restart signal, and further, in the processing 603 of the interprocessor control device 6 described above, the instruction processor state information 61 corresponding to the instruction processor number information 531. Of the control interface units 70, 71, 7n
By making it possible to issue an access request from the device even by the suppression notification, it is possible to execute arbitrary access addresses and access type instructions simultaneously.

FIG. 8 is a flow chart of an embodiment in which the present invention is applied to a logic circuit simulation of a multiprocessor structure.

Here, of the multiple processor configuration, two instruction processors are used, and in the logic circuit model 80 whose normality has been confirmed, each processor 800, 801 is stopped in the same manner as the above-mentioned test method, When the instruction processors 800 and 801 of the above are stopped, the logic circuit model 80 whose normality is confirmed passes the data of the buffer and the storage device set in the initialization processing to the logic circuit model under test 81, and the logic circuit model under test is tested. At 81, all the instruction processors under test 810 and 811 are operated at the same time, and the instruction under test section 120 of the test program 10 is processed at the same time, whereby the competitive operation test can be carried out. Transfer the data in the buffer and storage device to the logic circuit model 80 whose normality is confirmed, and confirm the normality. In the logic circuit model 80 that is, to confirm the validity of the contention operation test by treating the result determination unit 140 of the test program, the test is terminated.

According to this embodiment, only the competitive operation test can be executed in the logic circuit model 81 under test.

Further, when the inter-processor controller 6 gives a start instruction to all the instruction processors 20, 21, 2n, the restart signal 60 to any instruction processor is delayed, so that a variety of test variations are possible. .

[0025]

As described above, according to the present invention,
It is possible to reliably, easily and efficiently perform a competitive operation test with high accuracy and high reliability on a device shared by a plurality of instruction processors.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a schematic diagram showing the configuration of a test program.

FIG. 3 is a flowchart of a competitive operation test process in a computer system according to an embodiment of the present invention.

FIG. 4 is a configuration diagram of an execution control monitoring unit.

FIG. 5 is a configuration diagram of monitoring information.

FIG. 6 is a configuration diagram of an inter-processor control unit.

FIG. 7 is a flowchart of an inter-processor control unit according to an exemplary embodiment of the present invention.

FIG. 8 is a flow chart when the present invention is implemented by logic simulation.

FIG. 9 is a flowchart of an example of a conventional competitive operation test.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Multiprocessor computer system, 6 ... Buffer control part, 8 ... System control device, 9 ... Storage device, 10 ... Test program, 20, 21, 2n ... Instruction processor 0, 1, n, 30, 31, 3n ... buffer,
50, 51, 5n ... Execution control device, 61 ... Instruction processor status information, 62 ... Reboot condition information, 66 ... Reboot determination unit, 68 ... Reboot signal, 70, 70, 7n ... Control interface unit, 80 ... Normal A logical model whose property is confirmed, 81 ... Logical model under test, 500 ... Instruction processor stopping unit, 510 ... Monitoring information creating unit, 520
... monitoring information output unit, 530 ... monitoring information.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuyuki Honma 1 Horiyamashita, Hadano City, Kanagawa Hitachi General Computer Division (72) Inventor Satoshi Someya 1 Horiyamashita, Hadano City, Kanagawa Hitachi Computer Co., Ltd. In electronics

Claims (3)

[Claims] 1. In a computer system having a plurality of instruction processors, a storage device shared by each instruction processor and various buffers, initialization is performed by a test program for each instruction processor, and a storage device required for the test is provided. A competitive operation test method characterized in that after setting the data in the buffer, all instruction processors issue the instruction under test at the same time. 2. The computer system according to claim 1, wherein an instruction for accessing an arbitrary area of a storage device shared by each instruction processor in the test program in the test method operates as an instruction under test. Competitive operation test method. 3. The competing operation test of a computer system according to claim 1, wherein the access method of the instruction under test is classified for each processor, and an arbitrary combination is operated by issuing the instruction under test. method.