JPH08293428A - Chip capacitor - Google Patents

Abstract

PURPOSE: To reduce the size of the total configuration of a chip capacitor, by providing an electrode for connecting an external wiring therewith on the top surfaces of both its buffer material made of an insulator and the predetermined region of its upper electrode, and by reducing the area of the chip capacitor while preventing its dielectric thin, film from being damaged by the connection of the external wiring. CONSTITUTION: On the top surface of an upper electrode 18, except a predetermined region 18a, a buffer material 20 made of an insulator with a predetermined thickness is formed. As the buffer material 20, the polyimide of an organic material or the like is used. Further, on the top surfaces of both the buffer material 20 and the predetermined region 18a of the upper electrode 18, an electrode 22 is formed as one electrode for connecting an external wiring therewith. In case of connecting the external wiring with the electrode 22, a region 22a or 22b positioned on the buffer material 20 is used. In case of a wire-bonding, etc., when a force F is applied to the region 22a or 22b of the electrode 22 from above it, the force F is absorbed by the buffer material 20. Therefore, a dielectric thin film 16 is prevented from being damaged by the force F.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to chip capacitors, and more particularly to hybrid integrated circuits (Hyb).
The present invention relates to a chip capacitor suitable for use as a component such as a rid integrated circuit (hybrid IC).

[0002]

2. Description of the Related Art Generally, when forming a hybrid circuit, a chip capacitor or the like is used as a component according to the circuit structure. It is known that the capacitance depends on the dielectric constant of the dielectric used for the dielectric layer in the chip capacitor, the thickness of the dielectric layer, and the area of the dielectric layer and the electrodes sandwiching the dielectric layer. There is.

That is, if a dielectric having a high dielectric constant is used, the thickness of the dielectric layer is reduced, or the area of the dielectric layer and the electrodes sandwiching the dielectric layer is increased, the static capacitance of the chip capacitor is reduced. The electric capacity can be increased.

FIG. 3 shows an explanatory view of a sectional structure of a conventional chip capacitor, for example, a chip capacitor formed by laminating dielectric ceramics. The upper electrode 204 is formed on the upper surface of the dielectric ceramic 202 as a layer, and the lower electrode 206 is formed on the lower surface of the dielectric ceramic 202.

In such a chip capacitor 200, since the dielectric ceramic 202 made of a fired body having a high fracture strength is used as the dielectric layer, the dielectric layer 202 is formed on the upper electrode 204 at the time of wire bonding in the mounting process, for example. Even if a force F from the direction is applied,
It is less likely that the dielectric ceramic 202 is damaged and the upper electrode 204 and the lower electrode 206 are short-circuited.

Therefore, as an electrode for connection in wire bonding, the upper electrode 204 can be used as it is as one electrode for wire bonding, and the lower electrode 206 can be used as the other electrode for wire bonding. Since it can be used as it is, it is not necessary to provide an installation space for electrodes for connection at the time of wire bonding, and the area of the chip capacitor 202 can be reduced.

However, in the chip capacitor 200 using the dielectric ceramic 202, it is possible to appropriately select and use a material having a high dielectric constant as the dielectric ceramic 202, but the dielectric ceramic 202 is a fired body. For this reason, the thickness is inevitably large. Therefore, in order to obtain a high capacitance of 1000 pF or more, there is a problem that the area of the chip capacitor 200 becomes extremely large. there were.

On the other hand, as a conventional chip capacitor,
A chip capacitor in which a dielectric layer is formed by using a thin film is also known, and FIG. 4 shows an explanatory view of a cross-sectional structure of a chip capacitor in which a dielectric layer is formed by using a thin film. The capacitor 300 includes a lower electrode 304 formed in a predetermined area on the upper surface of the substrate 302 and a dielectric thin film 30 formed in a predetermined area on the upper surface of the lower electrode 304.
6 and the upper electrode 3 formed on the upper surface of the dielectric thin film 306.
08, and the function of the capacitor is realized by the laminated structure of the lower electrode 304, the dielectric thin film 306, and the upper electrode 308.

By the way, such a chip capacitor 3
In 00, since the dielectric thin film 306 is used as the dielectric layer, it is possible to reduce the thickness of the chip capacitor 300. However, for example, at the time of wire bonding in the mounting process, the upper electrode 308 is used. When a force F from above is applied to the dielectric thin film 30
6 may be damaged and the upper electrode 308 and the lower electrode 304 may be short-circuited. Therefore, as one electrode for connection in wire bonding, the upper electrode 308 is connected via the air bridge (aerial wiring) 310.
The electrode 312 connected to the substrate was formed on the substrate 302 (note that in FIG. 4, the lower electrode 304 is used as it is as the other electrode for wire bonding, and the region 304a is connected. The surface.).

That is, in the chip capacitor 300 using the dielectric thin film 306 as the dielectric layer, the substrate 30
Since it is necessary to provide an electrode 312 for connection in wire bonding on the chip capacitor 2,
There is a problem that the area of 00 becomes large.

That is, the dielectric thin film 306 is used as the dielectric layer.
In an attempt to reduce the area of the chip capacitor 300 using the chip capacitor 300 using
Since it is necessary to secure a space for providing the electrode 312 for connection in wire bonding on the 2 above,
As the space for the electrode 312 is secured, the areas of the dielectric thin film 306 and the upper electrode 308 have to be narrowed, which causes a problem that the obtained electrostatic capacitance is reduced.

The present invention has been made in view of the above-mentioned various problems of the prior art, and an object thereof is to use a dielectric thin film as a dielectric layer to increase the thickness of a chip capacitor. In addition to reducing the thickness, an electrode for external wiring is provided on the upper electrode through a cushioning material made of an insulator with a predetermined thickness, so that the force applied during wire bonding in the mounting process A chip that reduces the size of the chip capacitor while preventing damage to the dielectric thin film
It is intended to provide a capacitor.

[0013]

To achieve the above object, a chip capacitor according to the present invention comprises a substrate, a lower electrode formed on the upper surface of the substrate, and a dielectric formed on the upper surface of the lower electrode. Body thin film, an upper electrode formed on the upper surface of the dielectric thin film, a buffer material made of an insulator having a predetermined thickness formed on the upper surface of the upper electrode except a predetermined region, and the buffer material And an electrode for connection with an external wiring formed on the upper surface of the predetermined region on the upper electrode.

[0014]

[Function] Since the buffer material is formed between the connection electrode and the upper electrode, even if a force is applied to the connection electrode during wire bonding during the mounting process, etc., the buffer material absorbs the force. Thus, the dielectric thin film is protected and its damage can be prevented.

Therefore, the dielectric thin film can be formed extremely thin, and the chip capacitor can be thinned.

Further, since the electrodes for connecting to the external wiring are provided on the upper electrode with the cushioning material interposed therebetween, it is necessary to secure a space for providing the electrodes for connecting to the external wiring on the substrate. Therefore, the area of the chip capacitor can be reduced.

As described above, since the thickness of the chip capacitor can be reduced and the area of the chip capacitor can be reduced, the overall structure of the chip capacitor can be miniaturized.

[0018]

Embodiments of the chip capacitor according to the present invention will now be described in detail with reference to the drawings.

FIG. 1 is an explanatory view showing a sectional structure of a chip capacitor according to a first embodiment of the present invention. A chip capacitor 10 includes a lower electrode 14 formed on an upper surface of a substrate 12 and a lower electrode. A dielectric thin film 16 formed on a predetermined region of the upper surface of the dielectric thin film 14 and an upper electrode 18 formed on the upper surface of the dielectric thin film 16.
The function of the capacitor is realized by the laminated structure of 6 and the upper electrode 18.

Further, on the upper surface of the upper electrode 18, a cushioning material 20 made of an insulating material is formed with a predetermined thickness except for the predetermined region 18a.

The buffer material 20 has an insulating property and can be formed to have a predetermined thickness (for example, a thickness of about 10 μm), and also has elasticity, good high frequency characteristics, and dielectric loss. Is preferable, and for example, an organic material such as polyimide can be used.

Then, on the upper surface of the predetermined region 18a of the buffer material 20 and the upper electrode 18 formed as described above, as one electrode for connection to an external wiring (not shown),
For example, the electrode 22 used at the time of wire bonding in the mounting process is formed. When connecting an external wiring or the like to the electrode 22, the regions 22a and 22b located on the cushioning material 20 are used.

The lower electrode 14 is used as one electrode for connection to an external wiring (not shown), and the external wiring is connected to the region 14a.

In the above structure, the area 2 of the electrode 22 is used at the time of wire bonding in the mounting process.
When the force F from above is applied to 2a or the region 22b, the force F is absorbed by the cushioning material 20.

That is, since the cushioning material 20 acts as a cushion against the force F, the dielectric thin film 16 is not damaged by the force F, and the dielectric thin film 16 is protected from the force F.

As a result, the dielectric thin film 16 can be made extremely thin, so that the thickness of the chip capacitor 10 can be reduced and the capacitance can be increased. Like

Since it is not necessary to secure a space for forming the electrode 22 used at the time of wire bonding in the mounting process in the space on the upper surface of the substrate 12, the area of the chip capacitor 10 can be reduced. You can

As described above, since the thickness of the chip capacitor 10 can be reduced and the area thereof can be reduced, the chip capacitor 10 can be downsized as a whole, and thus, the unit area per unit area can be reduced. Capacitance can be increased.

FIG. 2 is an explanatory view showing a sectional structure of a chip capacitor according to a second embodiment of the present invention. The chip capacitor 100 has a lower electrode formed on the upper surface of a substrate 102 having conductivity. 104, a dielectric thin film 106 formed on the upper surface of the lower electrode 104, and a dielectric thin film 106.
And the upper electrode 108 formed on the upper surface of the above, and the function of the capacitor is realized by the laminated structure of the lower electrode 104, the dielectric thin film 106, and the upper electrode 108.

Further, on the upper surface of the upper electrode 108, a cushioning material 110 made of an insulating material is formed with a predetermined thickness except for the predetermined region 108a.

As in the first embodiment, the cushioning material 110 has an insulating property and can be formed to have a predetermined thickness (for example, a thickness of about 10 μm), and also has elasticity. It is preferable to use a material having good high frequency characteristics and a small dielectric loss, and for example, an organic material such as polyimide can be used.

Then, on the upper surface of the predetermined region 16a of the buffer material 110 and the upper electrode 108a formed as described above, as one electrode for connection to an external wiring (not shown), for example, wire bonding in a mounting process. An electrode 112 used at the time and the like is formed. Then, when connecting an external wiring or the like to the electrode 112, the regions 112a, 11 located on the cushioning material 110
2b is used.

An electrode 114 is provided on the lower surface of the substrate 102 as the other electrode for connecting to an external wiring (not shown).

Therefore, in this second embodiment,
Since it is not necessary to use the upper surface of the lower electrode 106 for connecting to the external wiring, the dielectric thin film 106 and the upper electrode 104 can be formed on the entire upper surface of the lower electrode 106, so that the same static electricity per unit area can be obtained. If the capacitance is obtained, the area of the chip capacitor 10 can be further reduced as compared with the first embodiment.

Therefore, if the chip IC according to the present invention is used to form a hybrid IC, the hybrid IC can be miniaturized.

[0036]

As described above, the present invention reduces the thickness of a chip capacitor by using a dielectric thin film as a dielectric layer, and it is more effective than an insulator having a predetermined thickness on the upper electrode. Since the electrodes for external wiring are provided via the buffer material, it is possible to reduce the area of the chip capacitor while preventing damage to the dielectric thin film due to the force applied during wire bonding in the mounting process. Therefore, there is an excellent effect that a chip capacitor having a reduced overall structure can be realized.

[Brief description of drawings]

FIG. 1 is an explanatory view showing a cross-sectional structure of a chip capacitor according to a first embodiment of the present invention.

FIG. 2 is an explanatory view showing a sectional structure of a chip capacitor according to a second embodiment of the present invention.

FIG. 3 is an explanatory diagram showing a cross-sectional structure of a conventional chip capacitor using a dielectric ceramic as a dielectric layer.

FIG. 4 is an explanatory diagram showing a cross-sectional structure of a conventional chip capacitor using a dielectric thin film as a dielectric layer.

[Explanation of symbols]

10, 100, 200, 300 Chip capacitor 12, 102, 302 Substrate 14, 104, 206, 304 Lower electrode 16, 106, 306 Dielectric thin film 18, 108, 204, 308 Upper electrode 20, 110 Buffer material 22, 112 Electrode for connection 114 Electrode for connection 202 Dielectric ceramic 310 Air bridge 312 Electrode for connection

Claims (4)

[Claims] 1. A substrate, a lower electrode formed on the upper surface of the substrate, a dielectric thin film formed on the upper surface of the lower electrode, an upper electrode formed on the upper surface of the dielectric thin film, and the upper portion. Connection between a cushioning material made of an insulator having a predetermined thickness and formed on the upper surface of the electrode excluding a predetermined area, and an external wiring formed on the cushioning material and the upper surface of the predetermined area on the upper electrode And an electrode for the chip capacitor. 2. The chip capacitor according to claim 1, wherein the lower electrode is an electrode for connection with an external wiring. 3. The chip capacitor according to claim 1, wherein the substrate is made of a conductive material, and an electrode for connecting to an external wiring is formed on a lower surface of the substrate. . 4. The chip capacitor according to claim 1, wherein the dielectric thin film is formed of polyimide.