JPH08288858A - Variable length code decoding device - Google Patents

Abstract

PURPOSE: To provide the variable length code decoding device which can be used for code data, whose code length cannot be unequivocally detected from the ID code, and requires only the decoding table capacity corresponding to the total number of code data. CONSTITUTION: Code data having a maximum or minimum value in a set of code data of the same code length is stored in a code data storage means 11 as a boundary code with respect to each code length. By code length calculation means 12, the value of data of a certain length from the head of input code data is compared with values of respective boundary codes stored in the code data storage means 11, and the code length of code data to be decoded is calculated based on the comparison results. The difference value between input code data and the boundary code having the same code length out of boundary codes in the code data storage means is obtained by a difference value determining means 13. Decoded data is obtained from this difference value by a decoded data calculation means 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable length code decoding device for sequentially decoding a series of code data coded by a variable length code.

[0002]

2. Description of the Related Art Variable-length coding occurs as a whole by assigning a short code to a frequently-occurring information sample to a fixed-length information sample and a long code to an infrequently-occurring information sample. This is a coding method that reduces the amount of information.

When a series of code data coded by this type of variable length code is decoded on the receiving side, since each code data forming the received data has a different length, the received data is received. It is necessary to decode each code data while detecting the code length of each code data in the data, and a variable length code decoding device for that purpose is provided on the receiving side.

A conventional variable-length code decoding apparatus receives an input buffer for receiving a series of code data, receives a series of code data from the input buffer, and shifts this data in the upper direction to locate the code data. From the barrel shifter, the decoding table that decodes the output data of the barrel shifter into fixed-length information, and the code length table that detects the code length of the first code data in the output data of the barrel shifter and outputs it as the shift amount to the barrel shifter. Was configured.

In such a configuration, since a code data having an arbitrary code length and an unknown code length is associated with one fixed length data, a decoding table having an enormous capacity is required. For example, for simplicity, consider a case where the following three types of code data A, B, and C are decoded by a decoding table. Code data A: △△ Code length 2 bits Code data B: △△△ Code length 3 bits Code data C: △△△△ Code length 4 bits

In this case, 4 bits are taken out from the head of the output data of the barrel shifter, and this 4-bit data is Δ
If ΔXX, fixed length data corresponding to code data A, Δ
If ΔΔX, the data corresponding to the code data B is output, and if ΔΔΔΔ, the data corresponding to the code data C is output to perform decoding. Here, X is an unspecified value.

However, since it is not possible to create a decoding table that accepts an unspecified value as an address, the address of the decoding table is eventually set to 4 bits and the following fixed length data is stored at each address.

<Address> <Fixed Length Data> ΔΔ00 Fixed Length Data Corresponding to Code Data A ΔΔ01 Fixed Length Data Corresponding to Code Data A ΔΔ10 Fixed Length Data Corresponding to Code Data A ΔΔ11 Fixed length data corresponding to code data A ΔΔΔ0 Fixed length data corresponding to code data B ΔΔΔ1 Fixed length data corresponding to code data B ΔΔΔΔ Fixed length data corresponding to code data B

As described above, the conventional variable-length code decoding apparatus described above has a problem that the capacity of the decoding table becomes larger than necessary in comparison with the number of types of code data.

As a method considering this problem, there is a decoding method in which one address can be assigned to one code and the capacity of the decoding table can be suppressed to the total number of codes. It is proposed in JP-A-5-152973.

Japanese Unexamined Patent Publication No. 5-95292 and Japanese Unexamined Patent Publication No. 5-1
In the technique disclosed in Japanese Patent No. 52973, when the contents of each piece of code data of a variable length code are preliminarily determined, as shown in FIG. 17, each piece of code data having the same code length has the same pattern (hereinafter referred to as “ID Code)). Then, when the decoding device decodes the reception data consisting of a series of code data, first, the I at the beginning of the reception data is
The code length is detected based on the D code. Then, based on the detected code length, the start address corresponding to the code length in the decoding table (hereinafter referred to as "offset")
Generate Then, the ID code is deleted from the received data, the displacement determined by the remaining portion is added to the offset, and the address of the decoding table corresponding to the code data is determined.

[0012]

However, depending on the method of generating the variable length code, the code length is not always obtained uniquely from the ID code. For example, in the case of the code shown in FIG. 18, the code length is obtained from the ID code. The length cannot be detected.
However, the decoding devices disclosed in Japanese Patent Laid-Open Nos. 5-95292 and 5-152973 are coded by a coding system configured to uniquely detect the code length from the ID code as shown in FIG. There is a problem in that it cannot be applied to code data encoded by a code system in which the code length cannot be uniquely detected from the ID code as shown in FIG.

In consideration of the above problems, the present invention is applied not only to a code configured to uniquely detect a code length from an ID code, but also to a code whose unique code length cannot be detected from an ID code. However, it is an object of the present invention to provide a variable-length code decoding device that can be used universally and that can suppress the capacity of the decoding table to the total number of codes.

[0014]

FIG. 1 shows the basic configuration of the present invention. That is, the present invention, in a decoding device for sequentially decoding a series of code data encoded by a variable-length code, selects the code data having the largest value or the code data having the smallest value from a set of code data having the same code length. A code data storage unit 11 that stores a boundary code for each code length is compared with an input code data string and each boundary code stored in the code data storage unit, and a code to be decoded based on each comparison result. A code length calculating means 12 for calculating the code length of data, and the same code length as the code length calculated by the code length calculating means among the boundary data stored in the code data to be decoded and the code data storing means. Difference value determining means 13 for determining a difference value with a code length
And a decoded data calculation unit 14 for obtaining decoded data from the difference value determined by the difference value determination unit.

[0015]

According to the above construction, when the code data coded by the variable length code is input, the boundary between the input code data string in the code length calculation means 12 and each code length stored in the code data storage means 11. The code length of the code data included at the beginning of the input code data string is calculated from the code. Then, the difference value determining means determines a difference value between the code data and one of the boundary codes stored in the code data storing means and having the code length calculated by the code length calculating means. Then, the decoded data is calculated by the decoded data calculation means based on the difference value determined by the difference value determination means.

[0016]

【Example】

<First Embodiment> A first embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 2 is a block diagram showing the variable-length code decoding apparatus according to this embodiment. This variable-length code decoding apparatus detects a code length by comparing a boundary code storage unit 21 storing a boundary code with input code data and each boundary code output from the boundary code storage unit 21. 22 and
An address calculator 23 that obtains a difference value between the input code data and the boundary code output from the boundary code storage unit 21, and generates an address of the decoding table 24 from the difference value; and the decoding table 2
4 and.

An example of a variable length code having a maximum code length of 8 bits is shown in FIG. In the following, a variable length code decoding apparatus for decoding coded data encoded by the variable length code shown in FIG. 3 will be described. In this embodiment, all types of code data to be handled are divided into sets having the same code length. Then, in each set, each code data having the same code length is sorted in ascending order, and the code data having the smallest value is determined as the boundary code in the set. This boundary code is used as a threshold when distinguishing the code data in the set from the code data belonging to the adjacent set having different code lengths. The details will be described later.

When the boundary code is extracted from the code system shown in the code table of FIG. 3, the boundary code of the set of code data of code length 2 is "00" and the boundary code of the set of code data of code length 3 is " 100 ", code length 4 is" 1010 ", code length 5 is" 11010 ", code length 6 is" 1111010 ", code length 7 is" 1111000 ", code length 8 is" 11111 ".
This boundary code is stored in the boundary code storage unit 21 for each code length as shown in FIG. 4. These boundary codes are arranged in the maximum code length 8 and the code length is less than 8 bits. As for the code, the bits are aligned on the lower bit side, and the upper empty bits are filled with "0".

FIG. 5 shows the contents of the decoding table 24. The decoding table 24 has address areas for the total number of code data. One address is assigned to each code data, and fixed length data (hereinafter, referred to as a decoded value) corresponding to the code data is stored in the address corresponding to the code data. Further, each decoded value corresponding to each code data having the same code length is stored in a continuous area of the decoding table 24. That is, in the decoding table shown in FIG. 5, addresses 0 to 1 are assigned as the storage areas of the decoded values of the code data of code length 2, and the address 2 is stored as the storage areas of the decoded values of the code data of code length 3. Is assigned, and the address 3 is assigned as a code length 4 area.
˜5, address 6 to 8 as code length 5 area, code length 6
Addresses 9 to 10, areas 11 to 14 as code length 7 areas, and address 1 as code length 8 areas
5 to 19 are assigned respectively.

Further, the arrangement of the decoded values in the area corresponding to each code length is stored in the order corresponding to the size of the code data having the same code length. Here, the decoded values are stored in the ascending order of the code data. ing. For example, taking code length 5 as an example,
When the respective code data having the code length 5 shown in FIG. 3 are arranged in the ascending order, they are “11010”, “11011”, and “11100”. Then, according to FIG. 3, the fixed length data corresponding to these are as follows.

<Code Data> <Fixed Length Data> “11010” 11 “11011” 9 “11100” 1

Therefore, in the area corresponding to the code length 5 of the decoding table shown in FIG. 5, according to the arrangement of the code data,
Each decoded value corresponding to each coded data is “11”,
The data is stored as decoded data in the order of "9" and "1". Here, the address where the boundary code of each code length is stored in the decoding table (for example, "11010" above)
Will be referred to as "boundary address" below.

FIG. 6 is a diagram showing the internal configuration of the code length calculation circuit 22 in FIG. The code length calculation circuit 22 compares the boundary code for each code length output from the boundary code storage unit 21 and the input code data with the comparators 61a to 6a.
1f, and a code length generation circuit 62 that generates a code length from the outputs of the comparators 61a to 61f. Comparator 6
1a compares the lower 3 bits of the boundary code having a code length of 3 with the upper 3 bits of the input code data, and the comparator 61b has a code length of 4
The lower 4 bits of the boundary code and the upper 4 bits of the input code data, and the comparator 61c compares the lower 5 bits of the boundary code of code length 5 and the upper 5 bits of the input code data with the comparator 61d.
Is the lower 6 bits of the boundary code of code length 6 and the upper 6 bits of the input code data, the comparator 61e is the lower 7 bits of the boundary code of code length 7 and the upper 7 bits of the input code data, and the comparator 61f is the code The 8-bit boundary code of 8 bits and the input code data of 8 bits are compared with each other. Comparators 61a-6
1f is "1" when the input code data is smaller than the boundary value
Otherwise, '0' is output.

The code length generation circuit 62 includes comparators 61a to 6a.
The code length is generated from the output of 1f, and the code length is output according to the output results of the comparators 61a to 61f, as shown in the correspondence table of FIG.

FIG. 8 is a diagram showing the internal configuration of the address calculator 23 in FIG. The address calculator 23 selects the boundary code corresponding to the code length output by the code length calculation circuit 22 from the boundary code output for each code length of the boundary code storage unit 21, and the input code data of the shifter. A barrel shifter 82 that shifts in the lower direction by the amount obtained by subtracting the code length from the bit width, and fills the upper empty bits with "0";
A subtractor 83 that subtracts the output of the selection circuit 81 from the output of the barrel shifter 82, a boundary address storage unit 84 that stores a boundary address for each code length, and a boundary address that corresponds to the code length output by the code length calculation circuit 22. And an adder 85 for adding the output results of the subtractor 83.

As described above, the boundary address is an address assigned to the boundary code of each code length. When the boundary address corresponding to each code length is extracted from the decoding table of FIG. 5, the boundary address of code length 2 is “0” and the code length is 3
Has a boundary address of "2", code length 4 is "3", code length 5 is "6", code length 6 is "9", and code length 7 is "1".
1 "and the code length 8 is" 15 ". This boundary address is stored in the boundary address storage unit 8 for each code length as shown in FIG.
Stored in 4.

Next, input code data "11110101"
A series of operations of the variable-length code decoding apparatus according to the present embodiment will be described by taking the process of decoding as an example.

First, the input code data is code length calculation circuit 2
2 and is compared with each boundary code value in the boundary code storage unit 21. The comparator 61a compares "111" with "100" and outputs "0". Similarly, the comparator 61b compares "1111" and "1010" with "0", the comparator 61c compares "11110" and "11010" with "0", and the comparator 61d has "111101" with "111".
111010 "is compared to" 0 "," 6111010 "and" 1111000 "are compared to" 0 "in the comparator 61e, and" 11110101 "to the comparator 61f.
And "11111000" are compared and "1" is output. The outputs of the comparators 61a to 61f are "0000".
As a result, the code length generation circuit 62 outputs the code length “7”.

Then, the code length "7" is sent to the address calculator 23.
Is input, and the selection circuit 81 selects the boundary code “01111000” having the code length “7”. In the barrel shifter 82, the input code data “11110101” is
One bit is shifted in the lower direction and "0" is added to the upper bit to become "01111010". "0111101
"0" and "01111000" are input to the subtractor 83 and the subtraction result "2" is output. The subtraction result “2” and the boundary address “11” corresponding to the code length “7” output from the boundary address storage unit 84 are input to the adder 85 and the addition result “1” is input.
3 ”. This addition result “13” is the decoding table 24.
Input code data "1111"
The decoded value "2" of the code "1111010" included at the beginning of "0101" is obtained.

<Second Embodiment> A second embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 10 is a block diagram showing the variable length code decoding apparatus according to the present embodiment. This variable-length code decoding device is provided with a boundary code storage unit 1 that stores a boundary code.
01, the code length calculation circuit 102 for detecting the code length by comparing the input code data with each boundary code output from the boundary code storage unit 101, and the code length output from the input code data and the code length calculation circuit 102. To decryption table 104
The address arithmetic unit 103 for generating the address of 1 and the decoding table 104.

The case of decoding the coded data coded by the variable length code will be described below based on the example of the code table of FIG. Further, in the present embodiment, the following description will be made on the assumption that the boundary code is the largest code among the code lengths.

When the boundary code is extracted from the code table of FIG.
The boundary code of the code length 2 is "01", the boundary code of the code length 3 is "100", and the code length 4 is "1100" and the code length 5 hereinafter.
Is "11100", code length 6 is "111011", code length 7 is "1111011", and code length 8 is "111111".
This boundary code is stored in the boundary code storage unit 101 for each code length as shown in FIG. 11. The boundary code is aligned with the maximum code length of 8, and codes less than 8 bits are on the lower bit side. The bits are aligned with each other, and the upper vacant bits are filled with "0".

FIG. 12 shows the contents of the decoding table 104. As shown in the figure, addresses 0 to 4 are assigned as storage areas for decoded values of code length 8, addresses 5 to 8 are assigned as storage areas for decoded values of code length 7, 9 to 10, addresses 11 to 13 as a code length 5 area, and address 14 as a code length 4 area
˜16, address 17 as code length 3 and code length 2
Addresses 18 to 19 are respectively allocated as the areas. The array of decoded values in each area for each code length is stored in the order according to the size of the code data of the same code length,
Here, the decoded values are stored in ascending order of coded data. For example, taking the code length of 5 as an example, when the code data of the code length of 5 is arranged in ascending order, “11010” and “110
11 "and" 11100 ", the decoded value corresponding to the code is stored in the order of" 11 "," 9 ", and" 1 "in this code data array in the area of the code length 5 of the decoding table. ing.

FIG. 13 shows the code length calculation circuit 1 in FIG.
2 is a diagram showing an internal configuration of 02. FIG. Code length calculation circuit 10
Reference numeral 2 denotes a comparator 131a that compares the boundary code output for each code length of the boundary code storage unit 101 with the input code data.
To 131f and a code length generation circuit 132 that generates a code length from the outputs of the comparators 131a to 131f.

The comparator 131a compares the input code data with the boundary code of code length 2, 131b compares the input code data with the boundary code of code length 3, and 131c compares the input code data with the boundary code of code length 4. , 131d is a comparison between input code data and a boundary code having a code length of 5, 131e is a comparison between input code data and a boundary code having a code length of 6, 131f is a comparison between input code data and a boundary code having a code length of 7. Do.

Here, the number of bits of the input code data and the boundary code input to the comparators 131a to 131f is the same bit (“1” in the code of FIG. 3) repeating pattern at the head common to the codes of the same code length. It is limited by the number of bits of the remaining data. For example, in 131e, input code data is compared with a boundary code having a code length of 6, but the same bit repeating pattern common to codes having a code length of 6 is "111", so the number of bits excluding this pattern is "3". Make a comparison. That is, the lower 3 bits of the upper 6 bits of the input code data are compared with the lower 3 bits of the boundary code of code length 6. Hereinafter, similarly, the comparator 131a compares the lower 2 bits of the boundary code having the code length 2 with the upper 2 bits of the input code data, and the comparator 131b.
Is the lower 2 bits of the boundary code of code length 3 and the lower 2 bits of the upper 3 bits of the input code data, and the comparator 131c is the lower 3 bits of the boundary code of code length 4 and the upper 4 bits of the input code data. The low-order 3 bits, the comparator 131d outputs the low-order 3 bits of the boundary code of code length 5 and the low-order 3 bits of the high-order 6 bits of the input code data, and the comparator 131f outputs the low-order 3 bits of the boundary code of the code length 7 and the input code data. The lower 3 bits of the upper 7 bits of are compared with each other. The comparators 131a to 131f output "1" when the input code data is larger than the boundary value, and output "0" otherwise.

The code length generation circuit 132 includes comparators 131a-131a.
The code length is generated from the output result of 131f, and FIG.
As shown in the correspondence table of, the code length is output according to the outputs of the comparators 131a to 131f.

The code length calculation circuit used in the second embodiment is
By reducing the bit width of the comparator that compares the input code data and the boundary code, the circuit scale can be reduced and the operation can be performed at high speed, as compared with the code length calculation circuit of the first embodiment.

FIG. 15 shows the address calculator 1 in FIG.
It is a diagram showing the internal configuration of 03. Address calculator 10
3 shifts the input code data in the lower direction by the amount obtained by subtracting the code length from the bit width of the shifter, and the upper empty bit is "0".
A barrel shifter 151 for storing the difference, a difference storage unit 152 that stores the difference between the boundary code and the boundary address for each code length,
The subtracter 153 is configured to subtract the difference corresponding to the code length output from the difference storage unit 152 and the output result of the barrel shifter 151.

When the boundary address of each code length is extracted from the decoding table of FIG. 12, the boundary address of the code length 2 is “19”, the boundary address of the code length 3 is “17”, and the code length 4 is “16”. , The code length 5 is “13”, the code length 6 is “10”, the code length 7 is “8”, and the code length 8 is “4”. Difference between the boundary address of each code length and the boundary code of each code length shown in FIG. 11 "boundary code-boundary address"
, Code length 2 is "-18", code length 3 is "-13", code length 4 is "-4", code length 5 is "15", code length 6 is "49", code length 7 is " 115 ”and the code length 8 is“ 24
8 ". This difference is stored in the difference storage unit 152 for each code length as shown in FIG. Here, "boundary code-boundary address" is stored, but the value of "boundary address-boundary code" may be stored. In that case, the subtractor 153 in the address calculator of FIG. 15 can be replaced by an adder.

The address calculator used in the second embodiment is
By storing the difference between the boundary code and the boundary address in the storage device in advance, a selection circuit and a subtracter are not required as compared with the address arithmetic unit of the first embodiment, so that the circuit scale can be reduced and the operation can be performed at high speed. be able to.

Next, input code data "10011111"
A series of operations of the variable-length code decoding apparatus according to the present embodiment will be described by taking the process of decoding as an example.

First, the input code data is code length calculation circuit 1
02, and is compared with each boundary code value in the boundary code storage unit 101. In the comparator 131a, the input code "1001"
The upper 2 bits "11" of 1111 "and the boundary code" 01 "of code length 2 are compared and" 1 "is output. Similarly, the comparator 131b outputs the lower 2 bits" 00 "of the upper 3 bits of the input code. And the lower 2 bits of the boundary code of code length 3 "0"
"0" is compared, and "0" is compared, and the comparator 131c compares the lower 3 bits "001" of the upper 4 bits of the input code with the lower 3 bits "100" of the boundary code of code length 4.
0'in the comparator 131d, the lower 3 bits "011" of the upper 5 bits of the input code and the boundary code 3 of the code length 5
Bit "100" is compared and "0" is detected by comparator 131e
Then, the lower 3 bits “11” of the upper 6 bits of the input code
1 "is compared with the lower 3 bits" 011 "of the boundary code having the code length 6 to be" 1 ", and the comparator 131f outputs the lower 3 bits" 111 "of the upper 7 bits of the input code and the boundary code having the code length 7 The lower 3 bits of "011" are compared and "1" is
It is output respectively. The outputs of the comparators 131a to 131f are "100011", and as a result, the code length generating circuit outputs the code length "3".

When the code length "3" is input to the address calculator 103, the input code data "10011111" is shifted in the lower direction by 5 bits in the barrel shifter 151 and "0" is added to the upper bit, and "0000010" is added.
The difference storage unit 152 outputs the boundary code / boundary address difference “−13” corresponding to the code length “3”, and outputs the difference output “−13” and the output “00” of the barrel shifter 151.
000100 ″ (= 4) is input to the subtractor 153, and the subtraction result “17” is obtained. By inputting the subtraction result “17” as the address of the decoding table 104, the decoded value “6” of the code “100” included in the head of the input code data “10011111” is obtained.

[0045]

As described above, according to the present invention, the code length is calculated from the input code data and the boundary code, and the difference value between the input code data and the boundary code corresponding to the code length is obtained. By calculating the address of the decoding table from, the capacity of the decoding table can be suppressed to the total number of codes and the encoded data can be decoded. Further, according to the present invention, it is possible to perform decoding not only on coded data coded by a specific code but also on coded data coded by an arbitrary code.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing a configuration of a variable length code decoding device according to a first exemplary embodiment of the present invention.

FIG. 3 is a diagram illustrating a variable length code handled in the embodiment.

FIG. 4 is a diagram illustrating a boundary code storage unit of the embodiment.

FIG. 5 is a diagram illustrating a decoding table of the same embodiment.

FIG. 6 is a block diagram illustrating a code length calculation circuit according to the same embodiment.

FIG. 7 is a diagram illustrating a code length generation circuit of the same embodiment.

FIG. 8 is a block diagram illustrating an address calculator of the embodiment.

FIG. 9 is a block diagram illustrating a boundary address storage unit of the embodiment.

FIG. 10 is a block diagram showing a configuration of a variable length code decoding device according to a second exemplary embodiment of the present invention.

FIG. 11 is a diagram illustrating a boundary code storage unit of the embodiment.

FIG. 12 is a diagram illustrating a decoding table according to the same embodiment.

FIG. 13 is a block diagram illustrating a code length calculation circuit according to the same embodiment.

FIG. 14 is a diagram illustrating a code length generation circuit of the same embodiment.

FIG. 15 is a block diagram illustrating an address calculator of the embodiment.

FIG. 16 is a diagram illustrating a difference storage unit of the embodiment.

FIG. 17 is a diagram illustrating a conventional variable length code.

FIG. 18 is a diagram illustrating a variable length code.

[Explanation of symbols]

 11 code data storage means 12 code length calculation means 13 difference value determination means 14 decoded data calculation means 21, 101 boundary code storage section 22, 102 code length calculation circuit 23, 103 address calculator 24, 104 decoding table

Claims (1)

[Claims] 1. A decoding device for sequentially decoding a series of code data encoded by a variable length code, wherein each of the code data having the largest value or the code data having the smallest value is set in a set of code data having the same code length. Code data storage means for storing each code length as a boundary code is compared with the input code data string and each boundary code stored in the code data storage means, and based on each comparison result, the code data to be decoded A code length calculating means for calculating a code length, and the same code length as the code length calculated by the code length calculating means among the boundary data stored in the code data to be decoded and the code data storing means. A difference value determining means for determining a difference value with the one having, and a decoded data calculating means for obtaining decoded data from the difference value determined by the difference value determining means. Variable length decoding apparatus according to claim.