JPH08288838A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE: To attain an operation of a phase locked loop circuit with evasion of the blind sectors and with addition of only a simple circuit by providing a voltage division circuit in which voltage division ratios different slightly from each other are set for two phase difference outputs and supplying the voltage division output to a differential input loop filter as the control voltage of a voltage control oscillator. CONSTITUTION: A voltage division circuit 5 performs the voltage division of both phase difference outputs Pd and Pu of a frequency phase comparator 1, and the voltage division outputs Pd' and Pu' are smoothed by the smoothing capacitors 6a and 6b and turned into the differential inputs of a differential input filter 2. A slight difference is secured between both resistances Ra and Rb and therefore a slight difference of voltage division ratios is also caused between both voltage division circuit parts. In a phase locked loop state, the coincidence is secured between the input voltage Pd' and Pu' of the filter 2 by the control of a phase feedback loop. Therefore, the operating point of the comparator 1 is substantially set at a rectilinear part with evasion of the blind zones of input/output characteristics. Thus a stable operation is secured for the comparator 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit, and more particularly to improvement of a phase locked loop oscillator such as a frequency synthesizer.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing an example of an oscillation circuit of this type of phase-locking system, in which an output of a VCO (voltage controlled oscillator) 3 is frequency-divided (fp) by a frequency dividing circuit 4 and a reference input. The frequency fr and the frequency phase comparator 1 digitally detect the frequency difference and the phase difference.

That is, if the phase of the divided signal (fp) is advanced with respect to the reference input signal (fr), the first phase difference output Pd having a pulse width corresponding to the amount of advance is generated.
On the contrary, if the phase of the divided signal is delayed with respect to the reference input signal, the second phase difference output P having a pulse width corresponding to the delay amount is output.
u is generated.

Such a digital frequency phase comparator is a well-known circuit, and for example, those disclosed in Japanese Patent Laid-Open Nos. 3-295316 and 5-206845 can be used.

These first and second phase difference outputs Pd, P
The high frequency component of u is removed through a smoothing filter composed of resistors R1 and R2 and capacitors 6a and 6b, and becomes a differential input of a differential input type loop filter 2. The output of the differential input loop filter 2 becomes the control voltage of the VCO 3, and the reference input signal (fr) is output to the output O of the VCO 3.
A signal that is phase-synchronized with is obtained.

In the phase locked oscillator circuit having such a structure, the reference input signal (fr), which is the two inputs of the frequency phase comparator 1, and the frequency divider circuit 4 when the phase lock is established.
The frequency-divided signal (fp) is completely phase-synchronized as shown in the lower side of FIG. 5, and the phase difference between the two is zero. Therefore, the two digital outputs Pd and Pu of the comparator 1 both maintain a high level (VH), and the potential difference between the DC components of these two digital outputs Pd and Pu is zero.

However, in the phase-locked state, the phase of the frequency-divided output signal (fp) with respect to the reference input signal instantaneously shifts due to various factors. Therefore, an error signal corresponding to this shift is output from the comparator 1. This error signal causes VCO3
Are controlled so that the reference input signal (fr) and the divided output signal (f
The control is performed so that the phase of (p) coincides with that of p). Therefore,
The output signal O that is always in phase with the reference input signal is VCO3.
Is generated from.

Here, the relationship of the DC component of the difference between the output signals Pd and Pu with respect to the input phase difference showing the input / output characteristic of the frequency phase comparator 1 is generally considered to be linear. However, in reality, due to factors such as the internal propagation delay of the comparator 1, it is not perfectly linear and exhibits a characteristic having a dead zone as shown in FIG. This dead zone is such that the output signal (DC voltage difference between Pd and Pu) does not change when the input signal phase difference is near zero.

[0009]

The conventional phase-locking oscillator circuit shown in FIG. 4 has a dead zone in the input / output characteristics of the frequency phase comparator as shown in FIG. When the phase of the frequency divider circuit output with respect to the reference input signal matches and the synchronization is established, a minute phase shift of the frequency division output with respect to the reference input signal cannot be detected, and control is not applied, so the output There is a drawback in that the phase noise of the signal is deteriorated.

A technique for avoiding the dead zone in the input / output characteristics of such a frequency phase comparator is disclosed in the above-mentioned Japanese Patent Laid-Open No.
Although proposed in Japanese Patent Application Laid-Open No. 295316/1993 and Japanese Patent Application Laid-Open No. 5-206845, these techniques are premised on a phase locked loop circuit provided with a charge pump circuit between a phase comparator and a filter. The techniques of the above publications cannot be applied as they are to the phase-locked oscillation circuit having the differential input loop filter 2 shown in FIG. 4 that does not have a charge pump circuit.

An object of the present invention is to provide a phase locked loop circuit which is operable by avoiding a dead zone by simply adding a simple circuit to a circuit having a differential input loop filter.

[0012]

According to the present invention, the voltage-controlled oscillation means compares the phase of this oscillation signal with the reference input signal, and when the oscillation signal is in a phase lead state with respect to the reference signal, Phase comparing means for generating a first phase difference output according to the phase lead amount and for generating a second phase difference output according to the phase delay amount in the phase delay state, and the first and second positions. First and second parts provided corresponding to the phase difference outputs and respectively dividing the corresponding phase difference outputs with different voltage division ratios.
And a filter means for generating a control voltage for the voltage controlled oscillation means by using both the divided voltage outputs of the first and second voltage dividing means as differential inputs. Is obtained.

[0013]

The voltage dividing circuit is provided for each of the two phase difference outputs of the frequency phase comparator, and the voltage dividing ratios of these voltage dividing circuits are set to be slightly different. By supplying this divided voltage output to the differential input loop filter and using it as the control voltage of the VCO, the dead zone is avoided and the frequency phase comparator is operated stably.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention, and the same parts as those in FIG. 4 are designated by the same reference numerals. In FIG. 1, a portion different from FIG. 4 will be described. The voltage dividing circuit 5 is provided corresponding to each of the two phase difference outputs Pd and Pu of the frequency phase comparator 1, and divides the corresponding phase difference outputs respectively. Are provided, and the divided outputs Pd 'and Pu' are smoothed by smoothing capacitors 6a and 6b, respectively, and become the differential inputs of the differential input loop filter 2.

The voltage dividing circuit 5 has a resistance voltage dividing circuit configuration, and a resistor R1 is inserted in series with the signal line of the phase difference output Pd.
And a resistor Ra inserted in parallel therewith. Further, it comprises a resistor R2 inserted in series and a resistor Rb inserted in parallel to the signal line of the phase difference output Pu.

The resistors R1 and R2 have the same resistance value R, and the resistors Ra and Rb are selected to have slightly different resistance values.

The other structure is the same as that of the circuit of FIG. 4, and the description thereof is omitted.

In such a configuration, R1 =
Since R2 = R and there is a slight difference between Ra and Rb, there is a slight difference in the voltage division ratio of both voltage dividing circuit portions.

Here, in the phase locked state, control is performed by the action of the phase feedback loop so that the input voltages Pd 'and Pu' of the differential input loop filter 2 match. But,
Since there is a difference between the two resistance voltage division ratios, in order to equalize the difference between the divided voltages Pd 'and Pu' as described above, there is a difference in the DC voltage between the two output signals Pd and Pu of the comparator 1. Must have happened.

FIG. 2 shows an example of the waveform of each signal in the above-mentioned phase locked state, and is an example in the case where Ra is set slightly larger than Rb. In this case, the voltage division ratio Ra / (R + Ra) between Pd and Pd 'is slightly larger than the voltage division ratio Rb / (R + Rb) between Pu and Pu', and therefore in the phase locked state, Pd 'and Pu' In order for the voltages to match, the DC component of Pd must be smaller than that of Pu.

The waveforms of Pd and Pu in FIG. 2 show exactly that state, and as a result, the phase-locked loop is locked (phase synchronization is established) with a steady phase difference φ between fr and fp. You are doing it.

This is equivalent to setting the operating point in a straight line portion avoiding the dead zone of the input / output characteristic without repairing it, and therefore, it becomes possible to operate outside the dead zone. As a result, the sensitivity to the phase change of the output signal is improved, and the phase noise characteristic is improved.

[0024]

As described above, according to the present invention, with a simple configuration in which a voltage divider circuit is simply added to the output of the phase comparator,
A circuit that operates by avoiding the dead zone of the phase comparator can be applied to the phase-locked oscillator circuit that uses the differential input loop filter, and an excellent phase noise characteristic can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a signal waveform diagram of each part showing an operation example of the circuit of the embodiment of the present invention.

FIG. 3 is a diagram showing operating points of the frequency phase comparator of the embodiment circuit of the present invention.

FIG. 4 is a diagram showing an example of a conventional phase locked loop circuit.

FIG. 5 is a signal waveform diagram of each part showing an operation example of the conventional example of FIG.

FIG. 6 is an input / output characteristic diagram of the frequency phase comparator.

[Explanation of symbols]

 1 frequency phase comparator 2 differential input filter 3 VCO 4 frequency divider circuit 5 voltage divider circuit 6a, 6b smoothing capacitor

Claims (3)

[Claims] 1. A voltage-controlled oscillating means, and a phase comparison between the oscillated signal and a reference input signal, and when the oscillated signal is in a phase lead state with respect to the reference signal, a first position corresponding to the phase lead amount. Phase comparison means for generating a phase difference output and for generating a second phase difference output according to the phase delay amount when in the phase delay state, and provided corresponding to the first and second phase difference outputs, respectively. First and second voltage dividing means for dividing the phase difference output into different voltage division ratios, respectively, and the first and second voltage dividing means.
And a filter means for generating a control voltage of the voltage controlled oscillation means by using both voltage division outputs of the voltage division means as differential inputs. 2. The filter means includes the first and second filters.
2. The phase-locked loop circuit according to claim 1, further comprising a smoothing capacitor for smoothing each divided output of the voltage dividing means, and a differential input loop filter using these smoothed outputs as differential inputs. . 3. The first voltage dividing means is inserted in parallel with a first resistor serially inserted in the signal line of the first phase difference output and a signal line of the first phase difference output. And a second resistor, the second voltage dividing means includes a third resistor serially inserted in the signal line of the second phase difference output, and the signal line of the second phase difference output. And a fourth resistor inserted in parallel with the first resistor, the first resistor and the third resistor having the same resistance value, and the second resistor and the fourth resistor having different resistance values. The phase locked loop circuit according to claim 1 or 2, wherein