JPH08288821A - Output driver with programmable driving characteristic - Google Patents

Abstract

PROBLEM TO BE SOLVED: To optimize the output driver of IC corresponding to specified conditions during a production period. SOLUTION: A driving signal to be impressed to the gate of pull-up transistor 32 at an output driver 20 is limited by an output high voltage limited to be outputted to an output buffer 21. Concerning a reference voltage regulator circuit 24 for generating this limited high output voltage, the sum of currents on a current mirror is controlled by a bias current source 26 based on the current mirror, that is programmed by a fuse or controlled during an operating cycle and the output impedance of reference voltage regulator can be selected. Through rate control to the output driver transistor is applied under the control of bias circuit for generating a reference voltage for follow as well and that reference voltage can be programmed by a fuse or a control signal. Therefore, a through rate can be selected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the technical field of integrated circuits, and more particularly to output driver circuits in integrated circuits.

[0002]

2. Description of the Related Art In the field of modern digital integrated circuits, complementary metal-oxide-semiconductor (CMO) is particularly well known.
S) In integrated circuits that are manufactured according to the technology and can be used in low-power applications such as battery-powered computers, designers find it difficult to balance the performance of the device with the power dissipation. Often faced. Such a tradeoff is especially difficult in designing output driver circuits where rapid switching of the output terminals (especially when driving a significant load) usually requires sinking and sourcing significant current. It is a thing. In addition to the problem of providing adequate current to quickly switch capacitive loads, high performance output drivers are especially concerned in the worst case when multiple output terminals switch simultaneously. In some cases, large noise may be generated mainly due to the voltage modulation from the inductive component of the data bus impedance. Therefore, optimizing the output driver circuit to provide high performance with low power dissipation and low noise is often a difficult problem for circuit designers.

Further, when the system is applied in different situations, the output drive conditions required for the integrated circuit may be different. Of course, the load presented to the integrated circuit output will vary between system applications. Furthermore, speed,
Power and noise conditions may vary from application to application. These variations in device conditions allow circuit designers to design the optimum output driver circuit for each type of system, but the constraints of the integrated circuit manufacturer's inventory and planning are , Typically requires circuit designers to optimize output driver circuits over a wide range of anticipated applications. As a result, integrated circuit performance is typically only optimized for a portion of the potential market.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks of the prior art, and provides an output driver circuit which can be optimized for a specific condition during a manufacturing period. The purpose is to Another object of the present invention is to provide an output driver circuit that can be optimized under the control of the user. Yet another object of the present invention is to provide an output driver circuit that can be optimized to match the characteristics of transistors manufactured in the integrated circuit itself. Yet another object of the present invention is to provide an output driver circuit that can be permanently optimized by programming the fuse.

[0005]

The present invention can be implemented in the form of an output driver circuit for an integrated circuit. The output driver circuit has a pull-up transistor, and its gate drive is controlled by the output buffer based on the output reference voltage. The output reference voltage is generated by a circuit based on a current source based on a current mirror,
It is possible to switch one or more parallel branches to a reference branch. Therefore, the current source output conducts the mirrored current according to the current in the reference branch.
By introducing by switching the parallel branch into the reference branch, the effective mirror ratio is changed, which mirror ratio can adjust the output reference voltage and also control the bias reference voltage. Whether the drive characteristics of the output driver are programmed at a later stage in the manufacturing process (for example by programming fuses, by bond wire connections, or by controlling these circuit functions under the control of logic signals (programming by fuses or (If wire bond option is used) or by system user (if logic signal is used)
It is possible to program.

[0006]

DETAILED DESCRIPTION OF THE INVENTION The present invention may be implemented in many types of integrated circuits that produce digital output signals. Examples of such integrated circuits are read-only, writable read-only, random access (static or dynamic), and FIFO.
Types of memory circuits, timer circuits, microprocessors, microcomputers, microcontrollers, and other logic circuits of the general or programmable type. For convenience of description, the preferred embodiment of the present invention describes an example of a memory integrated circuit, which is used to supply output data to an integrated circuit (eg, microprocessor, etc.) having a lower power supply voltage. Because it is often done.

FIG. 1 shows a block diagram of a read / write memory 10 in which the preferred embodiment of the present invention is implemented.
The memory 10 has a plurality of memory cells arranged in the form of a memory array 16. Generally, the memory 10
Operates to receive an M-bit address and output an amount of N-bit data in synchronization with a system clock (shown as "CLK"). The integers M and N are selected by the designer according to the desired memory density and data path size. The memory cell selected in the memory array 16 is accessed by the operations of the address register 12, the timing / control circuit 14, and the address decoder 17. The data terminal 28 allows communication of data to and from the read / write memory 10, while the data terminal 28 in this embodiment is a common input / output terminal, but, of course, in another embodiment, Memory 1
It is also possible to provide separate dedicated input and output terminals within 0. The data is read via a read circuit 19 (which can have a sense amplifier, a buffer circuit, etc.), an output buffer 21, an output driver 20,
Data is read from selected memory cells in the memory array 16, while data is read from the input driver 18 and the write circuit 1.
It is written to the selected memory cell in the memory array 16 via 7.

The address register 12 has an integer number M of address inputs A _{1 to} A _M. As known in the memory art, address inputs allow an M-bit address to be applied to memory 10 and stored in address register 12. In this embodiment, the memory 1
0 is of the synchronous type and, as such, the address value at address input A is clocked into address register 12 via CLK, where CLK is supplied from timing and control circuit 14 to address register 12. . When the address is stored, the address register 12 applies the address to the memory array 16 via the address decoder 17. The timing and control circuit 14 is shown as receiving a general set of control inputs (shown as "CTRL"), which are, for example, read / write enable, output enable, burst mode enable, 6 represents various control and / or timing signals known in the art such as chip enable.

In this embodiment, memory 10 receives power from power supply terminal V _CC and has a reference voltage terminal GND. According to a preferred embodiment of the present invention, the memory 10
Provides output data at data terminal 28 for reception by another integrated circuit driven by a power supply voltage lower than that applied to terminal V _CC of memory 10. For example, the power supply voltage applied to terminal V _{CC of} memory 10 may be nominally 5V (relative to the voltage at terminal GND), while the data supplied by memory 10 to terminal 28 may be The receiving integrated circuit may have a nominal 3.3V power supply voltage. To enable such a condition, the maximum voltage driven by the output driver 20 of the memory 10 at the data terminal 28 should be at this low power supply voltage to avoid damaging downstream integrated circuits. Or its vicinity (ie 3.3.
V or its vicinity). As will be described in detail below, the preferred embodiment of the present invention includes a memory 1
It puts such a limit on the maximum output high level voltage driven by the zero output driver 20.

The memory array 16 is a standard memory storage array sized and configured according to the desired density and architecture. In general, array 16 receives the decoded address signal from address decoder 17 and in response, the desired one or more memory cells are accessed. As mentioned above, one of the control signals selects whether a read or write operation is performed. In the write operation, the input data supplied to the data terminal 28 and sent via the input buffer 18 is supplied to the memory cell selected by the write circuit 23. On the contrary, in the reading operation, the data stored in the selected memory cell is supplied to the output buffer 21 by the reading circuit 19.
Therefore, the output buffer 21 generates a control signal to the output driver 20 and supplies the digital output data signal at the data terminal 28. In either case, the internal operation of the memory 10 is controlled by the timing / control circuit 14.

In accordance with the preferred embodiment of the present invention, the memory 10
Further has an output buffer bias circuit 22. The output buffer bias circuit 22 uses the line VOHR.
Generate a bias voltage on EF, which is output buffer 2
The control signal supplied to 1 and thus the output buffer 21 limits the maximum output voltage driven by the output driver 20 on the data terminal 28 and the output buffer bias circuit 22 generates a voltage on the line BIAS, It is fed to the output buffer 21 and controls the pull-down slew rate as described below. As shown in FIG. 1 and as described in more detail below, output buffer bias circuit 22 according to the preferred embodiment of the present invention.
Are controlled by the timing / control circuit 14 according to the timing of the memory access cycle.

Next, referring to FIG. 2, the structure of the output buffer bias circuit 22 according to the preferred embodiment of the present invention and the operational relationship between the output buffer bias circuit 22 and the output buffer 21 and the output driver 20 will be described in detail. As shown in FIG. 2, the output buffer bias circuit 22 has a reference voltage and regulator 24, which produces a regulated voltage VOHREF at its output. Output buffer bias circuit 2
2 further comprises a bias current source 26, which is preferably provided in the timing and control circuit 14 of FIG. 1 in this embodiment of the invention, as described in detail below. Bus C from fuse or control circuit 25
Controlled by the control signal above. As described in detail below, the control signal on bus C can be generated according to the state of a programmable fuse, or as a control signal from a configuration register or to an external signal. It is also possible to generate it based on.

Bias current source 26 is line VOHREF
Generates a bias current i _BIAS that is used by a reference voltage and regulator 24 that produces a voltage above. According to this embodiment of the invention, the bias i _BIAS is based on the control signal on bus C and the bias circuit 120 on line BIAS.
Is controlled in response to a bias reference voltage generated by. Furthermore, according to this embodiment of the invention, the reference voltage
The regulator 24 receives the offset compensation current i _NULL from the offset compensation current source 28. The output buffer bias circuit 22 further includes a V _t shift circuit 30,
It acts to set the voltage VOHREF. The detailed structure and operation of the output buffer bias circuit 22 and the respective blocks forming the same will be described in more detail below. The voltage VOHREF is supplied to each of the output buffers 21. Therefore, the output buffer bias circuit 22 serves a plurality of output buffers 21. However, in many cases, depending on the number of the output buffers 21, a single output buffer bias circuit 22 controls all the output buffers 21. The output buffer bias circuit 22 of 1 may be sufficient. Each output buffer 21 receives complementary data inputs DATA, DATA * generated by the read circuit 19 (see FIG. 1). For example, output buffer 21 _j receives complementary data inputs DATA _j , DATA _j * (where “*” represents a logical complement). Each output buffer 21 supplies control signals (shown as PU and PD to the output buffer 21 _j ) to the corresponding output driver 20. Each output driver 20 drives a corresponding data terminal 28.
On the other hand, as shown in FIG. 1, since the data terminals are common input / output terminals, the input side (that is, the data input buffer etc.) is not shown in FIG. 2 in order to simplify the drawing.

Each output buffer 21 in this embodiment of the invention is configured as an N-channel push-pull driver. In particular, referring to the output driver 20 _j shown in detail in FIG. 2 (it should be understood that the other output drivers 20 are similarly configured), the N-channel pull-up transistor 32 is The drain is biased to V _CC and its source is connected to the data terminal 28 _j , and the N-channel pull-down transistor 34 has its drain connected to the data terminal 28 _j and its source is biased to ground. are doing. The output driver 20 further preferably includes an electrostatic protection device (not shown) known in the art. The gates of the transistors 32 and 34 receive the control signals PU and PD from the output buffer 21, respectively. As it will be appreciated by those skilled in the art, (a nominally, for example, 5V) V _CC so biases the drain of pull-up transistor 32, the voltage on line PU applied to the gate of transistor 32, a logic 1 (V _The maximum voltage at which transistor 32 drives data terminal 28 _j is limited (eg, 3.3 V).
Must be properly controlled to ensure that no more than The manner in which such limitations are made in accordance with the preferred embodiment of the present invention is described in detail below.

As shown in FIG. 2, the substrate node of N-channel pullup transistor 32 is preferably biased to ground rather than its source at data terminal 28 _j . As will be apparent to those skilled in the art, this substrate node bias for N-channel pull-up transistor 32 is suitable to avoid effects on latch-up. However, the bias condition for this transistor 32 effectively increases its threshold voltage, making it more difficult to limit the V _OH maximum driven by the output driver 20. This difficulty is due to the higher voltage that must drive line PU to turn on transistor 32. As explained below,
The preferred embodiment of the present invention addresses this difficulty in a manner that allows the substrate node of transistor 32 to be back biased (ie, biased to a voltage other than its source).

[0016] While a detailed description of the construction of output buffer 21 _j as shown in the output buffer Figure 2, it should be understood that other output buffer 21 has a similar configuration. The output buffer 21 _j receives the data input lines DATA _j and DATA _j * at the input ends of the NAND function units 40 and 42, respectively. The output enable line OUTEN is received at the input of each of the NAND functional units 40, 42 and performs the output enable function as described below.

An output enable function is performed, as described below.

The output of the NAND function section is applied to the gates of the P-channel transistor 36 and the N-channel transistor 38. The P-channel transistor 36 is
Its source is biased to the voltage VOHREF generated by the output buffer bias circuit 22 and its drain is connected to line PU. N-channel transistor 38 has its drain connected to line PU and its source biased to ground. Thus, transistors 36 and 38 form a conventional CMOS inverter for driving line PU with the logical complement of the logical signal provided by NAND function 40. However, the high voltage on line PU driven by transistor 36 causes the output buffer bias circuit 22 to
Is limited to the voltage VOHREF generated by. Since line PU is connected to the gate of N-channel pull-up transistor 32 in output driver 20 _j ,
The voltage VOHREF controls the maximum drive of the pull-up transistor 32 and thus the voltage at which the data terminal 28 _j is driven.

On the low side, the output of NAND function 42 is applied to the input of inverting buffer 43 (biased by V _CC in this embodiment). The output of inverting buffer 43 drives line PD, which is applied to the gate of N-channel pull-down transistor 34. Further details are given below and in 1994 1
Inversion buffer 43 further includes line BIA, as described in US patent application Ser. No. 08 / 357,664, filed February 16, assigned to the applicant.
It controls the slew rate of its associated output driver 20 by receiving the reference voltage from the bias circuit 120 on S and controlling the drive applied to the gate of the pull-down transistor 34 primarily on line PD.

In operation, when the output enable line OUTEN is at a logic high level, the states of the NAND function parts 40 and 42 are the same as the data input lines DATA _j and DATA.
Controlled by the state of _j *, they are logical complements of each other (because of the data input lines DATA _j , DA
Because TA _j * are logical complements of each other). Therefore, a logic high level on line DATA _j goes to a logic low level at the output of NAND function 40, turning on transistor 36, so that voltage VOHREF is applied to the gate of transistor 32 via line PU and data terminal 28. _j is a logic high level (as described above, V
Limited by the voltage on OHREF). Under this condition, the output of the NAND function unit 42 is in the high state (the data line DATA _j * is in the low state), which is inverted by the inversion buffer 43 and then output by the output driver 2
Turn off transistor 34 at 0 _j . In the other data state, the output of NAND function 40 is high (data line DATA _j is low), turning on transistor 38 to bring line PU low and transistor 32 off. The output of NAND function 42 is low, causing inverting buffer 43 to drive line PD high and turn on transistor 34, causing data terminal 28 _j to go low. The drive applied to line PU by inverting buffer 43 is controlled by the voltage on line BIAS, and thus controls the slew rate of output driver 20 _j . When the output enable line OUTEN is at a low logic level, the outputs of the NAND functional units 40 and 42 are the data input lines DATA _j and D.
Forced high regardless of the data state applied by ATA _j *, resulting in transistors 32,3
Both 4 are turned off, keeping the data terminal 28 _j in a high impedance state.

As mentioned above, the voltage on line VOHREF in this embodiment of the invention determines the drive applied to N-channel pull-up transistor 32 in output driver 20. Therefore, according to this embodiment of the invention, VOHRE is applied to the gate of pull-up transistor 32.
The configuration of the output buffer 21 for supplying F is
It is useful. Because it is composed of a minimum number of transistors and can switch quickly to make fast transitions at the data terminal 28. Further, according to this embodiment of the invention, output driver 2 is provided to limit _VOH maximum.
No serial devices are required within 0. Such a serial device necessarily reduces the switching speed of the output driver 20 and makes it susceptible to electrostatic discharge and latch-up. Furthermore, according to this embodiment of the invention, no gate driven bootstrap to N-channel transistor 32 is required, thus avoiding the effects on voltage slews and bumps.

A suitable voltage VOHREF is provided so that the memory 10 in this embodiment of the invention is capable of driving a logic high level to a safe maximum level for receipt by an integrated circuit having a lower power supply voltage. 2 shows the configuration of the output buffer bias circuit 22 described above.
A detailed description will be given in connection with each circuit function part of the output buffer bias circuit 22 shown in FIG. In addition, a line BIAS is provided to control the slew rate of the output driver 20 when switching the output from a logic high level to a logic low level.
The function of the output buffer bias path 22 when generating a voltage above will also be described.

Reference Voltage Regulator with V _t Shift Referring now to FIG. 3, the configuration and operation of reference voltage regulator 24 will be described in detail in relation to the other components of output buffer bias circuit 22. Explained.

As shown in FIG. 3, the reference voltage / regulator 24
Is configured in the form of a current mirror. P-channel transistors 44 and 46 each have their sources biased to V _CC and their gates connected together. In the reference branch of this current mirror, the drain of transistor 44 is connected to its gate and also to the drain of N-channel transistor 48. The gate of the N-channel transistor 48 has a resistor 47 connected in series between V _CC and ground,
Connected to a voltage divider composed of 49, the gate of transistor 48 is connected to the point between resistors 47 and 49, and the desired percentage of the V _CC supply voltage (eg,
60%). On the other hand, each branch of this resistive voltage divider can be made up of a series of resistors that are initially short-circuited by a fuse, in which case the selected fuse is opened to cause the transistor to open. It is possible to program the voltage applied to the gate of 48.

The source of transistor 48 is connected to bias current source 26. In the mirror branch of this current mirror, the drain of the transistor 46 is connected to the N-channel transistor 5 at the output node VOHREF.
Connected to the drain of 0. The gate of the transistor 50 is in a manner to be described in more detail below, are coupled to node VOHREF via V _t shift circuit 30. N
The source of the channel transistor 50 is connected to the source of the transistor 48 in this reference branch and thus to the bias current source 26. As described above, the bias current source 2
6 conducts the current i _BIAS , which is the reference voltage and regulator 2
4 is the sum of the currents in the reference and mirror branches of the current mirror of 4 (ie, the sum of the currents flowing through transistors 48 and 50). The current i _BIAS is generated primarily by N-channel transistor 52, whose drain is connected to the sources of transistors 48 and 50, whose source is biased to ground, and whose gate is bias reference circuit. Controlled by 54. As will be described in more detail below, according to the preferred embodiment of the present invention, a dynamic bias circuit 60 is also provided to control the current i _BIAS , which current is reduced at some time during the memory access cycle. It is possible (under control of the control bus C) to optimize the output impedance of the reference voltage / regulator 24 for different parts of the memory access cycle.

The V _t shift circuit 30, in this embodiment of the invention, biases the gate of the N-channel transistor 50 in the mirror branch of the reference voltage and regulator 24 so that the voltage VOHREF is N in the output driver 21.
Considering that it is applied to the gate of the channel pull-up transistor 32 (via the output buffer 21), it ensures that the voltage VOHREF is shifted upwards by the N-channel threshold voltage.
The manner in which this shift is performed will be described later with reference to the operation of the reference voltage / regulator 24.

The operation of the reference voltage / regulator 24 will be described in detail at a certain time in a memory cycle during which the output data should be supplied to the data terminal 28. The bias reference circuit 54 supplies a bias voltage to the gate of the N-channel transistor 52, sets the value of i _BIAS which is conducted through the current mirror, and the dynamic bias circuit 60 is effectively turned off in this case. N
The divided voltage generated by resistors 47 and 49, which is provided as a reference voltage to the gate of channel transistor 48, determines the range to which transistor 48 should conduct and thus bias the drain of P-channel transistor 44. Determine the conditions. The current conducted by transistor 44 is mirrored by transistor 46 in the mirror branch and is therefore a multiple of the current conducted by transistor 44 (which will be described below).

The voltage VOHREF at the drains of transistors 46 and 50 is determined by the voltage at the drains of transistors 44 and 48, by the relative dimensions of the transistors in the circuit, and by the effect of V _t shift circuit 30. As is well known in the art of current mirror circuits, the gate voltage of transistor 50 is such that the voltage on line VOHREF is taken into account when the differential amplifier effect of reference voltage regulator 24 is taken into account.
Feedback to the gate of 0 tends to match the voltage at the gate of transistor 48. However, the V _t shift circuit 30 has its gate VOHR.
Having a transistor 56 connected to its drain at EF and its source to the gate of transistor 50 and connected in a diode fashion;
Therefore, there is a threshold voltage drop between line VOHREF and the gate of transistor 50. The transistor 56 is an N in the output driver 20.
It is configured similarly to one of the channel pull-up transistors 32, and in particular has the same or similar gate length and the same substrate node bias (eg ground). N-channel transistor 58
Has its drain connected to the source of transistor 56, and its gate is controlled by bias reference circuit 54 to ensure proper current conduction through transistor 56, thus ensuring an accurate threshold voltage drop. Exists across transistor 56.

As a result of V _t shift circuit 30, the voltage on line VOHREF is from the reference voltage at the gate of transistor 48 by a threshold voltage value that closely matches the threshold voltage of N-channel pull-up transistor 32 of output driver 20. Boosted or increased. This additional threshold voltage shift is necessary considering that the voltage VOHREF is applied to the gate of the N-channel pull-up transistor 32 in the output driver 20, thus ensuring proper high level drive. The V _t shift is the output impedance of the reference voltage / regulator 24, especially the voltage V generated by the switching of the output buffer 21.
It is implemented by circuit 30 in a manner that does not increase the impedance to sink current through transistor 50 in the presence of variations in OHREF. The circuit 30 further includes a reference voltage / voltage regulator 2
Introducing a minimum offset voltage in 4 and adding only two additional transistors 5 without adding an entire stage.
Only 6,58 are needed.

The voltage generated on line VOHREF by reference voltage regulator 24 is output driver in a manner different from that described above with respect to the preferred method for controlling the source voltage of pull-up transistor 36 in output buffer 21. Of course, it can be applied to control the logic high level drive of 20. For example,
The voltage generated on line VOHREF can be applied directly to the gate of a transistor in series with the pull-up transistor in output driver 20, or, in another embodiment, line VOHR.
It is also possible to apply the voltage generated on EF to the gate of a transistor in series with the pull-up transistor in the output buffer 21, in these alternative embodiments the reference voltage on line VOEHREF is output. Limit the drive applied to the terminals. However, in such an alternative embodiment, it will be apparent to those skilled in the art that the absolute value level of the reference voltage on line VOHREF may need to be shifted from that used in the previous case. is there.

Offset Compensating Current Source Reference voltage / regulation so that it is possible to supply or sink substantial current to line VOHREF without significantly modulating the voltage on line VOHREF. Desirably, the device 24 has a very low output impedance. As mentioned above, the voltage on line VOHREF provides a maximum output drive while not damaging the integrated circuit receiving the output logic signal at data terminal 28.
Since the voltage on OHREF controls the maximum maximum output high level voltage V _OH, stable near level voltage on line VOHREF it is adjusted that circle etc. stop is important.

Therefore, in the reference voltage / regulator 24, it is desirable that the driving capability, and thus the transistor size of the transistors 46 and 50 (that is, the ratio of the channel width to the channel length, that is, W / L) is extremely large. . The large size for this transistor 46, 50 is that the reference voltage regulator 24 is able to supply current quickly (via transistor 46 from V _CC to line VOHRE).
F) or sinking current (through lines 50, 52 to line VOHREF to ground). For example, the W / L of the transistor 46 is 12
Can be on the order of 00 and the transistor 50
Can be set to about 600, and in the present embodiment, the W / L of the transistor 48 is 30.
It can be about 0. Further, it is desirable that the W / L of transistor 46 be greater than the W / L of transistor 44 so that a reasonable mirror ratio can be obtained in that case, thus line VO
The supply current available on HREF is increased. Furthermore, it is desirable that the W / L of the transistor 48 be significantly larger than the W / L of the transistor 44 for high gain. In the above embodiment, the W / L of the transistor 44 can be on the order of 60, in which case the mirror ratio of the reference voltage / regulator 24 is on the order of 20. The maximum current i _sourcemax is determined by the following equation.

I _sourcemax = i _BIAS {(W / L) ₄₆ / (W / L) ₄₄ } In the above example, the maximum supply current i _sourcemax is i _BIAS
About 20 times. The maximum sink current of the reference voltage regulator 24 is equal to i _BIAS , which is controlled by the bias current source 26. In this embodiment of the invention, as will be understood, of course, the supply current controls the turn-on of pull-up transistor 32 in output driver 21, and thus is a more important parameter for this embodiment of the invention. .

However, since the currents through the reference and mirror branches of the reference voltage / regulator 24 are not equal to each other, at the drains of the transistors 44, 48 on the one hand and the drains of the transistors 46, 50 on the other hand. Offset voltage may occur between nodes. This offset voltage is 300 to 40
It may be about 0 mV and increases as i _BIAS increases.

Furthermore, the W / L of transistor 48 is significantly greater than that of transistor 44 and because transistor 44 is connected in a diode configuration (ie the gate is connected to the drain). Transistor 44 is unable to quickly pull the voltage at the drain of transistor 48 (and the gates of transistors 44 and 46) high if needed. For example, if more than one of the output drivers 21 simultaneously switch on their respective pull-up transistors 32, in order to maintain the voltage on line VOHREF at an appropriate level, a reference voltage It requires a considerable supply current from the regulator 24. This supply current tends to pull down the voltage on line VOHREF first, which is the reference voltage regulator 24.
Will tend to pull down the voltage at the drains of transistors 44, 48 in the reference branch of. Because substantially all of the current conducted by transistor 46 is directed to line VOHREF, transistor 48 needs to temporarily supply most of the current i _BULK required by current source 26. Because it is done. However, because of its relatively small size (for high Miller ratios), transistor 44 is unable by itself to quickly pull up the voltage at its drain. If this voltage remains low, the voltage VOHREF will overshoot its steady-state voltage when the transient demand for the supply current is removed. This is because transistors 44 and 46 are strongly turned on by the low voltage on their gates. As mentioned above, the overshoot of voltage VOHREF can damage downstream integrated circuits that have lower power supply voltages.

Therefore, according to the preferred embodiment of the present invention, the offset compensating current source 28 includes transistors 44 and 48.
Current i _NULL at the drain of the reference voltage / regulator 24
It is provided to supply inside. Therefore, the size of the bias current source transistor 52 must be adequate to conduct the additional current i _NULL supplied to the reference branch of the reference voltage and regulator 24 across the current mirror. Of course, additional transistors can be provided in parallel with transistor 52 to conduct this additional current. The current i _NULL is to make the current conducted by the transistor 48 per unit channel width equal to the current conducted by the transistor 50 per unit channel width, and therefore the offset voltage is not generated. Absent and reduces the load on transistor 48 on transistor 44, and the voltages at the drains of transistors 44 and 48, and thus the gates of transistors 44 and 46, are quickly pulled high when needed. Is possible. Therefore, the voltage on the line VOHREF is prevented from overshooting.

Next, the configuration of the offset compensating current source 28 will be described in detail with reference to FIG. In this particular embodiment of the invention, the offset compensating current source 2
8 is controlled by the bias reference circuit 54 in the bias current source 26 to minimize the number of transistors required. Of course, the offset compensating current source can have its own bias reference network if desired.

Bias reference circuit 54 includes a P-channel transistor 62 whose source is biased to V _CC and whose gate is biased by a reference voltage BIAS generated by bias circuit 120 described below. It N-channel transistor 64 is connected in a diode configuration, the gate and drain of which are connected to the drain of transistor 64. The dimensions of transistors 62 and 64 are selected to ensure that P-channel transistor 62 remains saturated for the specified voltage BIAS. For example, when the voltage BIAS is about 2V, the W / L ratio is about 15V.
The transistors 62 and 64 are
Is saturated and V _CC is nominally 5V
Is. The common node at the drains of transistors 62 and 64 provides a reference voltage ISVR, which is applied to the gate of transistor 52 in bias current source 26 and to offset compensating current source 28.

The operation of the bias reference circuit 54 is as stable as possible because the current conducted in the reference voltage / regulator 24 is large and the expected variations in temperature in the processing parameters and the power supply voltage are also large. It is desirable to be one. The configuration of the bias reference circuit 54 shown in FIG. 4 provides such stability, and in particular the bias circuit 120 follows variations in the V _CC supply voltage and variations in processing parameters as described below. This is especially true when it is configured to do so. In this example, as the simulation results show, a bias reference circuit 54 is used to set the gate voltage at node ISVR with respect to variations in temperature, processing parameters and power supply voltage, and by transistor 52 in bias current source 26. The ratio of maximum current to minimum current conducted is about 1.17.

The offset compensating current source 28 according to this embodiment of the invention is realized by a current mirror circuit, in which case the reference branch comprises a P-channel transistor 66 and an N-channel transistor 68. The sources of the transistors 66 and 68 are V
Biased to _CC and ground, and their drains are commonly connected. The gate of the N-channel transistor 68 is connected to the node ISV from the bias reference circuit 54.
At R, the reference voltage is received and the gate of P-channel transistor 66 is connected to the common drain node of transistors 66 and 68 and, in a typical current mirror configuration, to the gate of P-channel transistor 69 in the mirror branch. There is. The transistor 69 is
It is biasing its source to V _CC , so its drain current gives a current i _NULL . Transistor 66,
The relative size of 69, of course, determines the mirror ratio, and thus the current i _NULL, and the mirror ratio on the order of 5 is 2.5 m.
This is typical for generating a current i _NULL of the order of A. As mentioned above, sufficient current capability must be provided to transistor 52 to conduct this additional current i _NULL , preferably an N-channel transistor is provided in parallel with transistor 52. ,
Its gate is controlled by line ISVR and has dimensions that match the dimensions of the mirror circuit of transistors 66, 68, 69 to conduct additional current i _NULL in a matched manner.

Next, the effect of the offset compensating current source 28 on the operation of the reference voltage / regulator 24 will be described with reference to FIGS. FIG. 5 shows the operation of the reference voltage / regulator 24 when the current i _NULL is zero, that is, when the offset compensating current source 28 does not exist. Figure 5
Is the voltage VOH at the output terminal of the reference voltage / regulator 24.
REF, the voltage V _{44 at} the common drain node of transistors 44 and 48, and the output voltage DQ at one of the data terminals 28 are shown. Time t ₀ represents the steady state condition of all data terminals 28 when driving low output voltages. For example, in steady state, the voltage VOHREF is preferably 3.3.
V (low power supply voltage of integrated circuit that receives output data from memory 10) + N-channel threshold voltage (pull-up transistor 3 in output driver 20)
2 is an N-channel device). At time t ₁ , the data terminals 28 begin switching to the new data state, and in this embodiment, the worst condition is that all (eg, 18) data terminals 28 are at a low to high logic level. When switching to. As shown in FIG. 5, when this switching begins, as indicated by the voltage DQ starting to rise, the voltages VOHREF and V ₄₄ fall. Because a significant supply current is required by the output buffer 21 on line VOHREF, which reduces the voltage. At this time, the voltage V ₄₄ also drops. Because the current through transistor 50 is near zero (all of the current in the mirror branch is needed by output buffer 21), it forces transistor 48 to conduct virtually all of the current i _BIAS. This is because I will let you. The additional conduction by this transistor 48 is
The voltage at node V ₄₄ is dropped. Time t ₂ represents the end of the output transient, where the demand for supply current begins to decrease, allowing the voltage on line VOHREF to rise due to the operation of reference voltage regulator 24. However, as noted above, due to the diode configuration of transistor 44, which is small in size and requires that the mirror ratio be large enough to provide the supply current needed by output buffer 21, node V ₄₄ The voltage at will remain low for a significant amount of time and will not begin to rise until time t ₃ . As long as the voltage at node V ₄₄ remains below its steady state value, that is, the value that keeps transistors 44 and 46 turned on strongly, line VO
The voltage at HREF is allowed to rise and rises past its steady state value by a significant margin (V _OS ). This rise in VOHREF above the desired value is reflected in the data terminal 28 via the output buffer 21 and the output driver 20, causing damage to the low power supply integrated circuit connected to the data terminal 28. It may be reflected to the extent that it causes it.

Referring now to FIG. 6, a current i based on a simulation under the same conditions as shown in FIG. 5 and having the same time axis as in FIG.
The operation of the reference voltage / regulator 24 is shown for a _NULL of 2.5 mA. As mentioned above, the switching occurring at time t ₁ is caused by the voltages VOHREF and VOHREF.
Drop ₄₄ . However, the transistors 44, 4
Additional current i applied to the common drain node of 6
_The time t _{3 at} which the _NULL helps charge this node so that the voltage V ₄₄ starts to rise is the first switching time t _1.
Occurs earlier than after. In this case, the voltage V ₄₄ starts rising rapidly, so that the voltage VOHREF is i _NULL =
It is not allowed to overshoot its steady state value for as long as in the case of FIG. 5, which is zero.

Programmable Compensation Bias Circuit As described above, the current i _BIAS generated by the bias current source 26 is _equal to the bias circuit, as is the output slew rate controlled by the inverting buffer 43 in the output buffer 21. Depends on the voltage on line BIAS generated by 120. Furthermore, as will be apparent from the following description, other functions such as the reference voltage and the output impedance of the regulator 24 are also provided in the line BIA.
Controlled according to the voltage on S. Next, the configuration and operation of the bias circuit 120 according to the preferred embodiment of the present invention will be described in detail with reference to FIG.

The bias circuit 120 is a current mirror bias circuit, and the reference branch of the current mirror is controlled by a voltage divider. As will be apparent from the description below, bias circuit 120 provides a bias voltage on line BIAS, which varies in a manner consistent with variations in the value of supply voltage V _CC and certain manufacturing process parameters.

Bias circuit 120 provides the voltage on line BIAS to the gate of P-channel transistor 62 in bias reference circuit 54, as previously described with reference to FIG. In the present embodiment, it is desirable for the gate-to-source voltage of P-channel transistor 62 to remain substantially constant with variations in the V _CC supply voltage, and thus the current therethrough. Is desirable. In other words, it is desirable for the voltage on line BIAS to follow the variations in V _CC . Thus, the current through transistor 62 of bias reference circuit 54 remains substantially constant with such variations.

In this embodiment of the invention, bias circuit 120 comprises a voltage divider having resistors 121, 123 connected in series between the V _CC power supply and ground. As shown in FIG. 11, additional resistors 125 and 127 are also present in the voltage divider, and fuses 124 and 126 are connected in parallel therewith. The output of the resistor divider at the node between resistors 121 and 123 is fed to the gate of N-channel transistor 128, which of course is shorted by fuses 124 and 126 to which resistors 125 and 127 are untouched, respectively. If not, the sum of the resistance values of the resistors 123 and 127 and all the resistors 1
The ratio of the V _CC power supply voltage determined by the ratio to the sum of 21,123,125,127.

According to this embodiment of the invention, the resistor 12
1, 123, 125, 127 are preferably configured as polysilicon resistors and have different resistance values. For example, resistors 125a, 125b, 125c
Can have a value corresponding to an index of 2 with respect to each other (for example, the resistor 125a has a resistance value twice the resistance value of the resistor 125b, and the resistor 125b has a resistance value of 125).
It has a resistance value twice that of c), and the resistance value of the resistor 121 can be somewhat larger than that of the resistor 125a. The relationship between such resistance values is the fuse 12
By leaving selected one of 4, 126 open, it is possible to give a high degree of freedom when tuning a desired ratio of the V _CC power supply voltage.
Due to the programmable capability of the fuse, ie the writable nature, the integrated circuit implementing the bias circuit 120 allows the voltage applied to the gate of the transistor 128 to be adjusted to the desired level.

On the other hand, instead of the fuses 124 and 126, a shorting transistor whose gate is controlled by a control signal from the bus C can be provided across each of the resistors 125 and 127. Therefore, the use of a shorting transistor allows the programmable capability for a desired percentage of the V _CC power supply voltage to be applied to transistor 128 to be provided in a non-permanent fashion,
For example, it allows the circuit to be programmed under the control of the user of the integrated circuit either before or after it is incorporated into the system.

As mentioned above, the gate of transistor 128 receives the output of the voltage divider comprised of resistors 121, 123, 125, 127. The source of transistor 128 is biased to ground and transistor 12
The drain of 8 is connected to the drain and gate of P-channel transistor 130, and the source of P-channel transistor 130 is connected to V _CC . The combination of the transistors 128, 130 constitutes the reference branch of the current mirror, through which the current conducted through the resistor 12
It is substantially controlled by the voltage output of a resistive voltage divider composed of 1,123,125,127. Therefore, the voltage applied to the gate of transistor 128, and thus transistors 128, 13 in the reference branch of the current mirror.
0 current conducted by varies according variations in voltage of V _CC power source, substantially the same rate of the voltage of V _CC power supply is maintained.

The output branch of the bias circuit 120 is a P-channel mirror transistor 132 and a linear load device 134.
Is included. The P-channel transistor 132 is
Its source is connected to V _CC , and its gate is connected to the gate and drain of transistor 130 in a current mirror mode. The drain of transistor 132 is connected to linear load device 134 and drives line BIAS. The load device 134 can be implemented as an N-channel transistor 134 with its source connected to ground and its gate connected to V _CC , in which case the common drain node of the transistors 132, 134 is biased on line BIAS. Drive the voltage output. On the other hand, the linear load device 134 can also be realized as a precision resistor or as a two-terminal diode.

In any case, the linear load device 134 is important in providing compensation for variations in processing parameters such as channel length. Transistor 1
Fluctuations in the channel length of 30, 132 cause fluctuations in the current conducted by transistor 132, and therefore due to the linear characteristics of load device 134,
It produces a corresponding fluctuation in the voltage on the line BIAS. Therefore, the bias circuit 120 provides an output voltage on line BIAS that tracks variations in processing parameters that affect the conduction of current by transistors in the integrated circuit.

As noted above, the current conducted by transistor 132 is controlled to match or be a specific multiple of the current conducted through transistor 130. Because the current conducted through transistor 128, 130 is controlled in accordance with the divided voltage of V _CC supply, the current conducted by transistor 132 (accordingly, the voltage on line BIAS) is controlled by the V _CC supply It Therefore, the voltage on line BIAS also follows the modulation in the V _CC supply voltage by modulating the voltage drop across linear load 134.

Certain dimensional relationships between the transistors in bias circuit 120 are believed to be extremely important in ensuring proper compensation. First, the transistor 128
Is preferably, but not close to, the minimum channel length and channel width for the manufacturing process used. Transistor 12 having a channel length close to the processing minimum allows transistor 12
The current conducted by 8 varies with variations in channel length for the highest performance transistors in the integrated circuit, and the use of longer channel lengths reduces the sensitivity of transistor 128 to such variations. However, the channel length of transistor 128 should be slightly larger than the processing minimum to avoid hot electron effects and short channel effects. Transistor 128 also preferably has a channel width that is relatively small, but not equal to the minimum value, to minimize the current conducted therethrough, and in particular, bias circuit 120 causes transistors 128, 130 to be the same. The current is minimized in consideration of the fact that the DC current is always conducted through (and the mirror branch transistor 132 and the linear load 134). An example of a size of transistor 128 based on recent manufacturing processes is a channel length of 0.8 μm and a channel width of 4.0 μm, where the process minimums are 0.6 μm and 1. It is 0 μm.

P-channel transistors 130 and 132
Must also be properly sized to properly bias the transistor 128 and the linear load device 134 (if configured as a transistor). Line B
To properly compensate for the bias voltage on IAS, transistor 128 is preferably biased in the saturation (square law) region, while transistor 134 is biased in the linear (ie, triode) region. This allows transistor 134 to operate as an effectively linear resistive load, while transistor 128 remains saturated. As is apparent from the configuration of bias circuit 120 in FIG. 2, such bias depends on the relative dimensions of transistors 128 and 130 and the relative dimensions of transistors 132 and 134.

Transistor 13 is such that the voltage at the gate of transistor 128 is as close to V _CC as possible while keeping transistor 128 in saturation.
It is desirable that 0 is as large as possible. Because the variation in V _CC is due to the resistances 121, 123, 12
Since it is applied to the gate of transistor 128 at a ratio defined by the voltage divider composed of 5,127, so that this ratio is as close to 1 as possible,
Further, it is desirable to maintain the transistor 128 in a saturated state. The large W / L ratio for transistor 130 allows its drain-to-source voltage to be relatively small, and thus transistor 1
The drain voltage of 28 is pulled higher, which allows the voltage at the gate of transistor 128 to be higher and still keep transistor 128 in saturation. Therefore, the bias circuit 120
Tracking capability is improved by transistor 130 being extremely large.

In the embodiment described above, the V _CC power supply voltage is nominally 5.0 V, and the table below shows that the transistors 128, 130 in the configuration of FIG. 11 for each channel length of 0.8 μm. , 132, 134 for the preferred channel width (microns).

Table Transistor Channel Width (μm) 128 4.0 130 32.0 132 76.0 134 4.0 As observed by simulation, this example bias circuit 120 shows a relatively wide range of V _This is effective in maintaining good tracking of the voltage on the line BIAS across the _CC power supply.

Dynamic Control of Bias Current As is apparent from the above description, the reference voltage / regulator 2
It is desirable that the output impedance of No. 4 is as low as possible during the period when the output buffer 21 and the output driver 20 switch the state of the data terminal 28. This low output impedance is due to the voltage V
The reference voltage and regulator 24 makes it possible to supply significant supply and sink currents without producing significant modulation at OHREF. However, such low output impedance requires that the DC current through the reference and regulator 24 be significant, thus producing significant steady state power dissipation and correspondingly increasing temperature. And it reduces reliability and load on the system power supply, all of which is undesirable.

Next, the configuration and operation of the dynamic bias circuit 60 when controlling the bias current i _BIAS in the memory access cycle will be described in detail with reference to FIG. Dynamic bias circuit 60
Are provided as an optional feature in the reference voltage regulator 24 to reduce the steady state current.
As shown in FIG. 7, the dynamic bias circuit 60 may be one of the lines of the control bus C generated by the timing and control circuit 14 from the clock signal C50 (which is generated by the fuse and control circuit 25). ) And apply it to the gate of N-channel transistor 72 via inverter 71. Transistor 72 has its drain connected to node ISVR, which is the output of bias reference circuit 54 and the gate of current source transistor 52. The source of the transistor 72 is connected to the drain of the N-channel transistor 74, and the gate of the transistor 74 is the node ISV.
It is connected to R and its source is biased to ground.

To explain the operation, the clock signal C
As long as 50 remains high, transistor 72 will be off and dynamic bias circuit 60 will not affect the gate bias of transistor 52 and will affect the value of current i _BIAS which is then conducted. There is no. When clock signal C50 is low, transistor 72 is turned on and the voltage at the gate of transistor 52 reduces the current at which transistors 72 and 74 pull node ISVR toward ground and are then conducted. So it will be reduced.

The range in which the gate bias of the transistor 52 is reduced by the dynamic bias circuit 60 is
It is determined by the size of transistor 74 in bias reference circuit 54 and the size of transistor 74 with respect to the size of transistor 52. This is obvious to those skilled in the art. This sizing depends on the gate-to-source voltage of transistor 74 being bias reference circuit 5
It can be easily determined considering that it is the same as the gate-to-bias voltage of the transistor 64 in FIG. However, the drain-to-source voltage of transistor 74 is typically very small, eg, the magnitude of the drain-to-source voltage of transistor 72 when turned on, which is on the order of 100 mV, for example.
It is less than the drain-to-source voltage of transistor 64. When both transistors 64 and 74 are in saturation, their drain currents are not significantly affected by their drain-to-source voltages, and so transistors 64 and 74 are equivalent to transistor 72.
Can be considered to be in parallel with each other when they are turned on. Since the current in transistor 52 mirrors the current in transistor 64 (which is in parallel with transistor 74 when transistor 72 turns on), clock signal C50 controls current i _BIAS , which effectively feeds transistor 52. The current mirror ratio of the transistor 64 is changed.

For example, if the current i _BIAS is to be reduced to 50% of its full value except during output switching, the channel width and channel length of transistors 64 and 74 will be the same as transistors 64 and 52. Are the same if the channel width and the channel length are the same as in this embodiment. When transistor 72 is turned off, current i _BIAS is applied to bias reference circuit 54.
Is equal to the current i ₆₄ through the transistor 64 at. When transistor 72 is turned on (clock signal C50 is low), transistors 64 and 74 are effectively in parallel with each other, as described above, and in this embodiment, the effective channel width of transistor 52. It has twice the channel width. Therefore, the current mirror ratio is 1/2.

W ₅₂ / (W ₆₄ + W ₇₄ ) = 1/2 Note that W ₅₂ , W ₆₄ and W ₇₄ are transistors ₅₂ , ₆₄ and _74, respectively.
Channel width (assuming the channel lengths are the same). The sum of W ₆₄ + W ₇₄ is the effective channel width of transistors 64 and 74 connected in parallel with each other. Therefore, the current i _BIAS is reduced by 1/2 during the time period during which the clock signal C50 is low.

The operation of the dynamic bias circuit 60 and its effect on the bias current i _BIAS in the memory access cycle will be described below with reference to FIG. Time t ₀ indicates the condition of memory 10 at the end of the previous cycle in steady state. Data terminal D
Q provides the output data value DATA ₀ from the previous cycle. Clock C50 is low at this time. This is because output switching has not occurred. Therefore, the current i _BIAS is half of its maximum value. This is because transistor 72 (FIG. 7) has been turned on by inverter 71, placing transistor 74 in parallel with transistor 64 of bias reference circuit 54, thus reducing the mirror ratio of transistor 52. This reduces the current i _BIAS drawn by the reference voltage regulator 24 during the time period in the memory access cycle where output switching is not scheduled, and thus during that period, the previous data state (ie, DATA). Only ₀ ) is maintained. The output impedance of the reference voltage and regulator 24 may be relatively high during this time period, but the voltage on line VOHREF is maintained at its correct steady state level.

At time t ₁ , a new memory access cycle is initiated by the activation of the input clock CLK, while in a completely static memory, for example, the clock CLK is the address or data input of the memory. It is possible to respond to edge transition detection pulses generated by detecting transitions at the terminals. In response to the leading edge of clock CLK, it is activated after a selected delay, which corresponds to a safer time less than the minimum expected read access time of the memory. When clock signal C50 is activated at time t ₂ , transistor 72 is activated.
Is turned off by the operation of the inverter 71. Therefore, the current mirror ratio of the transistor 52 has its maximum value (in this embodiment, before the time when the output buffer 21 and the output driver 20 start driving the data terminal 28 to the new data state (that is, DATA ₁ ). In 1)
Returned to. After another delay time sufficient to ensure that the new data state DATA ₁ is stable, the clock signal C50 returns to the low state as shown at time t ₃ in FIG. This causes transistor 72 to turn on and, in this embodiment, i _BIAS to its maximum value of 5.
It reduces to 0% and thus reduces the DC current flowing through the reference voltage regulator 24.

Adjustable Bias Current Source Next, referring to FIG. 9, a bias current source 26 'constructed in accordance with another embodiment of the present invention will be described in detail. Bias current source 26 'is controllable by a clock signal as in the case of dynamic bias circuit 60 described above, or by a reference voltage controllable by other control signals on control bus C generated by fuse and control circuit 25. _Provides multiple level adjustments of the current i _{BIAS to} the regulator 24. As such, the current i _BIAS can be optimized for a particular application by programming the fuse at a later stage in the manufacturing process or by the generation of a control signal or condition by the user. Therefore, it is possible to optimize the performance of the output driver in particular. Bias current source 26 'incorporates a bias reference circuit 54 and a current source transistor 52 connected to the reference voltage and regulator 24 as before. Further, as described below with reference to FIG. 7, transistors 72 and 74
Is the current i when transistor 72 is turned on.
It is provided to reduce _BIAS to 50% of its previous value. However, in this case, the transistor 7
The gate of No. 2 is controlled by the NAND function unit 73, which has a control signal C from the control bus C at one input terminal.
50 and receives at another input node FEN5
It receives the output of the fuse circuit 75 on 0 *.

Fuse circuit 75 provides the programmable or writable nature of the state of transistor 72 in a permanent manner. Such programmable ability is
It may be useful in the early stages of design and manufacture of memory 10 if the optimal value of i _BIAS has not yet been determined. Further, if the process variation in the manufacture of the memory 10 is sufficiently high and the optimum value of i _BIAS is set appropriately after the initial test of the memory 10, then i
A programmable characteristic of the value of _BIAS is desirable. For example, if memory 10 is processed to have a very short channel width, the value of i _BIAS is preferably reduced by programming fuse circuit 75 to keep transistor 72 on all the time. It is possible to Additionally, fuse circuit 75 may be programmed to select the desired output slew rate for a particular system application. For example, if an integrated circuit is intended for a relatively moderate performance application where noise and power dissipation are high concerns, optimizing the circuit will reduce the output impedance of the circuit. It is possible to have a relatively slow output slew rate by increasing it, which reduces the current supply capability of the pull-up transistor 32 in the output driver 20 and thus the output circuit according to this embodiment of the invention. Reduced noise and power dissipation. On the other hand, if the highest switching speed is desired despite power dissipation and noise issues, then the circuit should have the lowest output impedance and thus the fastest output slew rate and maximum current supply and sink capability. It is possible to optimize In other applications, operating points between these extremes may be desired, which is obtainable by the present invention.

The configuration of fuse circuit 75 can be accomplished in any one of a number of conventional ways. The example of FIG. 9 is simply from V _CC and its output to node F
It only has a fuse 76 connected between it and the input of an inverter 77 driving EN50 *.
Transistors 78 and 79 have their source / drain paths connected between the input of inverter 77 and ground. The gate of transistor 78 receives the power-on reset signal POR, so transistor 78 pulls up the input of inverter 77 to ground as memory 10 powers up. The gate of transistor 78 is connected to the output of inverter 77 at node FEN50 *. In operation, if the fuse 76 remains untouched, the node FEN50 *
Is held low by the operation of inverter 77.
When fuse 76 is opened, the pulse on line POR pulls the input of inverter 77 low, which causes node F
Drive EN50 * high and turn on transistor 78 to maintain this condition.

To explain the operation, the output terminal of the NAND function section 73 has a control signal C50 or a node FEN50.
High if any of the * 's are low. Therefore, when the fuse 76 is not opened, the node FEN50 * is kept low and the NAND function unit 7
The zero output is maintained high and transistor 72 is unconditionally maintained on. When fuse 76 is opened, control signal C50 controls the state of transistor 72, as in the case of FIG. 8 described above.

It should be noted that the generation of the control signal C50 can be done in several ways. For example,
The fuse and control circuit 25 of FIG. 1 can have a writable register, in which case the control signal C5
The 0 state can be set by the system user in a special test or operating mode, such as those enabled by a special overvoltage condition applied to some terminals of the device, such that In addition, the output driver capability can be programmed by the system manufacturer in a "permanent" fashion once the specific system application for the device is known. On the other hand, the state of the control signal C50 can be controlled by an external signal applied to the integrated circuit during the use period, or can be controlled by setting a writable register during the normal operation period. In that case, it is possible to adjust the output drive characteristics after the system is incorporated into the integrated circuit. In yet another embodiment, the state of the control signal C50 can be set by the manufacturer via the bond wire option, in which case the signal C50 will be either V _CC or ground during the bonding period. Directly or indirectly controlled by the voltage at the bond pad of the chip that can be connected to

Of course, the memory 10 can also be realized without the control signal C50, in which case the state of the transistor 72 depends only on the programmed state of the fuse circuit 75. In this way, integrated circuit manufacturers, upon knowing the requirements for integrated circuits that meet certain device specifications, will use laser programming operations similar to those used to enable redundant memory locations. It is possible to set the output driver characteristics at the end of the manufacturing cycle. Further, integrated circuit manufacturers can program integrated circuits based on their own performance characteristics. For example, if an integrated circuit is manufactured with relatively slow dynamic performance (eg, high threshold voltage and long transistor channel length), the manufacturer will have a slew rate with a relatively slow output drive characteristic. May be programmed to This is because the integrated circuit cannot meet the high-performance specifications anyway. However, for integrated circuits manufactured under high performance process conditions, the manufacturer has the best output drive characteristics with the highest slew rate and the lowest output impedance to achieve the best performance. May be programmed to The circuit of FIG. 9 allows such programming of output drive characteristics.

Bias current source 26 'according to another embodiment of the present invention also has transistors 72' and 74 'connected in series between node ISVR and ground in a manner similar to transistors 72 and 74 previously described. have. The gate of transistor 72 'is similarly controlled by NAND function 73' in response to the state of clock signal C67 and fuse circuit 75 'via node FEN67 *. However, the dimensions of transistor 74 'have been chosen to be different than the dimensions of transistor 74, and therefore transistor 72' will be clocked by clock signal C67.
Alternatively, when turned on by either fuse circuit 75 ', the current i _BIAS is selected to be a different percentage of its maximum value. For example, if the channel width of transistor 74 'is half that of transistor 52 and transistor 64 in bias reference circuit 54 (assuming the channel lengths are the same), the effective channel width of the parallel combination of transistors 64 and 74'. Is 1.5 times the channel width of the transistor 52. Therefore, the transistor 7
The value of i _BIAS when _4'is turned on is 2 / of its maximum value when transistor 74 'is turned off.
It is 3.

Of course, different values of the current i _BIAS are desired to be permanently programmed, clocked in at a specified time of the memory cycle, or under system control. If desired, other transistors of different sizes can be implemented in bias current source 26 'as well.
Furthermore, it is possible, for example, to turn on both transistors 72, 72 'simultaneously to further reduce the current i _BIAS . Other configurations for reducing current will be apparent to those skilled in the art.

According to this alternative embodiment of the invention, the value of the bias current i _BIAS may be different for individual memory circuits, depending on the particular design, depending on the processing parameters determined by electrical testing. It can be optimized at specific times during the memory cycle. This optimization makes it possible, on the one hand, to optimize the tradeoff between the maximum supply current and the sink current and the minimum output impedance for the reference voltage / regulator 24, and on the other hand the reference. It makes it possible to optimize the current drawn by the voltage regulator 24. Further, the desired output slew rate can be selected by selecting the desired current mirror ratio.

Variable bias with programmable bias voltage
Rourate Control Next, referring to FIG. 12, there is shown a state in which the V _CC and the process-compensated bias circuit 20 as described above are incorporated in the output driver circuit. The structure of the output buffer 21 _j and the output driver circuit 20 _j shown in FIG. 12 corresponds to that described with reference to FIG. is there. However, FIG. 12 illustrates the output driver 20 as described below.
The preferred embodiment of the inversion buffer 43 is shown in detail in such a way as to control the slew rate of _j .

As shown in FIG. 12, the gate of N-channel pull-down transistor 34 is driven from the drains of P-channel transistor 112 and N-channel transistor 114, and the gates of transistors 112 and 114 receive the input data signal from NAND gate 42. Are connected (see FIG. 2). Thus, transistors 112 and 114 implement a logical inversion of the logical state of the output of NAND gate 42. The source of transistor 114 is biased to ground, while the source of transistor 112 is the P-channel bias transistor 1.
10 and the source of transistor 110 is biased to V _CC . The gate of the P-channel bias transistor 110 has a bias circuit 120.
Driven by the voltage on line BIAS generated by In this configuration, the current conducted by transistor 110 controls the drive current of transistor 112 when transistor 34 is turned on driving a low logic level at terminal 28 _j . Thus, transistor 110 controls the rate at which the gate of transistor 34 is pulled high in response to a transition on the input data line. Therefore, the current of the transistor 110 is
Controls the rate at which pull-down transistor 34 is turned on when output terminal 28 _j is switched from a high logic level to a low logic level. In the embodiment of FIG. 12, the slew rate control by the inverting buffer 43 is applied only to the N-channel pull-down transistor 34. This is because the driving of the N-channel pull-up transistor is controlled by the voltage on the line VOHREF and the output impedance of the reference voltage / regulator 24 that drives the line VOHREF.

As is known in the art, inductive noise occurs as a result of the rate of change of the current applied to the load over time (dV = Ldi / dt). Therefore, if the switching speed is high, the noise usually increases. This is because the time change rate of the current increases. Circuit designers typically select operating points under optimal conditions in relation to switching speed and noise. As described above, in order to maintain this optimized operation, the bias circuit 120 provides a bias voltage on line BIAS that compensates for variations in power supply voltage and process variations,
Therefore, a stable output drive operation is provided. Therefore, the voltage at the gate of transistor 110 in output buffer 21 follows the variations in the V _CC power supply voltage (at the source of transistor 110). As a result, the current conducted through transistor 110 in output buffer 21 remains substantially constant with such variations in the V _CC supply voltage. This is because its gate-to-source voltage remains constant.

As mentioned above, in accordance with the preferred embodiment of the present invention, line B generated by bias circuit 120.
The voltage on IAS can either be selected fuse open or programmed by a control signal on bus C. This voltage programmability on line BIAS allows to select the slew rate at which transistor 34 in output driver 20 turns on, thus providing more control over the output drive capability of the integrated circuit.

A bias circuit 120 'constructed according to another embodiment of the present invention will be described in detail with reference to FIG. Components in circuit 120 'that are similar to those in circuit 20 described above are labeled with similar reference numbers.

The bias circuit 120 'is constructed similarly to the bias circuit 20 described above. However, in this embodiment, the linear load transistor 134
Is set by a voltage divider 138 so that the gate voltage is a specified percentage of the V _CC supply voltage. Transistor 134 operates as a substantially linear load,
In reality, it is a voltage controlled resistor whose on-resistance is a function of gate-to-source voltage. Figure 1 shows only part of V _CC
By applying it to the gate of transistor 134 as shown in FIG. 3, it is possible to reduce the undesired decrease in the resistance of transistor 134 when V _CC makes a positive transition.

Further, as shown in FIG. 13, the resistors 125 and 127 in the voltage divider of the bias circuit 120 'are connected in parallel with the corresponding shorting transistors 124' and 126 '. In the present embodiment, the shorting transistors 124 'and 126' are of the field effect type and have gates controlled by control signals C _H and C _L , respectively, which signals are fuse and control. This is a signal from the control bus C from the circuit 25. Thus, bias circuit 120 'is shown to use a control signal to set the voltage on line BIAS by selectively switching resistors 125, 127 into and out of the voltage divider of bias circuit 120'. ing. Of course, fuses can be used in the configuration of Figure 13 if permanent programmability is desired.

Bias circuit 120 'according to this embodiment of the invention further includes circuitry for disabling the slew rate control function if desired. When the bias function is disabled, transistor 110 of output buffer 21 is fully turned on, forming a low logic level on line BIAS in this embodiment. As shown in FIG. 13, NOR functional unit 140 receives inputs on lines DIS and STRESS, for example. Line DIS is generated elsewhere in the integrated circuit and provides a high logic level when bias circuit 120 'is to be disabled. Line DIS can be dynamically generated to be present for a particular operation, and line DIS forces bias circuit 120 'to open by opening a fuse during the manufacturing process. It is also possible to drive it by a fuse circuit so as to bring it into the enabled state. Line STRESS provides a high logic level during a particular test mode, such as when an abnormally high voltage is supplied to a node in an integrated circuit. Line STRESS is generated, for example, by a special test mode control circuit in response to overvoltage conditions, as is known in the art.

Therefore, the output terminal of the NOR gate 140 is
In response to neither line DIS or STRESS at its input being asserted, a high logic level signal is provided on line EN to enable bias circuit 120 '. Conversely, NOR gate 140 provides a low logic level on line EN in response to any of the disable conditions represented on lines DIS and STRESS. Line EN is passgate 1
42 is directly connected to the N channel side of 42 and is also connected to the P channel side of the pass gate 142 via the inverter 141, so that the pass gate 142 is conductive when the line EN is high. , And open when line EN is low (ie, when line DEN is high at the output of inverter 141). Line DEN is further connected to the gates of N-channel transistors 144 and 146. Transistor 144 has its drain connected to the gate of transistor 128.
6 has its drain connected to line BIAS, and the sources of transistors 144, 146 are connected to ground.

In operation, line EN and line DIS are both low because line DIS and STRESS are both low.
Is high, pass gate 142 is conductive and transistors 144 and 146 are turned off. The operation of bias circuit 120 'under this condition is the same as the operation of bias circuit 120 described above, so line BIAS follows changes in the V _CC supply voltage,
As described above, the transistor 110 in the inversion buffer 43 is controlled in such a manner as to maintain the operation at or near the optimized condition. Line DIS and STRES
If line EN is low and line DEN is high due to any one of S being asserted high, then pass gate 142 is turned off. Transistor 144 is line DEN
Is turned on by a high state, which turns off transistor 128 by pulling its gate to ground, which means that transistor 1
Inhibiting the conduction of current through either of 30,30. Transistor 146 is also turned on by the high state of line DEN, which pulls line BIAS to ground. Referring again to FIG. 12, the P-channel transistor 110 is connected to the line BIA.
It is fully turned on by S being at ground, in which case the slew rate of pull-down transistor 34 is uncontrolled. The bias circuit 120 'according to this embodiment makes it possible to selectively disable the slew rate control function.

Variable Output V _OH Control According to yet another embodiment of the present invention, the selectability of the VOHREF limiting function is provided either by a logic signal or by fuse programmable capability. This embodiment of the invention takes into account that not all memories of the same design can be specified for use in combination with other integrated circuits using lower power supplies. . For example, a portion of the memory in the subset That pair has a V _OH maximum of 5.0V, whereas a different subset in some cases have a V _OH maximum limited to 3.3V. For ease of manufacturing and inventory control, it is preferable to have a single integrated circuit design suitable for use as either, in which case the slowest possible stage of the manufacturing process. At 5.0V or 3.3
It is desirable to be able to make a decision between V _OH max of V. In addition, the relevance of a particular memory chip for 3.3V operation may depend on processing parameters, such as drive current, and thus the memory may be 3.3V even if the VOHREF limiting function is not enabled. 5.0 may not meet the operating specifications.
An operating specification for a memory having a _VOH maximum of V may be met. In this case, after the electrical test, V
It is desirable to have the selectivity of the OHREF limiting function.

In yet another embodiment, the memory 10
It may be useful to have a special test mode for the VOHREF limit function, in which case the VOHREF limit function can be selectively enabled and disabled.

Referring now to FIG. 10, there is shown another embodiment of the present invention in which the reference voltage / regulator 124 is constructed similarly to the reference voltage / regulator 24 described above. However, it can be disabled by an external signal, a special test mode signal, or programming of the fuse circuit. Components common to the reference voltage / regulator 24 and the reference voltage / regulator 124 are designated by the same reference numerals, and detailed description thereof will not be repeated for the reference voltage / regulator 124 of FIG. Omit.

In addition to the components previously described, the reference voltage / regulator 124 includes P-channel transistors 82, 8
4, 89 and N-channel transistor 86, which are NOR gate 80 as described below.
Forces some nodes to V _CC or ground when the VOHREF limiting function is to be disabled, as represented by the output of Each of P-channel transistors 82, 84, 89 has its source biased to V _CC , and its gate receives line LIMOFF * from the output of NOR gate 80. The drain of the transistor 82 is connected to the gates of the transistors 44 and 46 in the current mirror of the reference voltage / regulator 124, the drain of the transistor 84 is connected to the line VOHREF at the output of the reference voltage / regulator 124, Moreover, the drain of the transistor 89 is connected to the input terminal to the bias reference circuit 54. The N-channel transistor 86 has its drain connected to the bias current source 26.
At node ISVR, its source connected to ground, and its gate connected to inverter 8
After inversion by 5, it receives the signal LIMOFF *. According to this embodiment of the present invention, pass gate 88 provides voltage BIAS.
And a bias reference circuit 54, and is controlled by a true signal based on the signal LIMOFF * and its complement signal.

The operation will be described below. NOR gate 8
When the line LIMOFF * at the 0 output is at a high logic level, transistors 82, 84, 86 and 89 are all turned off and pass gate 88 is turned on. In this case, the reference voltage
Line VOHREF in the manner described above for regulator 24.
Operates to limit the voltage at.

However, when the line LIMOFF * at the output of NOR gate 80 is at a low logic level, transistors 82, 84, 86 and 89 are all turned on and pass gate 88 is turned off. Under this condition, line VOHREF is forced to 5.0.
The drain voltage applied to V and thus to output buffer 21 (and thus to the gate of pull-up transistor 32 in output driver 20) is not limited to a reduced level. Reference voltage / regulator 12
In order to minimize the DC current drawn through 4,
Certain nodes within it are also forced to a particular voltage. In this embodiment, the gates of transistors 44 and 46 are pulled to V _CC by transistor 82, thus turning off both the reference and mirror branches in reference voltage regulator 124. Pass gate 88 blocks the voltage BIAS from bias reference circuit 54, transistor 89 pulls the input to bias reference circuit 54 to V _CC , and transistor 86 pulls node ISVR to ground, thus transistors 52 and 58. Turn off. Of course, the output terminal of the NOR gate 80 can be applied to a node such as the offset compensating current source 28 and the bias reference circuit 54, if desired.

In this embodiment of the invention, NOR gate 80 receives three inputs and drives line LIMOFF * low when any one of its inputs is at a high logic level. The first input is the logic signal DIS, which can occur elsewhere in the memory 10, for example in the timing and control circuit 14, for example the input or instruction of which the logic signal DIS is activated. The combination can be applied to the memory 10. NOR gate 80 on node FDIS
The second input of is generated by the fuse circuit 90. Fuse circuit 90 is constructed as described above with respect to fuse circuit 75, so that node FDIS is at a logic low level when the fuse remains unchanged and a high logic level when the fuse is blown open. Becomes

According to this embodiment of the present invention, the special test pad TP enables and disables the reference voltage / regulator 124 during the electrical test in wafer form (ie, before packaging). It is possible to control. The test pad TP is connected to the input of an inverter 91, which drives the node TDIS which is received as the input of the NOR gate 80. The transistor 92 has its source / drain path connected between the input terminal of the inverter 91 and the ground,
Moreover, its gate is connected to the node TDIS at the output terminal of the inverter 91. The transistor 93 has its source / drain path connected between the input end of the inverter 91 and the ground, and its gate is controlled by the power-on reset signal POR.

To explain the operation, the test pad T
Inverter 91 forces node TDIS low when P is held at V _CC . However,
When the test pad TP is kept open or connected to ground, it is powered up and the transistor 93 pulls the input of the inverter 91 low.
Force a high logic level on node TDIS, which is maintained through the operation of transistor 92. The test pad TP is a reference voltage / regulator 1 during the electrical test period.
It is possible to control the enable and disable operations of 24. Depending on the results of such a test, it is possible to wire bond test pad TP to V _CC if reference voltage regulator 124 is permanently enabled, or reference voltage regulator 124. Can be left open (preferably hard-wired to ground) if it is to be permanently disabled for a particular memory 10.

The selective enabling and disabling of the V _OH limiting function of the reference voltage / regulator according to the present invention significantly improves the manufacturing control of integrated circuits incorporating such functions. . In particular, integrated circuits corresponding to different specification limits can be manufactured from the same design by selecting maximum V _OH voltage after electrical testing and later in the manufacturing process. In addition, as mentioned above, fuse programming can be used to adjust the voltage divider that provides the input voltage to the voltage reference regulator circuit, which allows additional tuning of the desired maximum V _OH voltage. It is possible.

Conclusion Therefore, according to the preferred embodiment of the invention described above, the optimization of the performance of the output driver circuit does not need to be selected in the design process, but instead at a later stage in the manufacturing process or in the integration. It is provided in a manner selectable by the user of the circuit. This optimization is provided by the ability to permanently or temporarily program the output impedance of the circuit that provides the reference drive voltage to the output buffer by selecting the current mirror ratio. Such optimization is further provided by the programmable ability of the reference voltage to control the slew rate of the output buffer. As a result, it is possible to obtain optimum device performance for a particular implementation without complicating inventory control for integrated circuit or system manufacturers.

Of course, various modifications of the above-described embodiment can also obtain the advantages of the present invention. For example, the case where the single bias circuit 120 is provided for both of supplying the bias voltage to the reference voltage / regulator 24 and generating the voltage for controlling the slew rate of the output driver has been described. It is also possible to provide a separate bias circuit for, especially if programming of the bias voltage is selected for one of these functions but not the other. Bias circuit can be provided.

Although the specific embodiments of the present invention have been described above, the present invention should not be limited to these specific examples, and various modifications can be made without departing from the technical scope of the present invention. Of course, it is possible.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing an integrated memory circuit incorporating an output drive circuit according to a preferred embodiment of the present invention.

FIG. 2 is a schematic diagram showing an output drive circuit according to a preferred embodiment of the present invention.

FIG. 3 is a schematic diagram showing a reference voltage and regulator circuit according to a preferred embodiment of the present invention.

FIG. 4 is a schematic diagram showing a bias current source used in a reference voltage and regulator circuit according to a preferred embodiment of the present invention.

FIG. 5 is a timing diagram illustrating the operation of a reference voltage and regulator circuit according to a preferred embodiment of the present invention when no offset compensating current is present.

FIG. 6 is a timing diagram illustrating the operation of a reference voltage and regulator circuit according to a preferred embodiment of the present invention when an offset compensating current is present.

FIG. 7 is a schematic diagram showing a dynamic bias control circuit used in a reference voltage regulator circuit according to a preferred embodiment of the present invention.

FIG. 8 is a timing diagram showing the operation of the circuit of FIG. 7 in an integrated circuit memory.

FIG. 9 is a schematic diagram showing a bias current source according to a preferred embodiment of the present invention having a programmable bias current level.

FIG. 10 is a schematic diagram showing a reference voltage and regulator circuit according to another embodiment of the present invention.

FIG. 11 is a schematic diagram showing a bias circuit according to a preferred embodiment of the present invention.

FIG. 12 is a schematic diagram showing an output buffer circuit according to a preferred embodiment of the present invention.

FIG. 13 is a schematic diagram showing a bias circuit according to another embodiment of the present invention.

[Explanation of symbols]

 10 memory 12 address register 14 timing / control circuit 16 memory array 17 write circuit 18 input driver 19 read circuit 20 output driver 21 output buffer 22 output buffer bias circuit 24 reference voltage / regulator 25 fuse / control circuit 26 bias current source 28 offset Compensation current source 32 Pull-up transistor 34 Pull-down transistor

Claims (28)

[Claims] 1. An output driver circuit for driving an output node in response to a data signal received at a data node, comprising a conduction path connected between the output node and a first power supply voltage and a control terminal. And a slew rate control function unit having an input end coupled to a data node and an output end coupled to a control terminal of the first drive transistor. The slew rate control function unit is connected in series with the conduction path of the current limiting transistor between the control terminal of the first drive transistor and the first voltage, and the current limiting transistor having a conduction path and a control electrode. A first transistor having a control path coupled to a data node and having a conducting path connected to the control node. A first transistor which, when applied to a terminal, causes said first voltage to turn on said first drive transistor, and which is connected on one side to the control terminal of said first drive transistor and on the other side to a second voltage A second transistor having a control path coupled to the data node and a biasing circuit for applying a bias voltage to the control terminal of the current limiting transistor that follows variations in the first voltage. The bias circuit is coupled between the first voltage and a reference voltage, and has a resistance voltage divider for generating a divided voltage, the resistance voltage divider is a power supply. A plurality of resistors connected in series between the voltage and the reference voltage, and one of the plurality of resistors
And a means for short-circuiting the one of the plurality of resistors, the bias circuit having a current mirror having a reference branch and an output branch, A current flowing through the reference branch is controlled by the divided voltage, the output branch conducting a mirrored current corresponding to the current flowing through the reference branch, An output driver circuit comprising: a load that conducts a mirrored current and that generates the bias voltage at a bias output node in response to the mirrored current. 2. The output driver circuit according to claim 1, wherein the short-circuit means has a fuse connected in parallel with the one of the plurality of resistors. 3. The short-circuit means according to claim 1, wherein the short-circuit means comprises a transistor having a conduction path connected in parallel with the one of the plurality of resistors and having a control electrode for receiving a short-circuit signal. Characteristic output driver circuit. 4. The voltage divided voltage according to claim 1, wherein the divided voltage is generated at a node between the first group and the second group of the plurality of resistors, and the short-circuiting means among the plurality of resistors. An output driver circuit in parallel with at least one of the first groups and in parallel with at least one of the second groups of the plurality of resistors. 5. The second drive transistor according to claim 1, further comprising a conduction path connected between the output node and the second power supply voltage, and a control terminal, wherein the second drive transistor is responsive to the bias voltage. A circuit for limiting the driving of the second drive transistor is provided, a reference voltage / adjuster circuit for generating the bias voltage is provided, and the reference voltage / adjuster circuit is the power supply. A current mirror having a voltage divider for generating a divided voltage based on a voltage, and a reference branch and a mirror branch, the reference branch receiving the divided voltage from the voltage divider and responding to the reference. A current transistor that conducts a current and causes the mirror branch to conduct a mirrored current in response to the reference current and derive the bias voltage based on the mirrored current. And a bias current source coupled to the reference branch of the current mirror and the mirror branch for conducting a controlled current to control the reference current and the mirror current, and a controlled current to be conducted by the current source. An output driver circuit having a circuit for selecting a current. 6. The bias current source according to claim 5, further comprising a source / drain path having one end connected to the reference branch and the mirror branch of the current mirror and the other end connected to a reference voltage. A current control device having a bias current source transistor having a gate, wherein the selecting means is coupled between the first voltage and a common node connected to the gate of the bias current source transistor. A first bias reference transistor having a source / drain path connected between the common node and a reference voltage and having a gate connected to the drain thereof; An output driver circuit comprising: a first adjustment branch that conducts current between a common node and a reference voltage. 7. The output driver circuit according to claim 6, further comprising a second adjustment branch for conducting a current between the common node and the reference voltage in response to the second selection signal. 8. The output driver circuit according to claim 6, further comprising a fuse circuit for generating the first selection signal. 9. The output driver circuit according to claim 6, further comprising a control circuit for generating the first selection signal. 10. The output driver circuit according to claim 1, wherein the load includes a linear load device. 11. An output driver circuit for driving an output node in response to a data signal received at a data node, comprising a conduction path connected between said output node and a power supply voltage, and comprising a control terminal. A drive transistor is provided, a circuit that limits the drive of the drive transistor in response to a bias voltage is provided, and a reference voltage / regulator circuit for generating the bias voltage is provided. The reference voltage / regulator circuit is a voltage divider that generates a voltage divided based on the power supply voltage, a current mirror having a reference branch and a mirror branch,
The reference branch receives the divided voltage from the voltage divider and conducts a reference current in response thereto, and the mirror branch conducts a mirrored current in response to the reference current and the mirror operation. A current mirror for deriving a bias voltage based on the generated current; a bias current source coupled to the reference branch of the current mirror and the mirror branch for conducting a controlled current to control the reference current and the mirror current; An output driver circuit, the circuit selecting a controlled current to be conducted by the current source. 12. The bias current source according to claim 11, further comprising a source / drain path having one end connected to a reference branch and a mirror branch of the current mirror and the other end connected to a reference voltage. And a bias current source transistor having a gate, wherein the selection means is coupled between a first voltage and a common node connected to the gate of the bias current source transistor, A bias reference transistor having a source / drain path connected between the common node and a reference voltage and having a gate connected to its drain, the common node and the reference in response to a first select signal An output driver circuit comprising: a first adjusting branch for conducting a current between the voltage and the voltage. 13. The output driver circuit according to claim 12, further comprising a second adjustment branch for conducting a current between the common node and a reference voltage in response to a second selection signal. 14. The output driver circuit according to claim 12, further comprising a fuse circuit for generating the first selection signal. 15. The output driver circuit according to claim 12, further comprising a control circuit for generating the first selection signal. 16. A method of determining drive characteristics of an output driver circuit in an integrated circuit, said output driver circuit comprising a conduction path connected between an output node and a first power supply voltage and having a control terminal. Comprising a first drive transistor comprising a control terminal driven to a first bias voltage to turn on the first drive transistor, to a first branch and a second branch of the voltage divider. The first and second selected resistance values are respectively arranged, a power supply voltage is applied to the voltage divider to generate a divided voltage, and the divided voltage is controlled in a saturation region. Controls the reference current in the reference branch of the current mirror by applying it to the terminal, and mirrors the reference current to generate the mirrored current in the output branch of the current mirror. , Causing the mirrored currents generate a first bias voltage is applied to the load in the output leg of the current mirror,
A method comprising the above steps. 17. The voltage divider according to claim 16, wherein each of the first branch and the second branch of the voltage divider has a plurality of resistors in series with each other, and the plurality of resistors in each of the first branch and the second branch. At least one of the resistors has a fuse connected in parallel, and in the arranging step, at least one fuse in at least one of the first branch and the second branch of the voltage divider is opened. A method characterized by. 18. The pressure divider according to claim 16, wherein each of the first branch and the second branch of the voltage divider has a plurality of resistors in series with each other, and each of the first branch and the second branch has a plurality of resistors. At least one of the plurality of resistors has a short-circuit transistor connected in parallel, and in the disposing step, a signal is applied to the short-circuit transistor in the first and second branches of the voltage divider to be connected in parallel therewith. A method of selecting whether or not the resistance being applied affects the voltage divider. 19. The second driver transistor according to claim 16, wherein the output driver circuit has a conduction path connected between the output node and a second power supply voltage, and has a control terminal. Wherein the control terminal of the second drive transistor is driven to a second bias voltage to turn on the second drive transistor, the method further comprising selecting a bias current, Generating a second bias voltage by controlling a current mirror comprising a mirror branch, wherein the current flowing through the reference branch is based on a power supply voltage and a divided voltage based on a selected bias current value. The controlled and the divided voltage defines the second bias voltage, the second bias voltage being the output buffer transistor. A second bias voltage applied to an output buffer transistor to turn on the output buffer transistor in response to receiving a data input signal indicating that a second drive transistor in the output driver should drive the output node. Is applied to the control electrode of the second drive transistor. 20. When selecting the bias current according to claim 19, a bias voltage is applied to a reference branch of the current mirror, and a current conducted by the reference branch of the current mirror is controlled by the bias voltage. And the current mirror has a mirror branch for conducting the selected bias current corresponding to the product of the reference current and the mirror ratio, and at least one adjustment coupled in parallel with the reference branch of the current mirror. A method of turning on a transistor to change a mirror ratio of the current mirror. 21. The method of claim 20, wherein, when turning on the adjusting transistor, the fuse is opened so that the adjusting transistor is biased to the on state. 22. The method of claim 20, wherein applying a logic signal to at least one control electrode of the adjusting transistor when turning on the adjusting transistor. 23. The bond transistor of claim 20, wherein the adjustment transistor has a control electrode coupled to a bond pad of the integrated circuit, and the bond pad is connected to a fixed voltage when the adjustment transistor is turned on. And thus turning on the regulation transistor. 24. A method of determining drive characteristics of an output driver circuit in an integrated circuit, wherein the output driver circuit comprises a conduction path connected between an output node and a first power supply voltage and a control terminal. And a control terminal driven to a bias voltage to turn on the drive transistor, the method comprising: selecting a bias current, comprising: a reference branch and a mirror branch. Generating a bias voltage by controlling a current mirror that controls the current mirror, wherein the current flowing through the reference branch is controlled by a divided voltage based on the power supply voltage and a value of the selected bias current, and The divided voltage defines the bias voltage, the bias voltage being the output buffer transition. A bias voltage to control the drive transistor by turning on the output buffer transistor in response to receiving a data input signal indicating that the drive transistor in the output driver should drive the output node. A method comprising the steps of applying to an electrode. 25. The selection of the bias voltage according to claim 24, wherein a bias voltage is applied to a reference branch of the current mirror, and a current conducted by the reference branch of the current mirror is controlled by the bias voltage. And the current mirror has a mirror branch for conducting the selected bias current corresponding to the product of the reference current and the mirror ratio, and at least one parallel branch is connected to the reference branch of the current mirror. Turning on an adjusting transistor to reduce the mirror ratio of the current mirror. 26. The method of claim 25, wherein when turning on the adjusting transistor, the fuse is opened and thus the adjusting transistor is biased on. 27. The method of claim 25, wherein applying a logic signal to a control electrode of at least one of the adjusting transistors when turning on the adjusting transistor. 28. The adjustment transistor of claim 25, wherein the adjustment transistor has a control electrode coupled to a bond pad of the integrated circuit and connects the bond pad to a fixed voltage when turning on the adjustment transistor. And turning on the adjusting transistor.