JPH08315573A - Voltage regulator for output driver with decreased output impedance - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a reference voltage circuit which can supply a relatively large current while the circuit avoids the generation of an offset voltage. SOLUTION: A voltage regulator for output driver is provided with a reference voltage regulator 24 which generates a limited high output voltage or a reference voltage to be applied across a circuit requiring a sink current other than an output buffer is provided. The reference voltage regulator 24 is constituted based on a current mirror and the sum of currents in the current mirror is controlled by a bias current source which can dynamically control the sum in an operation cycle or program the sum by means of a fuse. The voltage regulator is also provided with sink current route circuits 25 and 25' which give additional sink current routes when the limited high output voltage or reference voltage exceeds a desired level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the technical field of integrated circuits, and more particularly to output driver circuits for integrated circuits.

[0002]

2. Description of the Prior Art In modern digital integrated circuits, especially those manufactured based on the well-known complementary metal-oxide-semiconductor (CMOS) technology, circuit operation often allows the use of stable reference voltages. Depends on being. For example, many functional circuits within integrated circuits rely on current sources to conduct stable currents. Examples of such functional circuits include differential amplifiers, current mirrors,
There are operational amplifiers (operational amplifiers), level shift circuits, and circuits that generate a reference voltage by themselves. Since the current source is usually realized by an N-channel field effect transistor, the stability of the current source depends on the stability of the reference voltage applied to the gate of the N-channel field effect transistor.

Referring now to FIG. 11, a conventional reference voltage generator circuit based on a current mirror is shown. The reference voltage circuit of FIG. 11 has P-channel transistors 1, 3 connected in the form of a current mirror, their sources being biased to V _CC and their gates at the drain of transistor 1. Commonly connected. The drain of the transistor 1 is connected to the drain of the N-channel transistor 7, and the gate of the transistor 7 is V determined by the voltage divider 5.
Connected to receive _CC percentage. Transistor 1
And 7 form the reference branch of the current mirror. The drain of the transistor 3 is connected to the drain and gate of the N-channel transistor 9, where the reference voltage V _REF is generated. Thus, transistors 3 and 9 form the mirror branch of this current mirror,
The current conducted by transistor 3 "mirrors" the current conducted by transistor 1. The sources of the transistors 7, 9 are commonly connected to a current source 11, which conducts the current i _BIAS, which in this example is the sum of the currents flowing through the reference branch and the mirror branch. Is.

The conventional current mirror based reference voltage circuit of FIG. 11 is useful in certain applications. For example, if transistors 3 and 9 are configured to be fairly large (ie, the channel width to channel length ratio is relatively large), the output impedance of the circuit of FIG. _Allows relatively large currents to be sourced (ie, source) and sink (ie, sink) without producing significant modulation in the voltage at _REF . When such large supply and sink currents are applied, the mirror ratio (ie the ratio of the size of transistor 3 to the size of transistor 1) is large, reducing the DC current drawn by this circuit. It is also desirable to provide current amplification.

However, it has been observed that the circuit of FIG. 11 is exposed to the generation of offset voltage therein. For example, it has been found that the voltage at the drains of transistors 1 and 7 drops when a significant supply current is required to be generated on line V _REF . This is because the current through transistor 9 is reduced to almost zero (all the current in the mirror branch is supplied to line V _REF ). Due to the small size of transistor 1 which requires that the Miller ratio be large enough to supply the desired supply current and because it is in the form of a diode, transistor 1 has a fast node at its drain. Is impossible to pull up to, which allows the voltage on line V _REF to overshoot its desired voltage (transistor 3 is turned on relatively hard).
The overshoot on this line V _REF is
It is undesired when applied to a circuit that depends on a stable voltage on _REF . Other circuits that might receive the voltage on line V _REF is may emit a current demand for significant supply or sink on the line V _REF (suction), adversely affecting the stable voltage that it Becomes

Furthermore, the current per unit channel width is different in the reference branch relative to the mirror branch, especially when conducted by transistors 7 and 9, but the voltage V _REF is inaccurate. It may stabilize to a steady state value.

Furthermore, it is desirable to provide as much current drive as possible at the output of the reference voltage circuit. However, while the supply current provided by transistor 3 can be quite large (limited by the current mirror ratio, of course), the sink current that can be conducted by transistor 9 is the current source. Limited to the value i _BIAS conducted by 11. As such, the output impedance for a sinking state is typically a current i that is acceptable in terms of power dissipation.
Limited by the value of _BIAS .

[0008]

SUMMARY OF THE INVENTION The present invention solves the above-mentioned drawbacks of the prior art and provides a reference voltage circuit capable of supplying a relatively large current while avoiding the generation of an offset voltage. With the goal.

Another object of the invention is to provide such a circuit having improved transient response while maintaining a stable output reference voltage.

Yet another object of the invention is to provide such a circuit with improved switching performance.

Yet another object of the present invention is to provide such a relatively low output impedance so that modulation of the reference voltage is minimized when significant supply and sink currents are required. It is to provide a circuit.

Yet another object of the invention is to provide such a circuit in which the output impedance is not limited by the bias current source when large sink currents are required.

[0013]

The present invention can be implemented in an integrated circuit as an output driver system, where the voltage applied to the gate of the pull-up device is less than the minimum V _OH operating window. Although it is above, it is set to a voltage below the circuit power supply. The system includes circuitry to generate an appropriate gate voltage to the pullup device based on the adjusted voltage. The regulated voltage is generated by a reference voltage and voltage regulator circuit, in which case the regulated voltage is shifted by a threshold voltage and the output driver is an N-channel device with its substrate node back biased. To be possible. This regulated voltage acts as a bias voltage in the output buffer, thus limiting the output voltage of the output buffer applied to the gate of the N-channel pull-up device.

According to another embodiment of the present invention, a reference voltage
Circuitry is provided to assist in sinking current from the output of the voltage regulator circuit. This circuit provides such additional sinking current capability without the need for a bias current source in the reference voltage regulator circuit to conduct the additional current. ..
As a result, the output impedance of the reference voltage regulator circuit is reduced on the sink side without increasing the power dissipated by the circuit.

The present invention can be applied to other circuits that require a stable reference voltage other than the output driver.

[0016]

DETAILED DESCRIPTION OF THE INVENTION As will be apparent from the following description, the present invention can be implemented in many types of integrated circuits that produce digital output signals. Examples of such integrated circuits are, for example, read only, programmable (writeable) read only, random access (static or dynamic).
And FIFO type memory circuits, timer circuits, microprocessors, microcomputers, microcontrollers, and other general purpose or programmable (writable) type logic circuits. For convenience of description, the preferred embodiment of the present invention describes an example of a memory integrated circuit.
This is because memory circuits are often used to provide output data to integrated circuits (eg microprocessors) that have lower power supply voltages.

FIG. 1 shows a block diagram of a read / write memory 10 in which the preferred embodiment of the present invention is implemented. The memory 10 has a plurality of memory cells arranged in the form of a memory array 16. Generally, memory 1
0 operates to receive an M-bit address and to output an amount of N-bit data in synchronization with the system clock (shown as "CLK"). The integers M and N are
It is selected by the designer according to the desired memory density and data path dimensions. The memory cell selected in the memory array 16 is the address register 12
It is accessed by the operations of the control circuit 14 and the address decoder 17. The data terminal 28 in this embodiment is a common input / output terminal, but it should be understood, of course, that separate dedicated input and output terminals could be provided in the memory 10 instead. . Data is read from selected memory cells in memory array 16 via read circuit 19 (which may include sense amplifiers, buffer circuits, etc., as known in the art), output buffer 21, and output driver 20. ,vice versa,
Data is written to the selected memory cell in the memory array 16 via the input driver 18 and the write circuit 17.

The address register 12 has an integer number M of address inputs A _{1 to} A _M. As known in the memory art, address inputs allow an M-bit address to be applied to memory 10 and stored in address register 12. In this embodiment, the memory 10
Are synchronous and, as such, the address value at address input A is clocked into address register 12 via CLK, where CLK is the timing
It is passed from the control circuit 14 to the address register 12.
When the address is stored, address register 12 causes the address to be applied to memory array 16 via address decoder 17 in the normal manner. The timing and control circuit 14 receives a generalized set of control inputs (shown as "CTRL"), which are well known in the art such as read / write enable, output enable, burst mode enable, chip enable, and the like. It is intended to represent various control and / or timing signals.

In this embodiment, memory 10 receives power from power supply terminal V _CC and has a reference voltage terminal GND. In accordance with the preferred embodiment of the present invention, memory 10 provides output data at data terminal 28 for reception by another integrated circuit driven by a power supply voltage lower than that applied to terminal V _{CC of} memory 10. To do. For example, the power supply voltage applied to terminal V _{CC of} memory 10 is nominally 5V (relative to the voltage at terminal GND), while the integrated circuit receiving the data provided by memory 10 at terminal 28 is nominally 3.3V
It is possible to have a power supply voltage of To allow for this condition, the maximum voltage driven by the output driver 20 of the memory 10 at the data terminal 28 is set to this lower power supply voltage or to avoid damage to downstream integrated circuits. It must be in its vicinity (ie 3.3V or its vicinity). As described in more detail below, the preferred embodiment of the present invention is intended to provide such a limitation on the maximum output high level voltage driven by the output driver 20 of memory 10.

Memory array 16 is a standard memory storage array sized and configured according to the desired density and architecture. Generally, array 16
Receives a decoded address signal from the address decoder 17, and in response thereto, one or more desired memory cells are accessed. As mentioned above, one of the control signals selects whether a read or a write operation should be performed. In the write operation, the input data supplied to the data terminal 28 and communicated via the input buffer 18 is supplied to the memory cell selected by the write circuit 23. On the contrary, in the read operation, the data stored in the selected memory cell is supplied to the output buffer 21 by the read circuit 19. The output buffer 21 then supplies the control signal to the output driver 20 and the digital output data signal at the data terminal 28. In any case, the internal operation of the memory 10 is controlled by the timing / control circuit 14 as is conventionally done.

In accordance with the preferred embodiment of the present invention, the memory 10
Further has an output buffer bias circuit 22. The output buffer bias circuit 22 uses the line VOHR.
Generate a bias voltage on EF, which is output buffer 2
The control signal supplied to unit 1, and thus output buffer 21, limits the maximum output voltage driven by output driver 20 on data terminal 28. FIG.
Output buffer bias circuit 2 in accordance with a preferred embodiment of the present invention, as shown in FIG.
2 is controlled by the timing / control circuit 14 according to the timing of the memory access cycle.

Referring now to FIG. 2, the output buffer bias circuit 22 and the cooperative relationship thereof with the output buffer 21 and output driver 20 according to the preferred embodiment of the present invention will be described in more detail. As shown in FIG. 2, the output buffer bias circuit 22 has a reference voltage and regulator 24, which regulates the voltage VO at its output.
Generate HREF. Output buffer bias circuit 22
Further has a bias current source 26, which
As will be described in more detail below, the bias current source 26 is controlled by the clock signal generated on line C50 by the timing and control circuit 14 to cause the bias current source 26 to
Reference voltage / regulator 24 for generating voltage on HREF
Generate a bias current i _BIAS used by Furthermore, according to this embodiment of the invention, the reference voltage and regulator 2
4 receives the offset compensating current i _NULL from the offset compensating current source 28. Output buffer bias circuit 22
Further comprises a V _t shift circuit 30, which serves to set the voltage VOHREF. The detailed configuration and operation of the output buffer bias circuit 22 and the blocks forming the output buffer bias circuit 22 will be described in more detail below.

As shown in FIG. 2, the output buffer bias circuit 22 further includes a sink current path circuit 2 in accordance with another embodiment of the present invention described in further detail below.
Have five. The sink current path circuit 25 is connected to the ground and line V at the output end of the output buffer bias circuit 22.
Providing an additional current path to OHREF lowers the output impedance of the output buffer bias circuit 22 when significant sink current is required to be conducted. As such, the voltage overshoot on line VOHREF is minimized as a result of sink current conditions such as switching of the output driver. This reduction in output impedance causes the current i that needs to be conducted by the bias current source 26.
It has been obtained without increasing the value of _BIAS and thus without increasing the DC power dissipation of the output buffer bias circuit 22.

The voltage VOHREF is supplied to each of the output buffers 21. As such, the output buffer bias circuit 22 acts on multiple ones of the output buffers 21 and in many cases a single output buffer bias circuit 22 will output depending on the number of output buffers 21. It may be sufficient to control all of the buffer 21. Each output buffer 21 receives complementary data inputs DATA, DATA * produced by the read circuit 19 (FIG. 1).
reference). For example, output buffer 21 _j receives complementary data inputs DATA _j , DATA _j * (“*” represents a logical complement). Each output buffer 21 sends a control signal to the corresponding output driver 20 (P for output buffer 21 _j
(Denoted as U and PD). Each output driver 20 drives a corresponding data terminal 28. As shown in FIG. 1, the data terminal is a common input / output terminal, but in order to simplify the drawing, the input side (that is, the data input buffer etc.) is not shown in FIG.

Each output buffer 21 in this embodiment of the invention is implemented as an N-channel push-pull driver. With particular reference to the output driver 20 _j shown in detail in FIG. 2 (it should be understood that the other output drivers 20 are similarly configured), the N-channel pull-up transistor 32 has its drain connected to V Biased to _CC and its source connected to data terminal 28 _j , and N-channel pull-down transistor 34 has its drain connected to data terminal 28 _j and its source biased to ground. There is. Output driver 20 further preferably includes an electrostatic protection device (not shown), as is known in the art. The gates of the transistors 32 and 34 receive the control signals PU and PD from the output buffer 21, respectively. As will be appreciated by those skilled in the art, since V _CC (eg, nominally 5V) biases the drain of pull-up transistor 32, the voltage on line PU applied to the gate of transistor 32 provides a logic one. The maximum voltage (V _OH) above which transistor 32 drives data terminal 28 _j.
It must be properly controlled to ensure that the maximum (called maximum) does not exceed a limit (eg 3.3V).
The manner in which this limit is achieved in accordance with the preferred embodiment of the present invention is described below.

As shown in FIG. 2, the substrate node of N-channel pull-up transistor 32 is preferably biased to ground rather than its source at data terminal 28 _j . As will be appreciated by those skilled in the art, this N
The substrate node bias for the channel pull-up transistor 32 is suitable for avoiding the occurrence of latch-up. However, as will be appreciated, this bias condition for transistor 32 effectively increases its threshold voltage, making it more difficult to limit the V _OH maximum driven by output driver 20. This difficulty is due to the higher voltage that line PU must be driven to turn on transistor 32. As will be described below, the preferred embodiment of the present invention provides this difficulty in a manner that allows the substrate node of transistor 32 to be back biased (ie, biased to a voltage other than its source voltage). Is dealing with.

[0027] a detailed description of the construction of output buffer 21 _j as shown in the output buffer Figure 2. It should be understood that the other output buffers 21 are similarly configured. Output buffer 2
1 _j receives the data input lines DATA _j and DATA _j * at the input ends of the NAND function units 40 and 42, respectively.
The output enable line OUTEN is also the NAND function unit 4
It is received at each of the 0, 42 inputs and performs the output enable function as described below.

The output of the NAND function section is applied to the gates of the P-channel transistor 36 and the N-channel transistor 38. P-channel transistor 36 has its source biased to the voltage VOHREF generated by output buffer bias circuit 22 and its drain connected to line PU. N-channel transistor 38 has its drain connected to line PU and its source biased to ground. Therefore, the transistors 36 and 38 are connected to the NAND function unit 40.
Line PU on the logical complement of the logical signal supplied by
To form a conventional CMOS inverter for driving the. However, the high voltage at which line PU is driven by transistor 36 is limited to the voltage VOHREF generated by output buffer bias circuit 22. Since the line PU is supplied to the gate of the N-channel pull-up transistor 32 in the output driver 20 _j , the voltage VOHREF is applied to the pull-up transistor 32.
Control the maximum drive, and thus the voltage at which the data terminal 28 _j is driven.

On the low side, the output of NAND function 42 is applied to the input of inverter 43 (in this case biased by V _CC ). Inverter 4
The output of 3 drives line PD, which is applied to the gate of N-channel pull-down transistor 34.

In operation, when the output enable line OUTEN is at a high logic level, the states of the NAND function parts 40 and 42 are the same as the data input lines DATA _j and DA.
They are controlled by the state of TA _j * and are logical complements of each other (because of the data input lines DATA _j , DA
TA _j * are logical complements of each other). Therefore,
A high logic level on line DATA _j results in a low logic level at the output of NAND function 40, which turns on transistor 36 and thus voltage VOHRE.
F is applied to the gate of transistor 32 via line PU, driving data terminal 28 _j to a high logic level (limited by the voltage on VOHREF as previously described). The output of NAND function 42 under this condition is high (data line DATA _j * is low) which, after being inverted by inverter 43, causes output driver 2
Turn off transistor 34 at 0 _j . In the other data state, the output of NAND function 40 is high (data line DATA _j is low) turning transistor 38 on, pulling line PU low and turning transistor 32 off. NAND
The output of function 42 is low, which causes inverter 43 to drive line PD high and turn on transistor 34, pulling data terminal 28 _j low. When the output enable line OUTEN is at a low logic level, the outputs of the NAND functions 40, 42 are forced high regardless of the data state applied by the input lines DATA _j , DATA _j *. As a result, transistors 32 and 34 are both turned off, maintaining data terminal 28 _j in a high impedance state.

As mentioned above, the voltage on line VOHREF in this embodiment of the invention determines the drive applied to N-channel pull-up transistor 32 in output driver 20. Therefore, according to this embodiment of the present invention, the voltage V
The configuration of the output buffer 21 when supplying OHREF is particularly beneficial. Because it is implemented with a minimum number of transistors and can be switched quickly to make fast transitions at the data terminal 28. Furthermore, according to this embodiment of the invention, no series device is required in the output driver 20 to limit the V _OH maximum. Such series devices inevitably slow the switching speed of the output driver 20 and make it susceptible to electrostatic discharge and latch-up. Furthermore, according to this embodiment of the invention, no gate drive bootstrap for N-channel transistor 32 is required, thus avoiding being affected by voltage slew (distortion) and bumps (sudden changes). .

The appropriate voltage VOHREF is provided so that memory 10 in this embodiment of the present invention is capable of driving a logic high level to a safe maximum level for receipt by an integrated circuit having a lower power supply voltage. Regarding the configuration of the output buffer bias circuit 22 for
Each of the circuit functions of the output buffer bias circuit 22 shown in FIG. 2 will be described in detail.

Reference Voltage Regulator with V _t Shift Referring now to FIG. 3, the configuration and operation of reference voltage regulator 24 will be described in cooperation with other components of output buffer bias circuit 22. Based on this, a detailed explanation will be given.

As shown in FIG. 3, the reference voltage / regulator 24
Is configured in the form of a current mirror. P-channel transistors 44 and 46 each have their sources biased to V _CC and their gates are connected together. In the reference branch of this current mirror,
The drain of transistor 44 is connected to its gate and to the drain of N-channel transistor 48. The gate of the N-channel transistor 48 is V
It is connected to a voltage divider consisting of resistors 47 and 49 connected in series between _CC and ground, where the gate of transistor 48 is at the desired percentage of the V _CC supply voltage (eg, 60). %) Is connected to a point between resistors 47 and 49. On the other hand, each branch of the resistor divider
It can consist of a series of resistors that are initially shorted by a fuse, thus opening the selected fuse allows programming of the voltage applied to the gate of transistor 48. It is possible.

The source of transistor 48 is connected to bias current source 26. In the mirror branch of this current mirror, the drain of the transistor 46 is connected to the N-channel transistor 5 at the output node VOHREF.
Connected to the drain of 0. The gate of the transistor 50 is in a manner described in more detail below, are coupled to node VOHREF via V _t shift circuit 30. The source of N-channel transistor 50 is connected to the source of transistor 48 in the reference branch and thus to bias current source 26. As mentioned above, bias current source 26 conducts current i _BIAS , which is the sum of the currents in the reference and mirror branches of the current mirror of reference voltage regulator 24 (ie, through transistors 48 and 50). Is the sum of the currents). The current i _BIAS is mainly
Generated by N-channel transistor 52, the drain of which is connected to the sources of transistors 48 and 50, whose sources are biased to ground, and whose gate is controlled by reference bias circuit 54. As will be described in more detail below, according to a preferred embodiment of the present invention, there is a certain time in the memory access cycle to optimize the output impedance of the reference voltage and regulator 24 for different portions of the memory access cycle. To control to reduce the current i _BIAS at (under control of clock signal C50)
A dynamic bias circuit 60 is provided.

The V _t shift circuit 30 has a voltage VOHREF.
Is applied to the gate of the N-channel pull-up transistor 32 in the output driver 21 (output buffer 2
(Through 1), the voltage VOHREF
N in the mirror branch of the reference voltage regulator 24 in this embodiment of the invention to ensure that is shifted upwards by the N-channel threshold voltage.
It supplies the bias of the gate of the channel transistor 50. The manner in which this shift is generated is described below in connection with the operation of the reference voltage and regulator 24.

The operation of the reference voltage / regulator 24 will be described in detail at the point in the memory cycle at which output data should be supplied to the data terminal 28. The bias reference circuit 54 supplies a bias voltage to the gate of the N-channel transistor 52, sets the value of i _BIAS which is conducted through the current mirror, and sets the dynamic bias circuit 6
0 is effectively off at this point. The divided voltage generated by resistors 47 and 49 supplied as a reference voltage to the gate of N-channel transistor 48 determines the range in which transistor 48 conducts, and thus the bias condition at the drain of P-channel transistor 44. To do. The current conducted by transistor 44 is mirrored by transistor 46 in the mirror branch and is therefore a multiple of the current conducted by transistor 44 (this point is discussed below).

The voltage VOHREF at the drains of transistors 46 and 50 is determined by the voltage at the drains of transistors 44 and 48, by the relative size of the transistors in the circuit, and by the effect of V _t shift circuit 30. As is known in the art of current mirror circuits, the gate voltage of transistor 50 is
Considering the differential amplifier effect of the reference voltage / regulator 24,
Feedback of the voltage on line VOHREF to the gate of transistor 50 causes transistor 48 to
Tends to match the voltage at the gate of. However, the V _t shift circuit 30 has its gate connected to VOHRE.
A transistor 56 connected to its drain at F and its source to the gate of transistor 50 and connected in diode form,
Therefore, the threshold voltage drop is due to the line VOHRE
It exists between F and the gate of the transistor 50.
Transistor 56 is configured similarly to one of N-channel pull-up transistors 32 in output driver 20, and in particular has the same or similar gate length and the same substrate node bias (eg, ground). have. The N-channel transistor 58 is
Its drain is connected to the source of transistor 56, and its gate is controlled by bias reference circuit 54 to ensure proper current conduction through transistor 56, thus ensuring accurate threshold across transistor 56. There is a voltage drop.

As a result of the V _t shift circuit 30, the voltage on line VOHREF closely matches the threshold voltage value of the N-channel pull-up transistor 32 of the output driver 20 from the reference voltage at the gate of transistor 48. Only boosted. This additional threshold voltage shift is due to the voltage VOHREF
This is necessary considering that the voltage is applied to the gate of the N-channel pull-up transistor 32 in FIG. The V _t shift is performed by the circuit 30 in a manner that does not increase the output impedance of the reference voltage / regulator 24, and in particular the variation of the voltage VOHREF generated by switching the output buffer 21 occurs. In that case, it does not increase the impedance to sinking current through transistor 50. The offset voltage introduced into the reference and regulator 24 by providing the circuit 30 is minimal, and merely requires two additional transistors 56, 58 without adding an entire stage. Absent.

In order to control the logic level high drive of the output driver 20 in a manner different from that described above with respect to the preferred approach of controlling the supply voltage of the pull-up transistor 36 in the output buffer 21,
Of course, it is possible to apply the voltage generated on the line VOHREF by the regulator 24.
For example, the voltage generated on line VOHREF can be applied directly to the gate of a transistor in series with the pull-up transistor in output driver 20, or, in another embodiment, line VOHREF.
The voltage generated on OHREF can be applied to the gate of a transistor in series with the pull-up transistor in output buffer 21, and in each of these alternative embodiments the reference voltage on line VOHREF is the output. Limit the drive applied to the terminals. However, in these variations, the absolute level of the reference voltage on line VOHREF may need to be shifted from that used in the foregoing, as will be appreciated by those skilled in the art.

It is desirable that the offset compensating current source reference voltage / regulator 24 has a very low output impedance, and thus the line VO.
It is desirable to be able to supply and sink a significant amount of current to line VOHREF without significantly changing the voltage on HREF.
As described above, the voltage on line VOHREF is used to control the maximum output high level voltage V _OH maximum so as not to damage the integrated circuit receiving the output logic signals at data terminals 28 while supplying the maximum output drive Therefore, it is important that the voltage on line VOHREF stays steady near the regulated level.

Therefore, in the reference voltage / regulator 24, the driving capability, and hence the transistor size of the transistors 46 and 50 (that is, the ratio of the channel width to the channel length, that is, W / L) may be extremely large. desirable. This large size for transistors 46 and 50, via the voltage reference and regulator 24 is rapidly current (from V _CC through transistor 46 to line VOHREF) supplies or current sink viz draws (transistors 50, 52 line VOHREF to ground). For example, the W / L of transistor 46 can be on the order of 1200 and the W / L of transistor 50 can be
Can be on the order of 600, and the W / L of transistor 48 can be on the order of 300. Further, the W / L of the transistor 46 is the transistor 4
It is desirable to have a W / L greater than 4, so that an affordable mirror ratio can be obtained in that case, thus increasing the supply current available on line VOHREF. Furthermore, because of the high gain, the transistor 48
Is preferably significantly larger than the W / L of the transistor 44. In the above-described embodiment, the W / L of the transistor 44 is about 60, and in that case, the mirror ratio of the reference voltage / regulator 24 is about 20. The maximum supply current i _sourcemax is determined by the following equation.

I _sourcemax = i _BIAS {(W / L) ₄₆ / (W / L) ₄₄ } In the above embodiment, the maximum supply current i _sourcemax
Is about 20 × i _BIAS . The maximum sink current of the reference voltage regulator 24 is equal to i _BIAS controlled by the bias current source 26. In this embodiment of the invention, the supply current is the more important parameter for this embodiment of the invention. Because it controls the turn-on of the pull-up transistor 32 in the output driver 21.

However, since the currents flowing through the reference branch and the mirror branch of the reference voltage / regulator 24 are not equal to each other, on the one hand the transistors 44,
An offset voltage may occur between the node at the drain of 48 and, on the other hand, the node at the drains of transistors 46 and 50. This offset voltage can be on the order of 300-400 mV and increases with i _BIAS .

Further, since the W / L of transistor 48 is substantially greater than the W / L of transistor 44 and transistor 44 is in the diode configuration (ie, the gate is connected to the drain), transistor 44 is: It is not possible to quickly pull the voltage at the drain of transistor 48 (and thus the gates of transistors 44 and 46) high if needed. For example, if more than one of the output drivers 21 simultaneously switch on their respective pull-up transistors 32, a reference voltage / regulator to maintain the voltage on line VOHREF at an appropriate level. A considerable supply current from 24 is required. This supply current first tends to pull down the voltage on line VOHREF, which pulls down the voltage at the drains of transistors 44, 48 in the reference branch of reference voltage regulator 24. Because transistor 48 needs to temporarily supply most of the current i _BULK required by current source 26, as virtually all of the current conducted by transistor 46 is directed to line VOHREF. Because it is done. However, due to its relatively small size (for high Miller ratios), transistor 44 is unable by itself to quickly pull up the voltage at its drain.
If this voltage remains low, then the voltage VOHREF will overshoot its steady state voltage once the transient demand on the supply current has passed. This is because transistors 44 and 46 are strongly turned on by the low voltage on their gates. As mentioned above, the overshoot of the voltage VOHREF can damage downstream integrated circuits with lower power supply voltages.

Therefore, in accordance with the preferred embodiment of the present invention, an offset compensating current source 28 is provided to provide a current i _NULL into the reference voltage and regulator 24 at the drains of transistors 44 and 48. . The size of the bias current source transistor 52 is such that an additional current i is supplied across the current mirror into the reference branch of the reference voltage regulator 24.
Must be sufficient to conduct a _null .
Of course, additional transistors can be provided in parallel with transistor 52 to conduct this additional current. The current i _NULL is for making the current conducted by the transistor 48 per unit channel width equal to the current conducted by the transistor 50 per unit channel width, and therefore, no offset voltage is generated. And transistor 44
Relieve the load on transistor 48 above and drain the transistors 44 and 48, and thus transistor 4
The voltage at the 4,46 gates allows it to be pulled high quickly if needed. Therefore,
Overshoot of the voltage on line VOHREF is prevented.

Next, the configuration of the offset compensating current source 28 will be described in detail with reference to FIG. In this particular embodiment of the invention, the offset compensating current source 2
8 is controlled by a bias reference circuit 54 in the bias current source 26 to minimize the number of transistors required to implement. Of course, the offset compensating current source can have its own bias reference network if desired.

Bias reference circuit 54 includes a P-channel transistor 62 whose source is biased to V _CC and whose gate can be generated by a conventional reference voltage circuit and which is another of memory 10. It can be used in place or is preferably biased by a reference voltage PVBIAS generated by a compensating bias voltage reference circuit. The N-channel transistor 64 is connected in the form of a diode, and its gate and drain are connected to the drain of the transistor 64. The size of the transistors 62 and 64 is the voltage PV specified by the P-channel transistor 62.
It has been selected to ensure that it stays saturated with BIAS. For example, the voltage PVBIAS is about 2
Transistor 6 with a W / L ratio of about 15 for V
2 and 64 keep transistor 62 in saturation when V _CC is nominally 5V. Transistors 62, 64
The common node at the drain of supplies the reference voltage ISVR, which is applied to the gate of transistor 52 in bias current source 26 and offset compensating current source 28.

The operation of the bias reference circuit 54 should be as stable as possible because of the large current conducted in the reference voltage / regulator 24 and the large expected variations in processing parameters and supply voltage with respect to temperature. Is desirable. The configuration of the bias reference circuit 54 shown in FIG. 4 provides such stability. In the example described above, simulation results show that the bias reference circuit 54 is used to set the gate voltage at node ISVR with respect to variations in temperature, processing parameters and power supply voltage, and by transistor 52 in bias current source 26. The ratio of the maximum current to the minimum current conducted is about 1.17.

The offset compensating current source 28 according to this embodiment of the invention is realized by a current mirror circuit, in which case the reference branch comprises a P-channel transistor 66 and an N-channel transistor 68. . The sources of the transistors 66 and 68 are V
Biased to _CC and ground, and their drains are commonly connected. The gate of N-channel transistor 68 receives the reference voltage at node ISVR from bias reference circuit 54, and the gate of P-channel transistor 66 is connected to the common drain of transistors 66 and 68, and in a typical current mirror fashion,
It is connected to the gate of the P-channel transistor 69 in the mirror branch. Transistor 69 has its source biased to V _CC , so its drain current supplies current i _NULL . Of course, the transistors 66 and 69
The relative size of determines the mirror ratio and thus the current i
Determine _NULL . The mirror ratio is typically on the order of 5 to generate a current i _NULL of the order of 2.5 mA. As mentioned above, sufficient current capability must be provided to transistor 52 to conduct this additional current i _NULL . Preferably, an N-channel transistor is provided in parallel with transistor 52, the gate of which is controlled by line ISVR and a mirror circuit of transistors 66, 68, 69 for conducting additional current i _NULL in a matched manner. Have dimensions that match those of

Next, referring to FIGS. 5 and 6, the reference voltage
Offset compensating current source 28 for operation of the regulator 24
The effect of will be explained based on the simulation. FIG. 5 shows the operation of the reference voltage / regulator 24 when the current i _NULL is zero, that is, as if the offset compensating current source 28 does not exist. Figure 5
Is the voltage VOH at the output terminal of the reference voltage / regulator 24.
REF, the voltage V _{44 at} the common drain node of transistors 44 and 48, and the output voltage DQ at one of the data terminals 28 are shown. Time t ₀ represents the steady state conditions for all data terminals 28 when driving low output voltages. For example, in steady state, the voltage VOHREF is preferably 3.3.
V (lower power supply voltage of the integrated circuit receiving the output data from the memory 10) + N-channel threshold voltage (considering that the pull-up transistor 32 in the output driver 20 is an N-channel device).

At time t ₁ , the data terminals 28 begin switching to the new data state, and in this example, the worst condition is that all (eg, 18) data terminals 28 are at a low logic level to a high logic level. This is the case when switching to the level. As shown in FIG. 5, when this switching begins, as can be represented by the voltage DQ starting to rise, a significant supply current is required by the output buffer 21 on the line VOHREF, which pulls it down. As a result, the voltages VOHREF and V ₄₄ drop. The current through transistor 50 is reduced to near zero (all of the current in the mirror branch is needed by output buffer 21), forcing transistor 48 to conduct virtually all of current i _BIAS . Therefore, the voltage V ₄₄ drops at this point. The additional conduction by transistor 48 causes the voltage at node V ₄₄ to drop. Time t ₂ represents the end of the output transient, so the demand for supply current begins to decrease,
The line VOHRE is operated by the operation of the reference voltage / regulator 24.
Allows the voltage on F to rise. However, as noted above, due to the small size and diode configuration of transistor 44 required to have a mirror ratio large enough to supply the supply current required by output buffer 21. , The voltage at node V ₄₄ remains low for quite some time and does not begin to rise until time t ₃ . As long as the voltage at node V ₄₄ stays below its steady state value, which keeps transistors 44 and 46 strongly turned on, the voltage at line VOHREF is allowed to rise, in fact Beyond and rise by a considerable margin (V _OS ). The rise of VOHREF exceeding this desired value is reflected on the data terminal 28 via the output buffer 21 and the output driver 20, and actually causes damage to the low power supply integrated circuit connected to the data terminal 28. It is reflected to the extent that it causes it.

Referring now to FIG. 6, the operation of the reference voltage and regulator 24 for a current i _NULL of 2.5 mA is based on a simulation of the same conditions as shown in FIG. Are shown as having the same time axis as in. As described above, the time t ₁
The switching occurring at causes VOHREF and V ₄₄ to drop. However, transistor 4
An additional current i _NULL applied to the common drain node of 4,46 helps to charge this node, and consequently
The time t _{3 at} which the voltage V ₄₄ starts to rise occurs at a very early time after the first switching time t ₁ . In this case, the voltage V ₄₄ begins to rise so rapidly that the voltage VOHREF will not be as large and overshoot the steady state value as in the case of FIG. 5 where i _NULL = 0. Absent. Therefore, damage to the low power integrated circuit connected to the data terminal 28 is avoided.

Dynamic Control of Bias Current As is apparent from the above description, the output of the reference voltage / regulator 24 during the period when the output buffer 21 and the output driver 20 switch the state of the data terminal 28. It is desirable that the impedance be as low as possible. Such a low output impedance allows the reference voltage and regulator 24 to provide significant supply and sink currents without causing significant fluctuations in the voltage VOHREF. However, such a low output impedance results in a significant amount of DC current through the reference and regulator 24, and thus a significant steady state power dissipation, with a corresponding increase in temperature and reliability. It creates a sag and load on the system power supply, which are all undesirable.

Next, with reference to FIG. 7, the configuration and operation of the dynamic bias circuit 60 for controlling the bias current i _BIAS in the memory access cycle will be described in detail. The dynamic bias circuit 60 is provided as an optional function in the reference voltage / regulator 24 for the purpose of reducing the steady state current. As shown in FIG. 7, the dynamic bias circuit 60 is
It receives clock signal C50 and applies it through inverter 71 to the gate of N-channel transistor 72. Transistor 72 has its drain connected to the output of bias reference circuit 54 and node ISVR at the gate of current source transistor 52. The source of transistor 72 is connected to the drain of N-channel transistor 74, the gate of transistor 74 is connected to node ISVR and its source is connected to ground.

To explain the operation, the clock signal C
As long as 50 remains high, transistor 72 is off, and dynamic bias circuit 60 does not affect the gate bias of transistor 52 and does affect the value of the current i _BIAS that is conducted. Never give. When clock signal C50 is low, transistor 72 is turned on and the voltage at the gate of transistor 52 reduces the current that transistors 72 and 74 pull node ISVR toward ground and in doing so. So it will be reduced.

The range in which the gate bias of the transistor 52 is reduced by the dynamic bias circuit 60 is
As will be appreciated by those skilled in the art, bias reference circuit 54
The dimensions of transistor 74 in relation to the dimensions of transistor 64 in FIG. This sizing can be readily determined given that the gate-to-source voltage of transistor 74 is the same as the gate-to-source voltage of transistor 64 in bias reference circuit 54. However, the drain-to-source voltage of transistor 74 is typically much smaller than the drain-to-source voltage of transistor 64 by the amount of the drain-to-source voltage of transistor 72 when turned on, which is on the order of 100 mV for example. Transistors 64 and 74
, Both are in saturation, their drain currents are not significantly affected by their drain-to-source voltages, and so transistors 64, 7
4 can be considered to be in parallel with each other when transistor 72 is turned on. Since the current in transistor 52 mirrors the current in transistor 64 (which is in parallel with transistor 74 when transistor 72 is on), clock signal C50
Controls the current i _BIAS , which effectively changes the current mirror ratio of transistor 64 to transistor 52.

For example, if the current i _BIAS is to be reduced to 50% of its full value except during output switching, then the channel widths and lengths of transistors 64 and 52 are as in this example. If they are the same, the channel width and the channel length of the transistors 64 and 74 are the same. When transistor 72 is turned off, current i _BIAS equals current i ₆₄ through transistor 64 in bias reference circuit 54. When transistor 72 is turned on (clock signal C50 is low), transistor 6 is turned on as described above.
4, 74 are effectively in parallel with each other, and in this example, the channel width of the transistor 52 is effectively 2
It has a double channel width. Therefore, the current mirror ratio is 1/2 as shown in the following equation.

W ₅₂ / (W ₆₄ + W ₇₄ ) = 1/2 Note that W ₅₂ , W ₆₄ and W ₇₄ are transistors ₅₂ , ₆₄ and _74, respectively.
Channel width (assuming the channel lengths are equal). The sum of W ₆₄ + W ₇₄ is the effective channel width of transistors 64 and 74 in parallel with each other. Therefore, the current i _BIAS is reduced by 1/2 during the low period of the clock signal C50.

Next, the operation of the dynamic bias circuit 60 and its influence on the bias current i _BIAS in the memory access cycle will be described with reference to FIG. Time t ₀ indicates the condition of memory 10 at the end of the previous cycle in steady state. The data terminal DQ supplies the output data value DATA ₀ from the previous cycle. Since no output switching has occurred,
Clock C50 is low at this time. Therefore, transistor 72 (FIG. 7) is turned on by inverter 71, causing transistor 74 to be in parallel with transistor 64 of bias reference circuit 54, thus reducing the mirror ratio of transistor 52, so that current i _BIAS is half of its maximum value. Becomes This reduces the current i _BIAS drawn by the reference voltage regulator 24 during the time period in the memory access cycle where output switching is not scheduled, and thus during that period, the previous data state (ie, DATA ₀ ) Only is maintained. The output impedance of the reference voltage regulator 24 is relatively high during this period, but the voltage on line VOHREF is maintained at its correct steady state level.

At time t ₁ , a new memory access cycle is initiated by the input clock CLK becoming active, while in a completely static memory, for example, the clock CLK is the address or data input of the memory. It is possible to respond to edge transition detection pulses generated by detecting transitions at the terminals. In response to the leading edge of clock CLK, clock signal C50 is activated after a selected delay that corresponds to a time safely less than the minimum expected read access time of the memory. Clock signal C50 is time t
_When activated at ₂ , transistor 72 is turned off by the operation of inverter 71. Therefore,
The current mirror ratio of transistor 52 has its maximum value (1 in this example ₁ ) before the time when output buffer 21 and output driver 20 start driving data terminal 28 to the new data state (ie, DATA ₁ ). ). After another delay time sufficient to ensure that the new data state DATA ₁ is stable, the clock signal C
50 returns to the low state shown at time t ₃ in FIG. This turns on transistor 72,
i _BIAS is reduced to 50% of its maximum value (in this example), thus reducing the DC current drawn through the reference voltage regulator 24.

Adjustable Bias Current Source Next, a bias current source 26 'according to another embodiment of the present invention will be described in detail with reference to FIG. The bias current source 26 ′ is the dynamic bias circuit 60 described above.
_Provides a multi-level adjustment of the current i _{BIAS to} the reference voltage and regulator 24, which is controllable either by a clock signal or by programming the fuse as in the case.

Bias current source 26 'incorporates current source transistor 52 and bias reference circuit 54 which are connected to reference voltage and regulator 24 as previously described. Furthermore,
Transistor 72, as previously described with reference to FIG.
And 74 are provided to reduce the current i _BIAS to 50% of its previous value when transistor 72 is turned on. However, in this case, the gate of the transistor 72 is controlled by the NAND function unit 73, and the NAND function unit 73 receives the clock signal C50 at one input terminal and the fuse circuit 75 on the node FEN50 * at the other input terminal. Receive the output of.

Fuse circuit 75 provides the programmability of the state of transistor 72 in a permanent manner. Such programmability may be useful at an early stage in the design and manufacture of memory 10 if the optimal value of i _BIAS has not yet been determined. Furthermore,
The value of i _BIAS is programmable in memory 10
Process variations in the manufacture of i _BIAS are desirable when the value of i _BIAS changes so much that it is desirable to be set after an initial test of memory 10. For example, memory 1
If 0 is processed to have a very short channel width, the value of i _BIAS can be reduced, preferably by programming fuse circuit 75 to keep transistor 72 on. Is. In addition, the fuse circuit 75 can be programmed to select the desired output slew rate.

The configuration of fuse circuit 75 can be accomplished in any one of a number of conventional ways. In the embodiment of FIG. 9, simply V _CC and the inverter 77
Has a fuse 76 connected between it and its input, which drives node FEN50 * from its output. Transistors 78 and 79 have their sources /
The drain path is connected between the input end of the inverter 77 and the ground. The gate of the transistor 78 receives the power-on reset signal POR, and the transistor 78 pulls up the input terminal of the inverter 77 to the ground when the memory 10 is powered up. The gate of transistor 78 is node F
It is connected to the output terminal of the inverter 77 at EN50 *. In operation, if fuse 76 remains unchanged, node FEN50 * is held low by the operation of inverter 77. If the fuse 76 is open, the pulse on the line POR will
7 is pulled low, node FEN50 * is driven high, and transistor 78 is turned on to maintain this condition.

To explain the operation, the output terminal of the NAND function section 73 has a clock signal C50 or a node FEN.
A high state is any 50 * low state. Therefore, by not opening the fuse 76,
The node FEN50 * is held low to keep the output of NAND function 70 high and to pull transistor 72
Unconditionally remains on. When the fuse 76 is opened, the clock signal C50 controls the state of the transistor 72 as in the case of FIG. 8 described above.

Of course, so that the state of transistor 72 depends only on the programmed state of fuse circuit 75,
It is also possible to configure the memory 10 without the clock signal C50.

Bias current source 26 'according to this alternative embodiment of the invention also includes transistors 72' and 74 'connected in series between node ISVR and ground in a manner similar to transistors 72 and 74 previously described. Have Similarly, the gate of the transistor 72 has a fuse circuit 75 'via the state of the clock signal C67 and the node FEN67 *.
Is controlled by the NAND function unit 73 '.
However, the size of transistor 74 'has been chosen to be different than the size of transistor 74, so that when transistor 72' is turned on by either clock signal C67 or fuse circuit 75 ',
The current i _BIAS is chosen to be a different percentage of its maximum value. For example, if the channel width of transistor 74 'is half that of transistors 52 and 64 in bias reference circuit 54 (assuming the channel lengths are the same), the effective channel of the parallel combination of transistors 64 and 74'. Width is 1.5 x transistor 5
2 channel width. Therefore, the transistor 74 '
The value of i _{BIAS when} the transistor is turned on is transistor 7
It is 2/3 of its maximum value when 4'turns off.

Of course, if it is desired that a different value of the current i _BIAS be permanently programmed or clocked in at a particular time in the memory cycle, then another transistor of a different size may be used to bias the current source. Two
It can likewise be realized in 6 '. Furthermore, it is possible, for example, to turn on both transistors 72, 72 'simultaneously to further reduce the current i _BIAS . Other combinations of reducing current will be apparent to those skilled in the art.

According to another embodiment of the present invention, the value of the bias current i _BIAS depends on the processing parameters as determined by electrical tests, or at a particular design time at a particular time during the memory cycle. On the other hand, it is possible to optimize each memory circuit. This optimization is an optimization of the balance between the maximum supply and sink currents and the minimum output impedance to the reference voltage regulator 24 on the one hand and the current carried by the reference voltage regulator 24 on the other hand. It is possible to do. Furthermore, it is possible to select the desired output slew rate in this optimization.

Additional Sink Current Path Circuits Referring now to FIGS. 12 and 13, another aspect of the present invention further reduces the sink current output impedance of the output buffer bias circuit 22 without increasing DC power dissipation. Examples will be described in detail. In each of the alternative embodiments of FIGS. 12 and 13, circuitry is provided to conduct significant current when the load on line VOHREF requires the output buffer bias circuit 22 to sink significant current. .

As is apparent from the above description, the DC power dissipation of the reference voltage and regulator circuit 24 is dominated by the value of the current i _BIAS conducted by the bias current source 26. The sink current capability of the reference voltage and regulator circuit 24 is also limited to this bias current i _BIAS . Therefore, circuit designers must weigh the tradeoff between sink current capability and DC power dissipation. However, each of the embodiments described below with respect to FIGS.
It provides additional sink current capability without the need to increase the value of the current i _BIAS and thus without increasing the DC power dissipation of the output buffer bias circuit 22.

Referring initially to FIG. 12, an output buffer bias circuit 22 constructed in the manner described above with respect to FIG. 3 is coupled with a sink current path circuit 25 constructed according to a first alternative embodiment of the present invention. Is shown. The sink current path circuit 25 has a P-channel sink transistor 100, the source of which is the line VOHR.
It is connected to EF and its drain is connected to ground. The gate of the sink transistor 100 is controlled by the drains of the P-channel transistor 102 and the N-channel transistor 104,
The source of 2 is biased to V _CC and the source of transistor 104 is grounded. P-channel transistor 102 acts as a load on transistor 104 because its gate is biased on-state and, yes. In the embodiment of FIG. 12,
The gate of the P-channel transistor 102 has a reference voltage
It connects to the drain of the current source transistor 52 in regulator circuit 24 (and thus the source of transistors 48 and 50). As such, transistor 102 remains substantially on. On the other hand, the transistor 10
The gate of 2 can be biased to ground so that transistor 102 acts as a substantially linear load device to transistor 104. In this embodiment of the invention, the gate of transistor 104 is the gate of transistor 44 in reference voltage and regulator circuit 24.
And 46 and receives the voltage V ₄₄ .
Therefore, transistor 104 turns on when the voltage V ₄₄ rises.

The reference voltage described above with reference to FIGS.
The operation of regulator circuit 24 deals with switching output terminal 28 from a low logic level to a high logic level,
In that case, the reference voltage and regulator circuit 24 was required to supply a significant current to the output driver 20 via the output buffer 21. The worst case for this condition is, of course, when all output drivers 20 switch in that direction. Sink current path circuit 2 of FIG.
5 are oriented to provide a sink current to the output buffer 21, which causes many or all output drivers 20 to switch their respective output terminals 28 at high frequency from a high logic level to a low logic level. This may occur if it should be done (i.e., if the reference voltage and regulator circuit 24 is still required to sink current while still supplying the current in the previous cycle).
The sink current path circuit 25 is described above with respect to FIGS. 5 and 6 when the voltage on line VOHREF overshoots its desired level on the reference voltage and regulator circuit 24 which supplies current to the output buffer 21. Acts to limit overshoot at.

When the reference voltage and regulator circuit 24 is to sink current, the voltage V _{44 at} the gates of transistors 44 and 46 (and transistor 104 in this embodiment) rises. This is because the sink current through transistor 50 actually rises to current i _BIAS . As the voltage V ₄₄ rises, transistor 104 turns on more fully, which pulls the voltage at the gate of transistor 100 towards ground, turning transistor 104 on. When the transistor 104 turns on, the voltage VOHRE
An additional current path from F to ground is provided, which helps pull the line VOHREF from the overshoot condition to its desired level in a timely manner. Therefore, the output impedance of the reference voltage and regulator circuit 24 is reduced by the sink current path circuit 25 according to this embodiment of the invention.

When the voltage on line VOHREF returns to its desired level, voltage V ₄₄ also returns to its steady state value. In this condition, transistor 104 becomes less conductive, so the gate of transistor 100 is biased non-conductive by load transistor 102.

Next, the sink current path circuit 25 'according to another modification of the present invention will be described in detail with reference to FIG. Reference voltage / regulator circuit 24 in FIG.
The configuration and operation of are similar to those described above.

The sink current path circuit 25 'according to this embodiment of the present invention is based on a current mirror and has the same configuration as the reference voltage / regulator circuit 24. In this embodiment of the invention, sink current path circuit 25 'comprises P-channel transistor 110, its source is connected to line VOHREF, and its drain is connected to ground, and thus it is otherwise To provide a sink current path for the. The gate of transistor 110 is biased by N-channel transistors 112 and 114 and their source / drain paths are connected in series between V _CC and ground. The gate of the transistor 110 is the drain of the transistor 114 and the transistor 11
It connects to 2 sources. The gate of the transistor 114 is connected to the line ISVR from the bias reference circuit 54 described above.
Biased by

The gate of transistor 112 is biased by a current mirror circuit as described in detail below. According to this embodiment of the invention, the current mirror of sink current path circuit 25 'has a reference branch consisting of P-channel transistor 144 and N-channel transistor 148 with their source / drain paths connected in series. The source of transistor 144 is biased to V _CC and transistor 148
Is connected to the drain of the current source transistor 152. The gate and drain of the transistor 144 are commonly connected, while the gate of the transistor 148 is connected to the resistor dividers 47, 4 of the reference voltage / regulator 24 described above.
Receive the divided voltage from 9. On the mirror side,
P-channel transistor 146 has its source biased to V _CC and its gate connected to transistor 144.
Connected to the gate and drain of the. N-channel transistor 150, on the other hand, has its drain connected to the drain of transistor 146 and its source connected to the source of transistor 148 in the reference branch, which in turn is connected to the drain of current source transistor 152. . The drains of transistors 146 and 150 are connected to the gate of transistor 112, and thus their drain voltage controls the conduction state of transistor 112. The gate of the transistor 152 is the line VO
Connected to HREF. Current source transistor 152
Has its source biased to ground and receives the bias voltage ISVR at its gate, and transistor 52 in the previously mentioned reference voltage regulator 24.
And conducts the controlled current i _BIAS therethrough.

Transistors 148 and 150 are preferred.
Are balanced with each other, and the transistor 144
And 146 are balanced with each other so that the current mirror ratio is substantially 1. An unamplified current mirror ratio can be used for this current mirror. This is because no significant supply or sink current is then required. As a result, no offset voltage is generated.

To explain the operation, the transistor 1
The current conducted by 46 is controlled by transistor 148.
Underneath, the group conducted by transistor 144
A quasi-current is generated by the mirror action and these reference currents
And the mirror current is added to
Current i_BIASAre conducted. By the transistor 150
Conducted current follows the voltage on line VOHREF
Controlled. Therefore, as described above, the output buffer 2
On line VOHREF based on switching operation 1
As the voltage on
Turned on. This means that the transistors 146,
The voltage at the drain of 150 and the transistor 112
The voltage at the gate of the
Turn off the transistor 112. Bias voltage ISV
Transistor 114 controlled by R is a transistor
There is a tendency to pull the gate of the switch 110 closer to the ground.
Turn on transistor 110, and thus line V
Provides an additional current sink path for OHREF.
This means that in the sink current state, the reference voltage / regulator 2
4 gives a reduced output impedance and thus
The voltage on IN-VOHREF exceeds its desired level
-Reduce the range that tends to shoot. Variable output V _OH control According to yet another embodiment of the present invention, whether by logic signals or
VOH by any of the fuse's programmability
The selectability of the REF limiting function is given. The present invention
Others that use a lower power supply, according to this embodiment of
Memory specified for use in combination with an integrated circuit of
Deal with cases where not all have the same configuration
Things. For example, if the subset memory is V_OHmaximum
Is 5.0 V, while V is_OHMost
Large may be limited to 3.3V. Manufacturing capacity
Either for ease of use and inventory control purposes
To provide a single integrated circuit design suitable for use
Desirable, in which case V of 5.0V or 3.3V_OH
The decision of the maximum is as possible as possible in the manufacturing process
Hopefully can be done in the final stage
Good. In addition, certain memory chips are suitable for 3.3V operation.
What you are doing is processing parameters such as current drive
May be dependent, so some memory may be VOHRE
3.3V operation even if F limit function is enabled
Although it does not satisfy the situation, V of 5.0V_OHHave maximum
The operating specifications for the memory to be used may be satisfied. This
In case of VOHREF limiting function after electrical test
It is desirable to have the possibility of selecting.

In addition, it may be useful to have a special test mode for memory 10 in which the VOHREF limiting function can be selectively enabled and disabled.

Next, referring to FIG. 10, there is shown another embodiment of the present invention, in which the reference voltage / regulator 124 is constructed similarly to the reference voltage / regulator 24 described above. However, it can be disabled by an external signal, a special test mode signal, or programming of the fuse circuit. It should be noted that common reference numerals are given to constituent elements common to the reference voltage / regulator 24 and the reference voltage / regulator 124, and the description of the reference voltage / regulator 124 in FIG. 10 will not be repeated. .

In addition to the components described above, the reference voltage / regulator 124 includes P-channel transistors 82, 84,
89 and an N-channel transistor 86,
They are NOR gates 8 as described in detail below.
VOHREF displayed by output of 0
If the limiting function is to be disabled, force a node to V _CC or ground. Each of P-channel transistors 82, 84, 89 has its source biased to V _CC and its gate is NOR gate 80.
The line LIMOFF * is received from the output terminal of. The drain of the transistor 82 is connected to the gates of the transistors 44 and 46 in the current mirror of the reference voltage regulator 124, and the drain of the transistor 84 is connected to the reference voltage.
It is connected to line VOHREF at the output of regulator 124, and the drain of transistor 89 is connected to the input to bias reference circuit 54. N-channel transistor 86 has its drain connected to node ISVR in bias current source 26, its source connected to ground, and its gate receives signal LIMOFF * after being inverted by inverter 85. . According to this embodiment of the invention, pass gate 88 is provided between voltage PVBIAS and bias reference circuit 54 and is controlled by the true and complement signals based on signal LIMOFF *.

The operation will be described. NOR function unit 8
When the line LIMOFF * at the 0 output is at a high logic level, transistors 82, 84, 86 and 89 are all turned off and pass gate 88 is turned on. In this case, the reference voltage / regulator 124 will operate on the line VOHR in the manner described above for the reference voltage / regulator 24.
Operates to limit the voltage at EF.

However, when line LIMOFF * at the output of NOR function 80 is at a low logic level, transistors 82, 84, 86 and 89 are all turned on and pass gate 88 is turned off. Under this condition, line VOHREF is forced to 5.0.
V and thus applied to the output buffer 21 (hence the pull-up transistor 3 in the output driver 20).
The drain voltage (applied to the 2 gate) is not limited to a reduced level. Reference voltage / regulator 124
A node therein is also forced to a particular voltage in order to minimize the DC current drawn through it. In this embodiment, the gates of transistors 44 and 46 are pulled to V _CC by transistor 82, thus turning off both the reference and mirror branches in reference voltage regulator 124. The pass gate 88 disconnects the voltage PVBIAS from the bias reference circuit 54 and causes the transistor 8
9 pulls the input terminal to the bias reference circuit 54 to V _CC ,
And transistor 86 pulls node ISVR to ground, thus turning off transistors 52 and 58. Of course, the output terminal of the NOR function section 80 can be further applied to a node in the offset compensating current source 28, the bias reference circuit 54, etc., if desired.

In this embodiment of the invention, NOR function 80 receives three inputs and drives the line LIMOFF * low when any one of them is at a high logic level. The first input is a logic signal DIS, which is for example a memory 10 such as a timing and control circuit 14.
Can be generated at other locations in. For example, some combination of inputs or instructions may be
It is possible to apply the logic signal DIS to 0 to activate the logic signal DIS. The second input on node FDIS of NOR function 80 is generated by fuse circuit 90. Fuse circuit 90 is configured as described above in connection with fuse circuit 75, so that node FDIS is at a low logic level when the fuse remains unchanged and a high logic level when the fuse is blown. is there.

According to this embodiment of the invention, the special test pad TP is in wafer form (ie before packaging).
Reference voltage / regulator 12 during electrical test in
4 enable and disable operations can be controlled. Test pad TP is connected to the input of inverter 91, which drives node TDIS, which is received as an input to NOR function 80. The transistor 92 has its source / drain path connected to the inverter 91.
Is connected to the node TDIS at the output of the inverter 91. The transistor 93 has its source / drain path connected between the input end of the inverter 91 and the ground, and its gate has a power-on reset signal PO.
Controlled by R.

To explain the operation, the test pad T
When P is held at V _CC , the inverter 91 operates at the node TD.
Force IS low. However, when test pad TP is left open or connected to ground, upon power-up, transistor 93 pulls the input of inverter 91 low, node TDI.
Force a high logic level on S, which is maintained by the operation of transistor 92. Therefore, during the electrical test period, the test pad TP is connected to the reference voltage / regulator 124.
It is possible to control the enable and disable operations of the. Depending on such test results, test pad TP can be wirebonded to V _CC if reference voltage and regulator 124 should be permanently enabled, or reference voltage If the regulator 124 is to be permanently disabled for a particular memory 10, it can be opened (preferably hardwired to ground).

The selective enabling and disabling of the V _OH limiting function of the reference voltage regulator according to the present invention significantly improves the manufacturing control of the integrated circuit incorporating the function. In particular, integrated circuits corresponding to different specification limits can be manufactured from the same design by selecting the maximum V _OH voltage after electrical testing and later in the manufacturing process. Further, as mentioned above, fuse programming can be used to adjust the voltage divider that provides the input voltage to the reference voltage regulator circuit, thus additionally tuning the desired maximum V _OH voltage. It is possible.

Although the specific embodiments of the present invention have been described in detail above, the present invention should not be limited to these specific examples, and various modifications can be made without departing from the technical scope of the present invention. It goes without saying that the above can be modified.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing an integrated memory circuit incorporating an output driver circuit according to a preferred embodiment of the present invention.

FIG. 2 is a schematic diagram showing an output driver circuit constructed according to a preferred embodiment of the present invention.

FIG. 3 is a schematic diagram showing a reference voltage and regulator circuit constructed in accordance with a preferred embodiment of the present invention.

FIG. 4 is a schematic diagram showing a bias current source used in a reference voltage and regulator circuit constructed in accordance with a preferred embodiment of the present invention.

FIG. 5 is a timing diagram illustrating the operation of a reference voltage and regulator circuit constructed according to the preferred embodiment of the present invention when no offset compensating current is present.

FIG. 6 is a timing diagram illustrating the operation of a reference voltage and regulator circuit constructed in accordance with a preferred embodiment of the present invention when an offset compensating current is present.

FIG. 7 is a schematic diagram showing a dynamic bias control circuit for use in a reference voltage and regulator circuit constructed in accordance with a preferred embodiment of the present invention.

FIG. 8 is a timing diagram showing the operation of the circuit of FIG. 7 in an integrated circuit memory.

FIG. 9 is a schematic diagram illustrating a bias current source configured according to another embodiment of the present invention having a programmable bias current level.

FIG. 10 is a schematic diagram showing a reference voltage and regulator circuit constructed in accordance with a preferred embodiment of the present invention.

FIG. 11 is a schematic diagram showing a reference voltage circuit configured based on a conventional technique.

FIG. 12 is a schematic diagram illustrating a reference voltage and regulator circuit according to another embodiment of the present invention with a circuit providing an additional sink current path.

FIG. 13 is a schematic diagram illustrating a reference voltage and regulator circuit including circuitry for providing an additional sink current path according to yet another embodiment of the invention.

[Explanation of symbols]

 10 read / write memory 12 address register 14 timing / control circuit 16 memory array 17 address recorder 18 input driver 19 read circuit 20 output driver 21 output buffer 22 output buffer bias circuit 28 data terminal

Claims (18)

[Claims] 1. A reference voltage circuit comprising: a source / drain path having a first end connected to a power supply voltage; and a gate connected to a drain end of the source / drain path. A reference transistor, comprising a source / drain path connected between a second end of the source / drain path of the first reference transistor and a common node, and comprising a gate for receiving a reference voltage; A second mirror transistor, a first mirror transistor having a source / drain path connected between the power supply voltage and an output node and having a gate connected to the gate of the first reference transistor; A second mirror transistor having a source / drain path connected between an output node and a common node and having a gate A transistor, a bias current source coupled to the common node for conducting a current including a sum of currents in the second reference transistor and the second mirror transistor, and a voltage at the output node connected to the output node is desired. And a sink current path circuit that conducts current in response to exceeding the level of the reference voltage circuit. 2. The sink transistor according to claim 1, wherein the sink current path circuit comprises a conduction path connected between the output node and ground, and a control electrode. A reference voltage circuit, comprising: a sink bias circuit coupled to a node and a control electrode of the sink transistor to turn on the sink transistor in response to a rise in voltage at the output node. 3. The control electrode according to claim 2, wherein the sink bias circuit has a conduction path connected between the first voltage and a control electrode of the sink transistor, and is biased to a bias voltage. A load transistor comprising: a sink transistor having a conduction path connected in series with a conduction path of the load transistor and having a control electrode coupled to respond to a voltage at the output node; A reference voltage circuit having a transistor. 4. The reference voltage circuit according to claim 3, wherein the control electrode of the sink control transistor is coupled to the gate of the first mirror transistor. 5. The reference voltage circuit according to claim 1, wherein the first mirror transistor and the first reference transistor are P-channel field effect transistors. 6. The reference voltage circuit according to claim 5, wherein the load transistor is a P-channel field effect transistor and the sink control transistor is an N-channel field effect transistor. 7. The reference voltage circuit according to claim 6, wherein the control electrode of the load transistor is connected to the common node. 8. The method according to claim 3, further comprising a source / drain path having a first end connected to the power supply voltage, and a gate connected to a drain end of the source / drain path. A first sink reference transistor, a source / drain path connected between a second end of the source / drain path of the first sink reference transistor and a sink common node, and the reference voltage A second sink reference transistor having a gate for receiving the first sink reference, the source / drain path connected between the power supply voltage and a control electrode of the sink control transistor, and A first sink mirror transistor having a gate connected to the gate of a transistor, control of said sink control transistor A second sink mirror transistor having a source / drain path connected between a pole and a sink common node and having a gate; the second sink reference transistor coupled to the sink common node And a sink bias current source for conducting a current including a sum of currents in the second sink mirror transistor. 9. The reference voltage circuit according to claim 8, further comprising a voltage divider for generating a reference voltage applied to the gate of the second reference transistor and the gate of the second sink reference transistor. 10. The reference voltage circuit according to claim 1, wherein the second mirror transistor has a significantly larger current drive capability than that of the second reference transistor. 11. An output driver circuit for an integrated circuit, comprising a pull-up drive transistor comprising a conduction path coupled between a power supply voltage and an output terminal and comprising a control electrode. A circuit for limiting the drive of the pull-up drive transistor in response to a bias voltage, a reference voltage / adjuster circuit for generating the bias voltage, and the reference voltage / adjustment circuit. A voltage divider that generates a voltage divided based on the power supply voltage, and a current mirror that includes a reference branch and a mirror branch, the reference branch being divided by the voltage divider. Receiving a voltage and conducting a reference current in response thereto, the mirror branch conducting a mirror current in response to the reference current and at the output based on the mirror current. A bias mirror for deriving a bias voltage, a bias current source coupled to the reference branch of the current mirror and the mirror branch for controlling the reference current and the mirror current conducted at that time, and the bias voltage of the current mirror And a sink current path circuit coupled to an output terminal and conducting a sink current in response to the bias voltage output exceeding a desired level, the output driver circuit. 12. The circuit according to claim 11, wherein a circuit for limiting driving of the pull-up driving transistor has an input terminal for receiving a data signal and is connected to a control electrode of the pull-up driving transistor. An output driver circuit having an output buffer having an output end, the output buffer being connected to receive a bias voltage lower than the power supply voltage. 13. The reference P-channel transistor according to claim 12, wherein the current mirror has a source biased by the power supply voltage and has a commonly connected drain and gate. A reference N-channel transistor having a drain connected to the drain of the transistor, having a gate for receiving the divided voltage, and having a source connected to the bias current source; A source biased by the power supply voltage, a gate connected to the gate of the reference P-channel transistor, and a drain coupled to generate the bias voltage. Mirror P-channel transistor, connected to the bias current source A mirror N-channel transistor having a source and having a drain connected to the drain of the mirror P-channel transistor and having a gate coupled to receive the bias voltage. An output driver circuit characterized by: 14. The sink current path circuit according to claim 13, wherein the sink current path circuit includes a conduction path connected between a first power supply and a control electrode of the sink transistor, and is biased to an ON state. A load transistor having a control electrode, a sink control having a conduction path in series with a conduction path of the load transistor and having a control electrode coupled to respond to the bias voltage. An output driver circuit including a transistor. 15. The output driver circuit of claim 14, wherein the control electrode of the sink control transistor is coupled to the gate of the mirror P-channel transistor. 16. The output driver circuit according to claim 15, wherein the load transistor is a P-channel field effect transistor, and the sink control transistor is an N-channel field effect transistor. 17. The output driver circuit according to claim 16, wherein a control electrode of the load transistor is connected to the common node. 18. The method of claim 14, further comprising a source / drain path having a first end connected to a power supply voltage and a gate connected to a drain end of the source / drain path. A first sink reference transistor, a source / drain path connected between a second end of the source / drain path of the first sink reference transistor and a sink common node, and A second sink reference transistor having a gate for receiving a voltage, a source / drain path connected between the power supply voltage and a control electrode of the sink control transistor, and the first sink A first sink mirror transistor having a gate connected to the gate of a reference transistor, said sink control transistor A second sink mirror transistor having a source / drain path connected between a control electrode and the sink common node and having a gate; coupled to the sink common node; An output driver circuit comprising a sink reference transistor and a sink bias current source that conducts a current including a sum of currents in the second sink mirror transistor.