JPH1188144A - Input circuit for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an input buffer for a semiconductor device that is stably operated even over the wide range of power supply voltage. SOLUTION: N-channel MOS transistors(TRs) 60, 61 are connected in series between a line of a ground level GND and an output node N54b of a 1st stage inverter 54 of an input buffer. A gate of the MOS TR 60 receives an input signal V1 and a gate of a MOS TR 61 receives an output voltage Vc of a voltage generating circuit 1. The MOS TR 61 is conductive with a conduction resistance in response to a range of 3-5 V of a power supply voltage VCC. Since a threshold voltage of the 1st stage inverter is continuously changed in the range of 3-5 V of the power supply voltage VCC, the input buffer is stably operated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input circuit of a semiconductor device, and more particularly, to an input circuit of a semiconductor device which generates an internal signal according to an external signal and supplies the internal signal to the internal circuit.

[0002]

2. Description of the Related Art FIG. 9 is a partially omitted circuit block diagram showing a configuration of a conventional semiconductor integrated circuit device (for example, DRAM) 50. Referring to FIG. 9, the semiconductor integrated circuit device 50 includes input buffers 51.1 to 51. m (m is a natural number), the internal circuit 52, and the output buffer 53.1
~ 53. n (n is a natural number).

[0003] Input buffers 51.1-51. m receives the external signals EXT1 to EXTm, generates an internal signal, and supplies the internal signal to the internal circuit 52. The internal circuit 52 includes input buffers 51.1 to 51. A predetermined operation (data writing / reading operation for a DRAM) is performed according to the internal signal given from m. Output buffers 53.1 to 53. n amplifies the signals D1 to Dn generated by the internal circuit 52 and outputs the amplified signals to the outside.

FIG. 10 shows an input buffer 5 shown in FIG.
1. FIG. 3 is a circuit diagram showing a configuration of m. Referring to FIG.
Input buffer 51. m includes an even number (four in the figure) of inverters 54 to 57 connected in series.

[0005] As shown in FIG.
P-channel MOS transistor 58 connected in series between the line of power supply potential VCC and the line of ground potential GND
And N channel MOS transistor 59. MO
The gates of S transistors 58 and 59 are connected to input node N54a of inverter 54, and MOS transistor 5
The drains of 8, 59 are output node N5 of inverter 54.
4b.

When input signal VI (EXTm) is at "L" level VIL, P-channel MOS transistor 58 is turned on and N-channel MOS transistor 59 is turned off, so that the potential of output node N54b, that is, output signal VO5 is output.
4 is at "H" level. When the level of input signal VI rises, the resistance of P-channel MOS transistor 58 increases and the resistance of N-channel MOS transistor 59 decreases. When the level of the input signal VI is
4 exceeds the threshold voltage Vth54 of the output node N5.
When the potential of 4b starts dropping and input signal VI goes to "H" level VIH, P-channel MOS transistor 58 is turned off, N-channel MOS transistor 59 is turned on, and output signal VO54 goes to "L" level.

On the contrary, when the input signal VI is at the "H" level VIH
From the input signal V to the “L” level VIL
When I decreases the threshold voltage of inverter 54 below Vth 54, the potential of output node N54b starts to rise,
When input signal VI attains "L" level VIL, P-channel MOS transistor 58 is rendered conductive, N-channel MOS transistor 59 is rendered non-conductive, and output signal VO54 attains "H" level. The same applies to the configuration and operation of the other inverters 55 to 57.

Therefore, when input signal VI transitions from "L" level VIL to "H" level VIH, for example, outputs VO54-VO of inverters 54-57 are output.
57 are sequentially inverted, and the input buffers 51. m output VO
(VO57) transitions from the "L" level to the "H" level after a predetermined delay time from the transition of the input signal VI.

In the semiconductor integrated circuit device 50, the power supply voltage is being reduced along with the improvement in the integration density. In recent years, devices having a power supply voltage VCC of 5V and devices having a power supply voltage VCC of 3V are mixed. In such a situation, the power supply voltage VCC
Therefore, a device that normally operates regardless of whether 5 V or 3 V is applied is desired.

On the other hand, the threshold voltage Vt of the inverter 54
h54 is determined by the ratio βP / βN of the current gain βP of the P-channel MOS transistor 58 to the current gain βN of the N-channel MOS transistor 59, and the power supply voltage VCC. For example, when βP / βN = 1 and VCC = 3V, the threshold voltage Vth54 becomes 1.5V, and βP / βN =
In the case of 1 and VCC = 5V, the threshold voltage Vth54 becomes 2.5V.

Therefore, for example, when VCC = 3V, βP / β is adjusted so that threshold voltage Vth54 becomes an appropriate value.
When N is set, the threshold voltage Vth54 becomes higher than an appropriate value when used at VCC = 5V. As a result, when the input signal VI changes from VIL to VIH and when the input signal VI changes from VIH to VIL, the input buffer 51. A difference occurs in the delay time of m. Further, the “H” level VIH of the input signal VI and the threshold voltage Vth54
, The margin becomes smaller, and a malfunction easily occurs.

Therefore, for example, Japanese Patent Laid-Open Publication No.
As disclosed in Japanese Unexamined Patent Publication, the power supply voltage VCC is 5 V
A method has been proposed in which the βP / βN value of the first-stage inverter is switched at 3 V to suppress the change in threshold voltage Vth.

In this input buffer, as shown in FIG. 12, output node N54b of inverter 54 and ground potential G
N channel MOS transistor 6 between ND line
0 and 61 are connected in series, and a signal generation circuit 62
Is provided. The gate of N-channel MOS transistor 60 is connected to the gate of N-channel MOS transistor 59, and the gate of N-channel MOS transistor 61 receives output signal φc of signal generation circuit 62. The signal generation circuit 62 detects the power supply voltage VCC, and outputs “L” level when VCC = 3V, and outputs “H” level when VCC = 5V.

Next, the operation of the input buffer will be described. When VCC = 3V, signal φc attains the “L” level, and N-channel MOS transistor 61 is rendered non-conductive, and the first-stage inverter is constituted only by inverter 54. In this case, the threshold voltage Vth of the first-stage inverter
54 ′ is the βP / βN and VC as described with reference to FIG.
It is determined at C = 3V.

When VCC = 5V, the signal φc becomes "H"
Level, and the N-channel MOS transistor 6 is turned on.
It is composed of an S transistor 60. In this case, the threshold voltage Vth54 'of the first-stage inverter is determined by βP / βN' and VCC = 5V. Here, βN ′ is the sum of the current amplification factors of N-channel MOS transistors 59 and 60, and βN ′> βN.

Therefore, by setting βP / βN and βP / βN ′ to appropriate values, the threshold voltage Vth can be kept constant regardless of whether the power supply voltage VCC is 3 V or 5 V.
The operation margin becomes small or the input signal VI becomes VIH
, And a transition from VIL to VIH can be prevented from having a difference in delay time of the input buffer.

[0017]

However, the signal generation circuit 62 shown in FIG. 12 uses a certain reference voltage Vref (for example, 4 ref.
V) is compared with the power supply voltage VCC, and when VCC <Vref, an “L” level is output. When VCC> Vref, an “H” level is output. Therefore, when VCC = 5V, the internal circuit is output. When the power supply voltage VCC decreases due to the operation of 52 and oscillates around 4 V, there is a problem that the threshold voltage Vth of the first-stage inverter also fluctuates and the operation of the device becomes unstable.

Therefore, a main object of the present invention is to provide an input circuit of a semiconductor device which operates stably with respect to a wide range of power supply voltages.

Another object of the present invention is to provide a delay time when an external signal transitions from a first logic potential to a second logic potential and when an external signal transitions from the second logic potential to the first logic potential. Is to provide an input circuit of a semiconductor device in which

[0020]

The invention according to claim 1 is
An input circuit of a semiconductor device that generates an internal signal according to an external signal and provides the internal signal to an internal circuit, comprising: a first transistor of a first conductivity type; second to fourth transistors of a second conductivity type; Prepare. The first of the first conductivity type
Is connected between a first power supply node and an output node from which an internal signal is output, and its input electrode receives an external signal. A second transistor of a second conductivity type is connected between the second power supply node and the output node;
The input electrode receives an external signal. A third transistor of the second conductivity type has its first electrode connected to the output node and its input electrode receiving an external signal. A fourth transistor of the second conductivity type is connected between a second electrode of the third transistor and a second power supply node. When the power supply voltage applied between the first and second power supply nodes has the first voltage value, the control unit turns off the fourth transistor, and the second power supply voltage is different from the first voltage value. When the power supply voltage is a voltage value between the first and second voltage values, the fourth transistor is turned on with a conduction resistance value corresponding to the voltage value. Make it conductive.

In the invention according to claim 2, the control means according to claim 1 reduces the power supply voltage by a predetermined voltage and inputs the reduced voltage to the fourth transistor.

According to a third aspect of the present invention, there is provided an input circuit of a semiconductor device for generating an internal signal according to an external signal and supplying the internal signal to an internal circuit, wherein the plurality of inverters are connected in series, and a third transistor of a second conductivity type is provided. , And control means. Each of the plurality of inverters connected in series,
A first power supply node is connected between a first power supply node and a subsequent-stage input node, and has an input electrode connected to a preceding-stage output node.
And a second transistor of the second conductivity type, which is connected between the second power supply node and the subsequent input node and whose input electrode is connected to the previous output node. The first stage receives an external signal and the last stage outputs an internal signal. The third transistor of the second conductivity type is connected between an output node of an inverter other than the first stage of the plurality of inverters and a second power supply node. The control means turns off the third transistor when the output voltage of the inverter preceding the certain inverter is the first voltage value, and when the output voltage is the second voltage value different from the first voltage value Turns on the third transistor.

According to a fourth aspect of the present invention, the control means according to the third aspect of the present invention lowers the output voltage of the inverter preceding the certain inverter by a predetermined voltage and inputs it to the third transistor.

According to a fifth aspect of the present invention, there is provided an input circuit of a semiconductor device which generates an internal signal in accordance with an external signal and supplies the internal signal to an internal circuit, comprising a first delay circuit, a second delay circuit, and gate means. The first delay circuit delays the external signal by a first time when the external signal transitions from the first logical potential to the second logical potential, and changes the external signal from the second logical potential to the first logical potential. In the case of transition to the potential, the potential is delayed by a second time shorter than the first time. The second delay circuit delays the external signal by a first time when the external signal transitions from the second logical potential to the first logical potential, and causes the external signal to change from the first logical potential to the second logical potential. In the case of transition to the potential, the potential is delayed by a third time shorter than the first time.
The gate means receives the output signals of the first and second delay circuits, and applies the slower one of the output signals to the internal circuit as an internal signal.

According to the sixth aspect of the present invention, the gate means of the fifth aspect of the present invention comprises the first and second gates of the first conductivity type.
, And third and fourth transistors of the second conductivity type. First and second transistors of the first conductivity type are connected in series between a first power supply node and an output node from which an internal signal is output, and each input electrode has a first and second delay, respectively. Receives the output signal of the circuit. Third and fourth transistors of the second conductivity type are connected in series between a second power supply node and an output node, and each input electrode receives an output signal of the second and first delay circuit, respectively. .

According to a seventh aspect of the present invention, there is provided an input circuit of a semiconductor device for generating an internal signal in accordance with an external signal and supplying the internal signal to an internal circuit, comprising a first delay circuit, a second delay circuit, and gate means. The first delay circuit delays the external signal by a first time when the external signal transitions from the first logical potential to the second logical potential, and changes the external signal from the second logical potential to the first logical potential. When transitioning to the potential, the potential is delayed by a second time longer than the first time. The second delay circuit delays the external signal by a first time when the external signal transitions from the second logical potential to the first logical potential, and causes the external signal to change from the first logical potential to the second logical potential. In the case of transition to the potential, the potential is delayed by a third time longer than the first time.
The gate means receives the output signals of the first and second delay circuits, and provides an earlier signal of the output signals to the internal circuit as an internal signal.

In the invention according to claim 8, the gate means according to claim 7 includes first and second inverters. The first inverter is activated in response to the transition of the external signal from the first logic potential to the second logic potential,
The output signal of the first delay circuit is transmitted as an internal signal. The second inverter is activated in response to a transition of the external signal from the second logic potential to the first logic potential,
The output signal of the second delay circuit is transmitted as an internal signal.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] FIG. 1 is a circuit block diagram showing a configuration of an input buffer of a semiconductor integrated circuit device according to a first embodiment of the present invention, which is compared with FIG. Referring to FIG. 1, this input buffer is different from the input buffer of FIG. 12 in that signal generation circuit 62 is replaced with voltage generation circuit 1.

As shown in FIG. 2, the voltage generating circuit 1 includes a power supply potential VCC line and an output node N of the voltage generating circuit 1.
1 and a P-channel MOS transistor 2 and an N-channel MOS transistor 3 connected in series between the output node N1 and a line of the ground potential GND. including. The gate of P-channel MOS transistor 2 receives signal / CS, and receives N-channel MOS transistor 3
Is connected to its drain, and an N-channel MOS
The gate of transistor 4 is connected to its source. N
Channel MOS transistors 3 and 4 and resistance element 5
Causes a small current to flow so that the output node N1 does not enter a floating state.

At the time of standby, signal / CS attains the "H" level of the inactivation level, P channel MOS transistor 2 is rendered non-conductive, and the through current from the line of power supply potential VCC to the line of ground potential GND is cut off. As a result, current consumption is reduced.

When active, signal / CS attains the "L" level of the activation level, P channel MOS transistor 2 is rendered conductive, and P channel MOS transistor 2 and N channel MOS transistors 3, 4 are connected from the line of power supply potential VCC. A current flows to the ground potential GND line via the resistor element 5 and the potential of the output node N1, that is, the control voltage Vc becomes VCC-Vthn3. However, Vthn
3 is a threshold voltage of the N-channel MOS transistor 3.

When VCC = 3V, Vc = 3-Vthn
3 (V), the N-channel MOS transistor 61 becomes non-conductive, and when VCC = 3 to 5 V, the conduction resistance value of the N-channel MOS transistor 61 decreases continuously as VCC increases, and VCC = 5 V In the case of Vc = 5-V
Vthn3 is set so that Nth MOS transistor 61 is turned on at thn3 (V).
Other configurations and operations are the same as those of the conventional input buffer shown in FIG. 12, and therefore, description thereof will not be repeated.

In this embodiment, the threshold voltage Vth54 'of the first-stage inverter is not changed in two steps as in the prior art, but is changed analogously, that is, continuously, in accordance with the power supply voltage VCC. VCC is 3V
It operates stably even if it vibrates between 5 and 5V.

In this embodiment, the power supply voltage VC
Although the case where C fluctuates between 3 V and 5 V has been described, the present invention is not limited to this, and the present invention relates to the power supply voltage VC.
It is needless to say that the present invention is also effective when C varies between a very low voltage (1.8 V or less) and a high voltage.

FIG. 3 is a circuit diagram showing a modification of the voltage generation circuit 1 shown in FIG. Referring to FIG. 3, voltage generating circuit 6 is different from voltage generating circuit 1 in that P-channel M
The point is that the OS transistor 2 is removed and N-channel MOS transistors 7 and 8 are newly provided. N channel MOS transistors 7 and 8 are connected to N channel MOS transistor 4 and resistance element 5 and ground potential G, respectively.
And ND line, and each gate receives signal CS together.

At the time of standby, signal CS attains the "L" level of the inactivation level, N channel MOS transistors 7 and 8 become non-conductive, and a through current from the line of power supply potential VCC to the line of ground potential GND is generated. It is cut off and current consumption is reduced.

When active, signal CS attains the "H" level of the inactive level, and N-channel MOS transistors 7, 8 are turned on, and N-channel MOS transistors 3, 4, 7, 8, 8 are connected from the line of power supply potential VCC. A current flows through the line of the ground potential GND via the resistor element 5 and the control voltage Vc becomes VCC-Vth3.

In voltage generating circuits 1 and 6, N channel MOS transistor 4 and resistance element 5 are provided for flowing a minute current from output nodes N1 and N6 to the line of ground potential GND. Only one of the resistance elements 5 may be provided. In addition, M for cutting through current during standby is
The OS transistors 2, 7, and 8 may be removed.
The specific configuration of the circuit may be any as long as it has a function similar to that of the voltage generating circuits 1 and 6.

[Second Embodiment] FIG. 4 is a circuit diagram showing a configuration of an input buffer of a semiconductor integrated circuit device according to a second embodiment of the present invention, which is compared with FIG. Referring to FIG. 4, this input buffer is different from the input buffer of FIG. 10 in that N-channel MOS transistor 10 is connected between output node N56b of third-stage inverter 56 and a line of ground potential GND. The point is that the N-channel MOS transistor 11 is connected between the input node N56a of the inverter 56 and the gate of the N-channel MOS transistor 10. The gate of N-channel MOS transistor 11 receives power supply potential VCC.

When the output VO55 of the second-stage inverter 55 goes to the "H" level (power supply potential VCC), the gate potential Vg of the N-channel MOS transistor 10 becomes VCC-V
thn11. Here, Vthn11 is a threshold voltage of the N-channel MOS transistor 11. VCC
= 3V, Vg = 3-Vthn11 (V), the N-channel MOS transistor 10 becomes non-conductive, and
When CC = 5V, Vg = 5−Vthn11 (V) so that the N-channel MOS transistor becomes conductive.
Vthn11 is set.

This input buffer has a voltage of VCC = 3V
In such a case, the buffer characteristics such as the operation margin are set to be optimal. Also, when VCC = 5V and input signal VI transitions from "L" level VIL to "H" level VIH and when transitions from VIH to VIL, the delay time of the input buffer becomes equal so that the N-channel MOS Threshold voltage Vthn11 of transistor 11 and current amplification factor β of N-channel MOS transistor 10
N is set.

Next, the operation of the input buffer will be described. When VCC = 5V, input signal VI is at “L” level V
When IL transitions to “H” level VIH and output VO55 of second-stage inverter 55 transitions from “L” level to “H” level, Vg = 5−Vthn11 (V), and N-channel MOS transistor 10 And the output VO56 of the third-stage inverter 56 quickly transitions from the “H” level to the “L” level. Therefore VCC =
In the case of 5V, the threshold voltage Vth of the first-stage inverter 54
54 becomes too high and the input signal VI changes from VIL to VIH.
To prevent the delay time of the input buffer from becoming long.

The first inverter 54 is connected to the NOR of FIG.
The gate 12 may be replaced. NOR gate 12 includes P-channel MOS transistors 13 and 14 connected in series between a power supply potential VCC line and output node N12b.
And an N-channel MOS transistor 1 connected in parallel between output node N12b and a line of ground potential GND.
5 and 16. The gates of MOS transistors 14 and 15 are connected to input node N12a to receive input signal VI, and the gates of MOS transistors 13 and 16 are commonly connected to receive signal / CS. Signal / CS is at "H" level during standby and at "L" level when active. Therefore, the through current during standby is reduced.

The N-channel MOS transistor 11
As shown in FIGS. 6A and 6B, the N-channel MOS transistor 17 diode-connected between the node N56a and the gate of the N-channel MOS transistor 10
Alternatively, it may be replaced with a P-channel MOS transistor 18. Further, a plurality of MOS transistors 11, 17, or 18 may be connected in series between node N56a and the gate of N-channel MOS transistor 10.

It goes without saying that Embodiments 1 and 2 may be combined. [Third Embodiment] FIG. 7 is a circuit block diagram showing a configuration of an input buffer of a semiconductor integrated circuit device according to a third embodiment of the present invention.

Referring to FIG. 7, this input buffer includes inverters 20 to 23 and 28, P-channel MOS transistors 24 and 25 and N-channel MOS transistor 2
6,27. Inverters 20, 21; 22, 23
Are connected in series between the input node N20 of the input buffer and the nodes N21 and N23. P channel M
OS transistors 24 and 25 are connected in series between the line of power supply potential VCC and node N25, and have an N-channel MOS transistor.
S transistors 26 and 27 are connected between node N25 and ground potential G.
It is connected in series with the ND line. The gates of MOS transistors 24 and 26 are connected to node N21,
The gates of the OS transistors 25 and 27 are connected to the node N23. Inverter 28 is connected between node N25 and output node N28 of the input buffer.

The buffer constituted by the inverters 20 and 21 is set such that the delay time T1 when the input signal VI changes from VIL to VIH is longer than the delay time T2 when the input signal VI changes from VIH to VIL. (T1> T2). On the other hand, in the buffer constituted by the inverters 22 and 23, the delay time T3 when the input signal VI transitions from VIH to VIL is longer than the delay time T4 when the input signal VI transitions from VIL to VIH, and T1 =
T3 is set (T3 = T1> T
4).

Next, the operation of the input buffer will be described. When the input signal VI transitions from VIL to VIH, the node N23 becomes "H" level after T4 from the transition start, the P-channel MOS transistor 25 is turned off, and the N-channel MOS transistor 27 is turned on.
Further, after T1 (T1> T4) from the transition start, the node N2
1 becomes "H" level, P channel MOS transistor 24 becomes non-conductive, and N channel MOS transistor 2
6 conducts, node N25 attains an "L" level, and output VO of inverter 28 attains an "H" level.

Conversely, when the input signal VI transitions from VIH to VIL, the node N21 becomes "L" level after T2 (T2 <T1) from the start of the transition, the P-channel MOS transistor 24 becomes conductive, and the N-channel MOS transistor 2
6 becomes non-conductive. Also, T3 (T3 = T1) from the transition start
> T2) After that, the node N23 goes to the “L” level, the P-channel MOS transistor 25 conducts, and the N-channel MO
S transistor 27 is turned off, node N25 attains an H level, and output VO of inverter 28 attains an L level. Therefore, when the input signal VI is VI
Delay time when transitioning from L to VIH and input signal VI
Becomes equal to the delay time when the signal transits from VIH to VIL.

In this embodiment, the inverter 2
0 and 21 and inverters 22 and 23
Although two sets of buffers are provided, the present invention is not limited to this. Three or more sets of buffers may be provided so that the delay times are the same even when the power supply voltage VCC fluctuates.

It goes without saying that the first to third embodiments may be combined. [Fourth Embodiment] FIG. 8 is a circuit block diagram showing a configuration of an input buffer of a semiconductor integrated circuit device according to a fourth embodiment of the present invention.

Referring to FIG. 8, the input buffer includes inverters 30-37, 44, P-channel MOS transistors 38, 39, 41 and N-channel MOS transistors 40, 42, 43. Inverters 30 to 33;
34 to 37 are input nodes N3 of the input buffer, respectively.
0 and nodes N33 and N37 are connected in series. M
The OS transistors 38 to 40; 41 to 43 are connected in series between the power supply potential VCC line and the ground potential GND line, respectively. The gates of MOS transistors 38 and 43 are connected to output nodes N35 and N31 of inverters 35 and 31, respectively. MOS transistor 3
Gates 9 and 40 are both connected to node N33, and M
Both gates of OS transistors 41 and 42 are connected to node N
37, and the drains of the MOS transistors 39 to 42 are all connected to the node N40. Inverter 4
4 is a node N40 and an output node N44 of the input buffer.
Connected between

The buffer composed of the inverters 30 to 33 is set such that the delay time T11 when the input signal VI changes from VIH to VIL is shorter than the delay time T12 when the input signal VI changes from VIL to VIH. (T11 <T12). On the other hand, the buffer composed of the inverters 34 to 37 outputs the input signal VI from VIL to VI
The delay time T13 at the time of transition to H is from VIH to V
It becomes shorter than the delay time T14 when transitioning to IL,
And T11 = T13 (T1
1 = T13 <T14).

Next, the operation of the input buffer will be described. When the input signal VI transitions from VIH to VIL, the node N31 becomes “L” earlier than the node N35.
Level and the N-channel MOS transistor 43 becomes non-conductive. When the "L" level signal of node N31 is transmitted through inverters 32 and 33 and node N33 attains "L" level, node N35 is at "L" level and P channel MOS transistor 38 is conducting, so that When the node N33 becomes "L" level, the node N4
0 becomes the “H” level, and the output VO of the inverter 44 becomes the “L” level. Therefore, in this case, input signal VI is applied to output node N44 via inverters 30-33.
Is output to

On the other hand, when input signal VI transitions from VIL to VIH, node N35 goes to "H" level earlier than node N31, and P-channel MOS transistor 38 is turned off. When the "H" level signal of node N35 is transmitted through inverters 36 and 37 and node N37 attains "H" level, node N31 is at "H" level and N channel MOS transistor 43 is conducting, so that node N31 is at the "H" level. When N37 goes to "H" level, node N40 goes to "L" level, and output VO of inverter 44 goes to "H" level. Therefore, in this case, input signal VI is output to output node N44 via inverters 34-37.

Therefore, the input signal VI changes from VIL to V
The delay time when transitioning to IH is equal to the delay time when the input signal transitions from VIH to VIL.

In this embodiment, the inverter 3
Buffers composed of 0 to 33 and inverters 34 to 37
Although two sets of buffers are provided, the present invention is not limited to this. Three or more sets of buffers may be provided so that the delay times are the same even when the power supply voltage VCC fluctuates.

It goes without saying that the first, second, and fourth embodiments may be combined.

[0059]

As described above, according to the first aspect of the present invention, the third circuit is provided between the output node of the inverter and the power supply node.
And the fourth transistor are connected in series, and when the power supply voltage has the first or second voltage value, the fourth transistor is turned off or on, and the power supply voltage is between the first and second voltage values. The fourth transistor is turned on with a conduction resistance value corresponding to the voltage value. Therefore, even if the power supply voltage oscillates between the first and second voltage values, the threshold voltage of the first-stage inverter continuously changes, and the threshold voltage of the first-stage inverter changes in two stages. It operates more stably than before.

According to the invention of claim 2, the control means of the invention of claim 1 steps down the power supply voltage by a predetermined voltage and inputs it to the fourth transistor. In this case, the control means can be easily configured.

In the invention according to claim 3, a third transistor is connected between the output node and the power supply node of an inverter other than the first one of the plurality of inverters, and the output voltage of the inverter at the preceding stage of the inverter is connected to the third transistor. When the voltage is the first or second voltage value, the third transistor is turned off or turned on. Therefore, it is prevented that the output voltage of the inverter becomes the second voltage value and the delay time of the input circuit becomes long.

According to a fourth aspect of the present invention, the control means according to the third aspect of the present invention lowers the output voltage of the preceding inverter by a predetermined voltage and inputs it to the third transistor. In this case, the control means can be easily configured.

In the invention according to claim 5, the external signal is the first signal.
A first delay circuit that delays the external signal by a first time longer than the opposite case when the logic signal transitions from the second logic potential to the second logic potential,
A second delay circuit that delays the external signal by a first time longer when the logic signal transitions to the logic potential of
Gate means for providing a slower one of the output signals of the first and second delay circuits to the internal circuit; Therefore, the delay time of the input circuit becomes equal between when the external signal transitions from the first logic potential to the second logic potential and when the external signal transitions to the second logic potential.

In the invention according to claim 6, the gate means according to claim 5 is connected in series between the first power supply node and an output node to which an internal signal is output, and each input electrode is First and second transistors of the first conductivity type receiving the output signals of the first and second delay circuits are connected in series between a second power supply node and an output node, and each input electrode is Third and fourth conductive types receiving output signals to the second and first delay circuits
Transistors. In this case, the gate means can be easily configured.

In the invention according to claim 7, the external signal is the first signal.
A first delay circuit that delays the external signal by a first time shorter than the reverse case when the external signal changes from the second logical potential to the first logical potential
A second delay circuit that delays the external signal by a first time shorter than the opposite case when the potential changes to
And gate means for providing an earlier signal of the output signal of the second delay circuit to the internal circuit. Therefore, the delay time of the input circuit becomes equal between the case where the external signal transitions from the first logic potential to the second logic potential and the opposite case.

In the invention according to claim 8, the gate means according to the invention according to claim 7 is activated in response to the transition of the external signal from the first logic potential to the second logic potential, and
The first signal for transmitting the output signal of the first delay circuit as an internal signal.
, And a second inverter which is activated in response to the transition of the external signal from the second logical potential to the first logical potential and transmits the output signal of the second delay circuit as an internal signal. . In this case, the gate means can be easily configured.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a configuration of an input buffer of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a voltage generation circuit shown in FIG.

FIG. 3 is a circuit diagram showing a modified example of the voltage generation circuit shown in FIG.

FIG. 4 is a circuit diagram showing a configuration of an input buffer of a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a modified example of the input buffer shown in FIG.

FIG. 6 is a circuit diagram showing another modification of the input buffer shown in FIG. 4;

FIG. 7 is a circuit diagram showing a configuration of an input buffer of a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIG. 8 is a circuit diagram showing a configuration of an input buffer of a semiconductor integrated circuit device according to a fourth embodiment of the present invention.

FIG. 9 is a partially omitted circuit block diagram showing a configuration of a conventional semiconductor integrated circuit device.

FIG. 10 is a circuit diagram showing a configuration of the input buffer shown in FIG.

FIG. 11 is a circuit diagram showing a configuration of the inverter shown in FIG.

FIG. 12 is a circuit block diagram showing a configuration of an input buffer of another conventional semiconductor integrated circuit device.

[Explanation of symbols]

1 voltage generating circuit, 2, 13, 14, 18, 24, 2
5, 38, 39, 41, 58 P-channel MOS transistors, 3, 4, 7, 8, 10, 11, 15 to 17, 2
6, 27, 40, 42, 43, 59 to 61 N-channel MOS transistor, 5 resistance element, 12 NOR gate, 20 to 23, 28, 30 to 37, 44, 54 to 57
Inverter, 50 semiconductor integrated circuit device, 51.1-
51. m input buffer, 53.1-53. n output buffer, 62 signal generation circuit.

Claims (8)

[Claims] 1. An input circuit of a semiconductor device, which generates an internal signal according to an external signal and provides the internal signal to an internal circuit, wherein the input circuit is connected between a first power supply node and an output node from which the internal signal is output. An electrode connected to a first transistor of a first conductivity type receiving the external signal, between a second power supply node and the output node;
A second transistor of a second conductivity type whose input electrode receives the external signal; a third transistor of a second conductivity type whose first electrode is connected to the output node and whose input electrode receives the external signal; A fourth transistor of a second conductivity type connected between a second electrode of the third transistor and the second power supply node, and between the first and second power supply nodes When the given power supply voltage is the first voltage value, the fourth transistor is turned off. When the power supply voltage is the second voltage value different from the first voltage value, the fourth transistor is turned off.
And control means for turning on the transistor when the power supply voltage is a voltage value between the first and second voltage values, with a conductive resistance value corresponding to the voltage value. , An input circuit of a semiconductor device. 2. The input circuit of a semiconductor device according to claim 1, wherein said control means steps down said power supply voltage by a predetermined voltage and inputs it to said fourth transistor. 3. An input circuit of a semiconductor device, which generates an internal signal according to an external signal and supplies the internal signal to an internal circuit, wherein each of the input circuits is connected between a first power supply node and an input node at a subsequent stage, and an input electrode thereof is provided. A first transistor of a first conductivity type connected to the output node of the preceding stage, and a first transistor connected between the second power supply node and the input node of the following stage;
A plurality of serially connected inverters, the input electrodes of which include a second transistor of the second conductivity type connected to the output node of the preceding stage, wherein the first stage receives the external signal and the final stage outputs the internal signal; A third transistor of a second conductivity type connected between an output node of a certain inverter other than the first one of the plurality of inverters and the second power supply node, and an output voltage of a preceding inverter of the certain inverter; Is a first voltage value, the third transistor is turned off, and if the output voltage is a second voltage value different from the first voltage value, the third transistor is turned on. An input circuit of a semiconductor device, comprising: 4. The control means according to claim 3, wherein said control means steps down an output voltage of an inverter preceding said certain inverter by a predetermined voltage and inputs the reduced voltage to said third transistor.
3. The input circuit of a semiconductor device according to claim 1. 5. An input circuit of a semiconductor device, which generates an internal signal according to an external signal and provides the internal signal to an internal circuit, wherein the external signal is applied when the external signal transitions from a first logical potential to a second logical potential. Delay for the first time,
A first delay circuit that delays by a second time shorter than the first time when the external signal transitions from the second logical potential to the first logical potential; When the external signal has transitioned from the logical potential to the first logical potential, the external signal is delayed by the first time, and when the external signal has transitioned from the first logical potential to the second logical potential, A second delay circuit that delays by a third time shorter than the first time, and an output signal of the first and second delay circuits, and a slower one of them is used as the internal signal. An input circuit of a semiconductor device, comprising: a gate means for giving the internal circuit. 6. The gate means is connected in series between a first power supply node and an output node to which the internal signal is output, and each input electrode is connected to an output of the first and second delay circuits, respectively. First and second transistors of a first conductivity type for receiving a signal;
Are connected in series between the power supply node and the output node,
Third and fourth conductive types, each of which receives an output signal of the second and first delay circuits, respectively.
The input circuit of the semiconductor device according to claim 5, comprising: 7. An input circuit of a semiconductor device, which generates an internal signal according to an external signal and provides the internal signal to an internal circuit, wherein when the external signal transitions from a first logical potential to a second logical potential, the external signal is output. Delay for the first time,
A first delay circuit that delays by a second time longer than the first time when the external signal transitions from the second logical potential to the first logical potential; When the external signal has transitioned from the logical potential to the first logical potential, the external signal is delayed by the first time, and when the external signal has transitioned from the first logical potential to the second logical potential, A second delay circuit that delays by a third time longer than the first time, and an output signal of the first and second delay circuits, and an earlier signal among them is used as the internal signal. An input circuit of a semiconductor device, comprising: a gate means for giving the internal circuit. 8. The gate means is activated in response to a transition of the external signal from the first logic potential to the second logic potential, and outputs an output signal of the first delay circuit to the internal circuit. The first to be transmitted as a signal
And the second signal, which is activated in response to the transition of the external signal from the second logic potential to the first logic potential, and transmits the output signal of the second delay circuit as the internal signal The input circuit of a semiconductor device according to claim 7, comprising: