JPH08288239A - Oxygen-diffusion barrier type electrode and manufacture thereof - Google Patents

Oxygen-diffusion barrier type electrode and manufacture thereof

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Publication number
JPH08288239A
JPH08288239A JP8918495A JP8918495A JPH08288239A JP H08288239 A JPH08288239 A JP H08288239A JP 8918495 A JP8918495 A JP 8918495A JP 8918495 A JP8918495 A JP 8918495A JP H08288239 A JPH08288239 A JP H08288239A
Authority
JP
Japan
Prior art keywords
diffusion barrier
oxygen
electrode
semiconductor
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8918495A
Other languages
Japanese (ja)
Other versions
JP2751864B2 (en
Inventor
Taku Hase
卓 長谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
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Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP7089184A priority Critical patent/JP2751864B2/en
Publication of JPH08288239A publication Critical patent/JPH08288239A/en
Application granted granted Critical
Publication of JP2751864B2 publication Critical patent/JP2751864B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE: To avoid poor contact of a polycrystalline Si or Si barrier layer connected to a lower electrode due to oxidation to form an oxide dielectric film. CONSTITUTION: The crystal grain boundary of a Pt or other precious metal thin film generally exists perpendicularly to the surface of a substrate. A metal serving as a barrier against the diffusion of oxygen is placed on the grain boundary to avoid diffusing oxygen, thereby preventing poor electric contact of a polycrystalline Si or Si barrier layer laid beneath the precious metal.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体表面に形成した電
極構造及びその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrode structure formed on a semiconductor surface and a method for manufacturing the same.

【0002】[0002]

【従来の技術】従来より、強誘電体などの酸化物誘電体
をキャパシタとして半導体集積回路中に組み込もうとす
る場合、多くの酸化物誘電体の作製時に必要な500℃
以上の高温と酸化性雰囲気によってキャパシタ用下部電
極として用いられた多結晶シリコンが酸化されコンタク
ト不良が発生してしまうという問題があった。そこで多
くの場合図3の様に下部電極として耐熱性、耐酸化性の
高いPtなどの高融点貴金属が用いられる。つまり、高
融点貴金属層1の下にTiNなどのシリコンバリア層2
を配置することにより高融点貴金属のシリサイド化を防
ぎ酸化物誘電体作製に耐えうる電極として用いられてい
る。導電性酸化物電極も酸化雰囲気に対して安定である
ため、その下にシリコンバリア層を備えてシリサイド化
を防ぐことによって使用する事が検討されている。
2. Description of the Related Art Conventionally, when an oxide dielectric such as a ferroelectric is to be incorporated into a semiconductor integrated circuit as a capacitor, a temperature of 500.degree.
Due to the above high temperature and oxidizing atmosphere, there is a problem that the polycrystalline silicon used as the lower electrode for the capacitor is oxidized and a contact failure occurs. Therefore, in many cases, as shown in FIG. 3, a high melting point noble metal such as Pt having high heat resistance and oxidation resistance is used as the lower electrode. That is, a silicon barrier layer 2 such as TiN is formed under the high melting point noble metal layer 1.
Is used as an electrode that can prevent the refractory noble metal from being silicidized and can withstand the production of an oxide dielectric. Since the conductive oxide electrode is also stable against an oxidizing atmosphere, it is considered to use it by providing a silicon barrier layer thereunder to prevent silicidation.

【0003】[0003]

【発明が解決しようとする課題】しかしながら従来の下
部電極構造には次のような問題点があった。Ptなどの
高融点貴金属を用いる場合は、高融点金属薄膜の結晶粒
界を酸素が透過することが可能で、酸化物誘電体作製時
に高融点貴金属の下のシリコンバリア層として使用され
ているTiNが酸化され絶縁性の酸化チタンが形成され
シリコン基板側との導通不良が発生してしまう。また導
電性酸化物を使用する場合もシリコンバリアのTiN上
に導電性酸化物を作製する時点でTiNが酸化されてし
まいやはり導通不良が発生し問題の解決にはならなかっ
た。
However, the conventional lower electrode structure has the following problems. When a high melting point noble metal such as Pt is used, oxygen can pass through the crystal grain boundaries of the high melting point metal thin film, and TiN is used as a silicon barrier layer under the high melting point noble metal when forming an oxide dielectric. Is oxidized to form insulative titanium oxide, resulting in poor conduction with the silicon substrate side. Further, even when a conductive oxide is used, TiN is oxidized at the time of forming the conductive oxide on TiN of the silicon barrier, and conduction failure still occurs, which cannot solve the problem.

【0004】本発明の目的は、上記問題点を解決できる
電極構造を提供することにある。
An object of the present invention is to provide an electrode structure which can solve the above problems.

【0005】[0005]

【課題を解決するための手段】本発明は半導体表面と電
気的接触を行う電極において、該半導体表面上に形成し
た半導体拡散バリア層上に積層した多結晶高融点貴金属
層の結晶粒界に酸素拡散バリア部を設けたことを特徴と
する酸素拡散バリア性電極である。ここで上記酸素拡散
バリア部はTi、Zr、Ta、Ruのいずれか1種もし
くは複数種類を組み合わせた金属の酸化物からなること
が好ましい。又この酸化拡散バリア性電極の製造方法
は、半導体表面に半導体拡散バリア層を形成し、該半導
体拡散バリア層上にTi、Zr、Ta、Ruのいずれか
1種もしくは複数種類を組み合わせた金属層を挟んで多
結晶高融点貴金属層を形成した後、非酸化雰囲気中で4
50〜650℃で熱処理する工程を有することを特徴と
する。ここで、さらに高融点金属層上に析出した上記バ
リア性金属を除去する工程を有していてもよい。
According to the present invention, in an electrode which makes electrical contact with a semiconductor surface, oxygen is present in a crystal grain boundary of a polycrystalline refractory noble metal layer laminated on a semiconductor diffusion barrier layer formed on the semiconductor surface. An oxygen diffusion barrier electrode having a diffusion barrier portion. Here, it is preferable that the oxygen diffusion barrier portion is made of an oxide of a metal in which one kind or a combination of plural kinds of Ti, Zr, Ta and Ru is combined. Further, in this method for manufacturing an oxidation diffusion barrier electrode, a semiconductor diffusion barrier layer is formed on a semiconductor surface, and any one kind or a combination of plural kinds of Ti, Zr, Ta and Ru is formed on the semiconductor diffusion barrier layer. After forming a polycrystalline high melting point noble metal layer sandwiching the
It is characterized by having a step of heat treatment at 50 to 650 ° C. Here, a step of further removing the barrier metal deposited on the high melting point metal layer may be included.

【0006】[0006]

【作用】本発明による電極構造を高融点金属としてPt
を用いた例を図1に示す。Ptはスパッタ法などで作製
される場合、特別な基板を選ばない限り多結晶膜となり
結晶粒は柱状構造となる。Pt上に酸化物誘電体を作製
する場合この柱状のPtの結晶粒界を通して酸素が拡散
してPtの下のTiNなどのシリコンバリアを酸化して
コンタクト不良が発生する。このように酸素の拡散は粒
界が主要なパスであるためこの粒界に酸化される前は酸
素に対してトラップとして機能し、酸化された後は酸素
の拡散に対して障壁として機能する酸素バリア性の金
属、例えばTiを配置すれば酸素の粒界拡散を抑えるこ
とができ、結果的にTiNの酸化を抑制できる。またP
tの結晶粒界は基板面に垂直に形成されているため、こ
の部分に酸素バリア性の金属の酸化物が存在しその酸化
物が絶縁性であってもコンタクト抵抗を増大させること
はないため、導電性酸化物となる金属、例えばRu、の
ほかに絶縁性の酸化物となる金属、たとえばZr、Ta
等を用いることが可能である。
The electrode structure according to the present invention uses Pt as a refractory metal.
An example using is shown in FIG. When Pt is produced by a sputtering method or the like, it becomes a polycrystalline film unless the special substrate is selected, and the crystal grains have a columnar structure. When an oxide dielectric is formed on Pt, oxygen diffuses through the crystal grain boundaries of the columnar Pt and oxidizes a silicon barrier such as TiN under Pt to cause contact failure. In this way, since the grain boundary is the main path for diffusion of oxygen, oxygen that functions as a trap for oxygen before being oxidized at this grain boundary and oxygen that functions as a barrier for oxygen diffusion after being oxidized. By disposing a metal having a barrier property, for example, Ti, the grain boundary diffusion of oxygen can be suppressed, and as a result, the oxidation of TiN can be suppressed. Also P
Since the grain boundary of t is formed perpendicularly to the substrate surface, an oxide of a metal having an oxygen barrier property exists in this portion, and even if the oxide is insulating, it does not increase the contact resistance. , A metal serving as a conductive oxide such as Ru, and a metal serving as an insulating oxide such as Zr and Ta.
Etc. can be used.

【0007】[0007]

【実施例】【Example】

(実施例1)図2は高融点貴金属としてPt、酸素バリ
ア性金属としてTiを用いた場合の下部電極及びキャパ
シタ作製時の各段階での深さ方向の組成分析結果を示し
たものである。図2(a)では基板側から多結晶シリコ
ン、TiN/Ti積層シリコンバリア層、厚さ20nmの
Ti酸素拡散バリア層、同じく200nmのPt層を示し
た。図2(a)の構造を500℃窒素中で30分熱処理
したところ図2(b)に示す様にPtの下のTi層はP
t層中とPt表面に拡散した。このとき試料の断面を高
分解能電子顕微鏡で観察すると、拡散したTiはPtの
表面と結晶粒界に析出していることが観察された。Pt
表面に析出したTiをエッチング除去した後に酸化物誘
電体としてジルコン酸チタン酸鉛(PZT)をゾルゲル
法で600℃で60分の熱処理で作製した。PZT作製
後の組成分析結果は図2(c)の様になり、Pt粒界に
存在するTiはPt表面近傍では酸化されていることが
分かったが、TiN側のPt粒界のTiは酸化されてお
らずTiN層も酸化されていないことが示された。この
電極構造をイオンミリング法により10μm ×10μm
に微細加工しコンタクト抵抗を測定したところ、30〜
50Ωとなり下部電極としての導通に問題がないことが
確認された。必要なPt膜厚は酸化雰囲気中の熱処理時
間と温度に依存したが、600℃以下でかつ60分以下
の熱処理ならば150nm以上が望ましく、150nm以下
ではコンタクト抵抗値が増大する傾向が見られた。
(Embodiment 1) FIG. 2 shows the results of composition analysis in the depth direction at each stage of manufacturing the lower electrode and the capacitor when Pt is used as the refractory metal and Ti is used as the oxygen barrier metal. In FIG. 2A, from the substrate side, polycrystalline silicon, a TiN / Ti laminated silicon barrier layer, a Ti oxygen diffusion barrier layer having a thickness of 20 nm, and a Pt layer having a thickness of 200 nm are shown. When the structure of FIG. 2 (a) was heat-treated in nitrogen at 500 ° C. for 30 minutes, the Ti layer under Pt showed P as shown in FIG. 2 (b).
It diffused in the t layer and on the Pt surface. At this time, when the cross section of the sample was observed with a high resolution electron microscope, it was observed that the diffused Ti was deposited on the surface of Pt and on the crystal grain boundaries. Pt
After the Ti deposited on the surface was removed by etching, lead zirconate titanate (PZT) was prepared as an oxide dielectric by heat treatment at 600 ° C. for 60 minutes by the sol-gel method. The composition analysis result after PZT fabrication is as shown in FIG. 2C, and it was found that Ti existing in the Pt grain boundary was oxidized near the Pt surface, but Ti in the Pt grain boundary on the TiN side was oxidized. It was shown that the TiN layer was not oxidized and the TiN layer was not oxidized. This electrode structure is 10μm x 10μm by ion milling method
When microfabrication was performed and contact resistance was measured,
It was confirmed to be 50Ω and there was no problem in conduction as the lower electrode. The required Pt film thickness depended on the heat treatment time and temperature in an oxidizing atmosphere, but if the heat treatment is 600 ° C. or less and 60 minutes or less, 150 nm or more is desirable, and at 150 nm or less, the contact resistance value tends to increase. .

【0008】(実施例2)高融点貴金属としてIr、酸
素バリア性金属としてTiを用いた場合を説明する。作
製方法は実施例1と同様で基板側から多結晶シリコン、
TiN/Ti積層シリコンバリア層、厚さ20nmのTi
酸素拡散バリア層、同じく200nmのIr層を成膜した
後、この構造を650℃窒素中で30分熱処理すること
によりIrの下のTi層はIrの粒界を拡散しIr粒界
とIr表面に析出した。Ir表面に析出したTiをエッ
チング除去した後に酸化物誘電体としてジルコン酸チタ
ン酸鉛(PZT)をゾルゲル法で600℃で作製し、P
ZTを除去した部分をイオンミリング法により10μm
×10μm に微細加工しコンタクト抵抗を測定したとこ
ろ、50〜100Ωとなり下部電極としての導通に問題
がないことが確認された。Ir電極の場合Ir表面が6
00℃酸素中で酸化されたが、IrO2 は導電性酸化物
であり電極の導電性を妨げることはなかった。Ir電極
の場合、酸素バリア性金属を粒界拡散させるのに必要な
温度がPt電極を用いた場合より100〜150℃程度
高かった。
(Example 2) The case where Ir is used as the high melting point noble metal and Ti is used as the oxygen barrier metal will be described. The manufacturing method is the same as in Example 1, and the polycrystalline silicon is
TiN / Ti laminated silicon barrier layer, 20 nm thick Ti
After depositing an oxygen diffusion barrier layer, which is also an Ir layer of 200 nm, and heat-treating this structure in nitrogen at 650 ° C. for 30 minutes, the Ti layer under Ir diffuses the grain boundaries of Ir and the Ir grain boundaries and the Ir surface. Deposited on. After removing Ti deposited on the Ir surface by etching, lead zirconate titanate (PZT) was prepared as an oxide dielectric by a sol-gel method at 600 ° C.
The part where ZT is removed is 10 μm by the ion milling method.
When the contact resistance was measured by microfabrication to × 10 μm, it was found to be 50 to 100 Ω and there was no problem in conduction as the lower electrode. In case of Ir electrode, Ir surface is 6
Although oxidized in oxygen at 00 ° C., IrO 2 was a conductive oxide and did not interfere with the conductivity of the electrode. In the case of the Ir electrode, the temperature required for diffusing the oxygen barrier metal at the grain boundaries was about 100 to 150 ° C. higher than that in the case of using the Pt electrode.

【0009】表1はPtもしくはIr電極と、各種の酸
素バリア性金属を用いた各組み合わせによるコンタクト
抵抗を示している。Zr、Ta、Ruの各元素でコンタ
クト抵抗値は下部電極として使用する上で問題のない値
となった。
Table 1 shows the contact resistance of each combination of Pt or Ir electrodes and various oxygen barrier metals. The contact resistance value of each element of Zr, Ta, and Ru was a value that causes no problem when used as the lower electrode.

【0010】[0010]

【表1】 [Table 1]

【0011】[0011]

【発明の効果】半導体表面上から電気的接触をとる多結
晶高融点貴金属において、多結晶高融点貴金属の柱状結
晶の粒界に酸素拡散バリア部を設けることにより、その
結晶粒界を介して半導体表面と高融点貴金属電極間に拡
散する酸素の侵入を防ぎ、電気的導通は結晶粒界以外の
結晶部分で確保することにより、半導体表面上に、導電
性の良好な多結晶高融点貴金属電極を実現できる。
EFFECTS OF THE INVENTION In a polycrystalline high melting point noble metal which makes electrical contact from the semiconductor surface, an oxygen diffusion barrier portion is provided at the grain boundary of the columnar crystal of the polycrystalline high melting point noble metal, so that the semiconductor can be connected through the grain boundary. A polycrystalline high melting point noble metal electrode with good conductivity is provided on the semiconductor surface by preventing the diffusion of oxygen that diffuses between the surface and the high melting point noble metal electrode and ensuring electrical continuity at crystal parts other than the crystal grain boundaries. realizable.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明による高融点貴金属粒界に酸素バリア性
金属を配置した下部電極構造を示す図である。
FIG. 1 is a diagram showing a lower electrode structure in which an oxygen barrier metal is arranged at a refractory noble metal grain boundary according to the present invention.

【図2】高融点貴金属としてPt、酸素バリア性金属と
してTiを用いた場合の下部電極及びキャパシタ作製時
の各段階での深さ方向の組成分析結果である。
FIG. 2 is a result of composition analysis in the depth direction at each stage of manufacturing a lower electrode and a capacitor when Pt is used as a high melting point noble metal and Ti is used as an oxygen barrier metal.

【図3】従来の酸素バリア性金属を用いない場合の下部
電極構造を示す図である。
FIG. 3 is a diagram showing a lower electrode structure when a conventional oxygen-barrier metal is not used.

【符号の説明】[Explanation of symbols]

1 Pt下部電極(高融点貴金属層) 2 TiN/Ti積層シリコンバリア層 3 多結晶シリコン 4 Ti(酸素バリア性金属) 1 Pt lower electrode (high melting point noble metal layer) 2 TiN / Ti laminated silicon barrier layer 3 Polycrystalline silicon 4 Ti (oxygen barrier metal)

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】半導体表面と電気的接触を行う電極におい
て、該半導体表面に設けられた半導体拡散バリア層上に
積層された多結晶高融点貴金属層の結晶粒界に酸素拡散
バリア部を設けたことを特徴とする酸素拡散バリア性電
極。
1. An electrode for making electrical contact with a semiconductor surface, wherein an oxygen diffusion barrier portion is provided at a crystal grain boundary of a polycrystalline refractory noble metal layer laminated on a semiconductor diffusion barrier layer provided on the semiconductor surface. An oxygen diffusion barrier electrode characterized by the above.
【請求項2】酸素拡散バリア部がTi、Zr、Ta、R
uのいずれか1種もしくは複数種類を組み合わせた金属
の酸化物からなることを特徴とする請求項1記載の酸素
拡散バリア性電極。
2. The oxygen diffusion barrier portion comprises Ti, Zr, Ta and R.
2. The oxygen diffusion barrier electrode according to claim 1, which is made of a metal oxide in which any one or a combination of u is combined.
【請求項3】半導体表面に半導体拡散バリア層を形成
し、該半導体拡散バリア層上にTi、Zr、Ta、Ru
のいずれか1種もしくは複数種類を組み合わせた金属層
を挟んで多結晶高融点貴金属層を形成した後、非酸化雰
囲気中で450〜650℃で熱処理する工程を有するこ
とを特徴とする酸素拡散バリア性電極の製造方法。
3. A semiconductor diffusion barrier layer is formed on a semiconductor surface, and Ti, Zr, Ta, Ru is formed on the semiconductor diffusion barrier layer.
An oxygen diffusion barrier comprising a step of forming a polycrystalline refractory noble metal layer with a metal layer formed by sandwiching one or a combination of two or more of the above and then performing heat treatment at 450 to 650 ° C. in a non-oxidizing atmosphere. Of manufacturing a conductive electrode.
【請求項4】非酸化雰囲気中で450〜650℃で熱処
理した後、高融点金属層上に析出した上記バリア性金属
を除去する工程を有することを特徴とする請求項3記載
の酸素拡散バリア性電極の製造方法。
4. The oxygen diffusion barrier according to claim 3, further comprising a step of removing the barrier metal deposited on the refractory metal layer after heat treatment at 450 to 650 ° C. in a non-oxidizing atmosphere. Of manufacturing a conductive electrode.
JP7089184A 1995-04-14 1995-04-14 Oxygen diffusion barrier electrode and its manufacturing method Expired - Lifetime JP2751864B2 (en)

Priority Applications (1)

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Application Number Priority Date Filing Date Title
JP7089184A JP2751864B2 (en) 1995-04-14 1995-04-14 Oxygen diffusion barrier electrode and its manufacturing method

Publications (2)

Publication Number Publication Date
JPH08288239A true JPH08288239A (en) 1996-11-01
JP2751864B2 JP2751864B2 (en) 1998-05-18

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JP (1) JP2751864B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10242399A (en) * 1997-02-27 1998-09-11 Samsung Electron Co Ltd High-dielectric capacitor and its manufacturing method
JP2001036029A (en) * 1999-06-28 2001-02-09 Hyundai Electronics Ind Co Ltd Semiconductor device for use in memory cell and its manufacture
US6239462B1 (en) 1997-07-24 2001-05-29 Matsushita Electronics Corporation Semiconductor capacitive device having improved anti-diffusion properties and a method of making the same
US7763921B2 (en) 2006-11-14 2010-07-27 Fujitsu Semiconductor Limited Semiconductor device and manufacturing method thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH077137A (en) * 1993-01-27 1995-01-10 Texas Instr Inc <Ti> Microelectronics structure and preparation thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH077137A (en) * 1993-01-27 1995-01-10 Texas Instr Inc <Ti> Microelectronics structure and preparation thereof

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10242399A (en) * 1997-02-27 1998-09-11 Samsung Electron Co Ltd High-dielectric capacitor and its manufacturing method
US6239462B1 (en) 1997-07-24 2001-05-29 Matsushita Electronics Corporation Semiconductor capacitive device having improved anti-diffusion properties and a method of making the same
US6809000B2 (en) 1997-07-24 2004-10-26 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same
JP2001036029A (en) * 1999-06-28 2001-02-09 Hyundai Electronics Ind Co Ltd Semiconductor device for use in memory cell and its manufacture
US7763921B2 (en) 2006-11-14 2010-07-27 Fujitsu Semiconductor Limited Semiconductor device and manufacturing method thereof
US8110411B2 (en) 2006-11-14 2012-02-07 Fujitsu Semiconductor Limited Semiconductor device and manufacturing method thereof
US8367428B2 (en) 2006-11-14 2013-02-05 Fujitsu Semiconductor Limited Semiconductor device and manufacturing method thereof

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