JPH0828735B2 - Multiple data link - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention provides various sensors and actuators used in various industrial machines, NC machines, automated guided vehicles, robots, etc., in a central processing unit in a controller for control. The present invention relates to an erroneous output suppressing device for a multiple data link that is centrally managed by using a single data link.

[Conventional technology]

FIG. 8 shows the overall structure of a conventional multiple data link.

That is, in FIG. 8, 10 is a machine controller that integrally controls the target machine as a control controller, 2-1, 2-2, 2-3, ..., 2-n are provided in each part of the machine. Sensor or actuator, 30
Arranged in the machine controller 10 as a central processing unit
LAN (Local Area Network) controller, 4
-1, 4-4, 4-3, ..., 4-n are arranged corresponding to each of a plurality of sensors or actuators 2-1 to 2-n, and various data (sensor data or actuator control data) are described above. It is a LAN controller that performs relay processing with the LAN controller 30. As described above, in this multiple data link, the LAN controller 3 as a central processing unit is used.
0 and LAN controllers 4-1 to 4- as peripheral processing devices
and n are connected in series in a ring shape.

Further, FIG. 9 shows an example of a protocol of the signals S _{0 to} Sn transmitted between the LAN controllers 30 and 4-1 to 4-n in such a multiplex data link.

In this example, the signals S _{0 to} Sn are a data string consisting of sensor data indicating sensor output from each sensor or a column of control data indicating control content for controlling the driving mode of each actuator, and this data. A start code, which is arranged immediately before the column and indicates the beginning of the data string with a predetermined logical structure of a plurality of bits, and a plurality of bits, which is arranged immediately after the data string and similarly has a predetermined logical structure (the logical structure of the start code, The stop code that indicates the end of the same data string and the above LA for detecting the occurrence of an error between each port (between each LAN controller)
Each of the N controllers 4-1 to 4-n is provided with an error check code which is individually generated and added immediately after the stop code as a code signal having a predetermined number of bits. In 30, 4-1 to 4-n, the existence of data (data string) is known based on the start code and the stop code and detection, and the presence or absence of an error is known based on the inspection of the error check code.

[Problems to be Solved by the Invention]

In such a multiplex data link, by adopting a signal having the above-mentioned protocol as a signal transmitted between the respective LAN controllers 4-1 to 4-n, it is sure that this will be done for the data transfer and the error check. Can be effectively achieved, but within the LAN controllers 4-1 to 4-n, there is a 1-bit loss in the data string or 1
Even if an abnormality such as bit addition occurs, there is no ability to detect the abnormality and incorrect data transmission is performed.

The present invention has been made in view of the above circumstances, and an object of the present invention is to detect an abnormal bit when a bit abnormality of a data string occurs inside a peripheral processing device and to perform erroneous data transmission. It is possible to provide a multiple data link capable of preventing the above.

[Means for Solving the Problems] In order to achieve the above-mentioned object, the present invention provides a method of communicating data of a plurality of sensors or actuators with one central processing unit and centrally managing the data. In response to each sensor or actuator of the above, the contents of this error check code are inspected with the input of a signal having at least an error check code transmitted together with the above-mentioned data in order to check whether or not an error has occurred. A peripheral processing unit that transmits and receives each data to and from each corresponding sensor or actuator and outputs the signal while monitoring the presence or absence of occurrence is provided, and these peripheral processing units are connected via the central processing unit. In the data link and for each of the peripheral processing devices, check whether the number of bits of the data string is normal, and In the error check method of the multiple data link provided with means for adding an error code to the transmission data when a bit abnormality is detected in the data string, the number of bits of the data string is doubled and the number of bits of the data string and stop code Is provided with a data string length inspection circuit for checking whether or not is even.

[Work]

It is checked whether the number of bits of the data string is normal, and if a bit abnormality is detected in the data string, an error code is added to the transmission data. At this time, if it is normal, the data string is always transmitted as even bits, and the data string length inspection circuit checks whether or not the number of bits of the data string + stop code is even among the received signals. Then, an abnormality of one bit missing or addition in the data string is detected.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 to 7.

What is shown in FIG. 1 to FIG.
It is a multiple data link proposed in -248881.
Then, FIG. 1 shows an example of a specific configuration of LAN controllers 4-1 to 4-n as respective peripheral processing devices on the premise of the configuration shown in FIG. 8 as a data link. .

Of course, these LAN controllers 4-1 to 4-n all have the same configuration.

The LAN controllers 4-1 to 4-n each receive a signal transmitted from the central LAN controller 30 or the LAN controller in the preceding stage and demodulate the signal as required, and the reception demodulated signal. From the start code detection circuit 402 for detecting the start code indicating the beginning of the data string with a predetermined theoretical structure, and the stop code indicating the end of the data string with a predetermined logical structure from the received and demodulated signal. Based on the stop code detection circuit 403 and the error check code of the reception demodulated signal (generated and output as an error check code generation circuit 407 of the preceding LAN controller as a code for searching for an error) Error check to inspect whether an error has occurred between the previous stage (previous port) and its own stage (local port) Whether or not an error code (which is generated and added through an error code adding circuit 408 of the preceding LAN controller based on the detection of the error occurrence) for notifying the occurrence of an error is added to the path 404 and the received demodulated signal. Error code detection circuit 405 that detects this when monitored and added, error check code inspection circuit 404, error code detection circuit 4
OR circuit OR whose input section is connected to each output side of 05,
A circuit for performing data conversion between the received demodulated signal (correctly, a data string of them) and the sensor or the actuators 2-1 to 2-n. Generates and outputs the sensor data to be transferred in its own stage based on the sensor output of the sensor, and when it is an actuator, generates and outputs the drive signal for driving it based on the control data for each corresponding actuator. A data conversion circuit 406, an error check code generation circuit 407 that newly generates and outputs an error check code based on the reception demodulation signal, and an input / output control of the reception demodulation signal to the error check code generation circuit 407. Generates an error code with the first switch circuit SW1 as necessary (depending on the selection by the second switch circuit SW2 described later) An error code adding circuit 408 for adding this to the received demodulated signal, the received demodulated signal (including this when data is added through the data conversion circuit 406), and the error check code generation circuit 407 are generated and output. A second switch circuit SW2 for selectively outputting either a signal (error check code) or a signal (error code) output from the error code adding circuit 408, and a selective output from the second switch circuit SW2. The required signal is modulated and this signal is transmitted to the next LAN controller or central LAN controller 3
And a transmitting circuit 409 for transmitting the signal to

FIG. 2 is a timing chart showing an operation example of the LAN controller 4-2 among the LAN controllers 4-1 to 4-n.
The signal processing operation executed by the controller will be described in detail.

Here, it is assumed that an error has occurred during signal transmission between the LAN controller 4-1 and the LAN controller 4-2.

Now, the front LAN controller (LAN controller 4-
1) to the next LAN controller (LAN controller 4-
2), there is signal transmission in the mode shown in FIG. 2A, and if this is received and demodulated by the receiving circuit 401,
The start code detection circuit 402 detects the start code of this received signal at the timing shown in FIG. 2 (b) and controls the switching of the first switch circuit SW1 to ON (initially OFF) (second). (See FIG. (G)). As a result, the error check code generation circuit 407 starts an operation of generating an error check code to be transmitted to the next stage LAN controller (LAN controller 4-3) based on the input signal (mainly the data string).

At this point, the second switch circuit SW2
However, as shown in FIG. 2 (h), the terminal 1 input selection state which is the initial state is maintained, and the start code and the data string are directly added to the transmission circuit 409 via the second switch circuit SW2. , Is transmitted and output as a signal S ₂ to the LAN controller 4-3 at the next stage through the transmission circuit 409 (second
See figures (h) and (i)).

During this period, the data conversion circuit 406 executes the above-described data conversion (data generation) operation with each corresponding sensor or actuator 2-2.

The stop code of the signal thus transmitted is then detected at the timing shown in FIG. 2 (c).

When the stop code is detected in this way, the stop code detection circuit 403 controls switching of the first switch circuit SW1 to the initial state of OFF and the second switch circuit SW2 to the terminal 2 input selected state (FIG. 2 (c), (See (g) and (h)).

In response to such switching of the second switch circuit SW2, the second switch circuit SW2
Following the detected stop code, an error check code newly generated by the error check code generation circuit 407 is selectively output from the switch circuit SW2 and transferred through the transmission circuit 409 (FIG. 2 (i)). reference).

In parallel with this, in the error check circuit 404,
The inspection for the error check code 1 transferred from the LAN controller 4-1 in the preceding stage is executed.

As a result, if no data error has occurred, no signal is output from the error check circuit 404. However, as assumed here, when the error check code 1 confirms the occurrence of an error, Simultaneously with this confirmation, an error detection signal which becomes a logic "1" level for a short time is output from the error check circuit 404 (see FIG. 2 (d)). Therefore, during this period (while the error detection signal is being output), the output of the OR circuit OR is also at the logical "1" level.

The output of the OR circuit OR is an error check code transmission completion signal (FIG. 2 (i) and (e)) issued from the error check code generation circuit 407 upon completion of output of the error check code generated by itself. (Refer to FIG. 3), and is added to the second switch circuit SW2.

The second switch circuit SW2 is set to the logic "0" level according to the logic level of the signal added from the OR circuit OR, on condition that the transmission completion signal of the generated code is added from the error check code generation circuit 407. If so, the switch circuit is controlled to switch to the terminal 1 input selection state in the initial state, and to switch to the terminal 3 input selection state if the logic "1" level as in this example. Therefore, in this case, at the same time when the error check code transmission completion signal is issued, the second switch circuit SW2 enters the terminal 3 input selected state, and the signal transferred and output through the transmission circuit 409 includes the error check code generation circuit 407. The error code output from the error code adding circuit 408 is added to the error check code (error check code 2) generated and output in (see FIG. 2 (h) and (i)). ).

After that, when the error code addition circuit 408 completes the addition of the error code, it issues an error code addition completion signal to the second switch circuit SW2 (FIG. 2 (i)).
And (f)), the second switch circuit SW2 is set to the terminal 1 input selection state in the initial state (see FIG. 2 (h)).

With the above operation of the LAN controller 4-2, this L
AN controller 4-2 to the next LAN controller 4-
An error code for notifying that an error has occurred is added to the signal S ₂ transferred and output to the signal No. 3. And LAN
In the controller 4-3 and thereafter, the added error code is detected through the error code detection circuit 405, and the output of the OR circuit OR when the error check code transmission completion signal is issued based on this detection is the same as the above. Set to logical "1" level. With this, LAN controller 4-
Signals to which error codes have been added are also transferred and output from all LAN controllers 3 and later.

FIG. 3 shows the above assumption of the signals S ₀ , S ₁ , S ₂ ... Sn transmitted between the LAN controllers (LAN controller 4-
1 and an error occurs between the LAN controller 4-2) and a protocol based on the above. The above-described operations are repeatedly executed in each of the LAN controllers 4-1 to 4-n. In response to the transmission of the signal S ₀ from the central LAN controller 30 having the form shown in FIG.
From 1 to 4-n, FIG. 3 (b), (c),
(D) and (e) have the form and their respective signals
S ₁ , S ₂ , S ₃ ... Sn will be transmitted.

Then, only the last output signal from the LAN controller 4-n and Sn are taken into the central LAN controller 30. In machine controller 10, this LAN controller 3
It is recognized that an error has occurred in the data link based on the error code added to the signal Sn taken in by 0.

As described above, even when the signals S _{0 to} Sn are transmitted without a time delay between the LAN controllers, that is, the times T _{00 to} Tn ₃ added to the protocol shown in FIG.
For example, even if these are set in the relationship of T ₀₀ = T ₁₁ = T ₂₁ = T ₃₁ = Tn ₁ , the central LAN
It is possible to effectively notify the error to all LAN controllers including the controller 30.

Note that, more generally, T ₁₁ <
The error notification method according to this embodiment is effective when at least the relationship of T ₀₁ , T ₂₁ <T ₁₂ , T ₃₁ <T _22, ... Is maintained.

By the way, according to the above-described embodiment, the central LAN controller 30 (machine controller 10) has an error in the data link based on the error code added to the signal Sn transmitted and output from the LAN controller 4n. LAN controller 4-1 though I can know that
Even if an abnormality such as 1-bit omission or 1-bit addition occurs in the data string within 4 to 4-n, there is no ability to identify the abnormality, and erroneous data transmission is performed.

In view of the above points, FIGS. 4 to 7 show the LAN controller 30 at the center of the error occurrence location.
2 shows a multiple data link according to the present invention, which can be effectively notified to a user.

That is, in this embodiment, as shown in FIG.
In the N controllers 4-1 to 4-n, a data string length inspection circuit 41 for checking whether or not the number of bits of the data string + stop code is an even number among the received signals.
0 is incorporated, and the other structure is similar to that of the multiple data link shown in FIG. Then, the conversion of the data string in the data conversion circuit 406 in the LAN controller 4-n is performed as follows.

(1) Output data string LAN controller 4 as shown in the protocol of FIG.
In -n, 2 bits of the data string of the signal Sn-1 and the signal n are deleted. Table 1 shows the correspondence between the data and the data to be output by the LAN controller 4-n.

The relationship shown in Table 1 is added by the LAN controller 30 shown in FIG.

(2) In case of input data string LAN controller 4 as shown in the protocol of FIG.
In -n, 2 bits are added to the data sequence of the signal Sn-1 and the signal n. Table 2 shows the relationship between 1-bit data input to the LAN controller n and 2-bit data added to the data string.

The data conversion circuit 406 performs the relationship shown in Table 2.

Each LAN controller 4-1 to 4-n sets the fifth data string.
By converting as shown in FIG. 1, Table 1, FIG. 6 and Table 2, in the normal case, the data string is always transmitted as an even bit.

Therefore, if the stop code of the data string in the protocol shown in FIG.
Of the signals received by the data string length inspection circuit 410,
By checking whether the number of bits of the data string + stop code is an even number, an error such as a missing 1 bit or an addition of 1 bit occurs in the LAN controller 4-1 to 4-n. However, the abnormality is detected.

In addition, the correspondence of the data in Table 1 and Table 2 is 1 → 10, 0
→ 01 was converted to 2 bits, but this is an example, and (1 → 1
Various ideas such as (1, 0 → 00), (1 → 10, 0 → 00) can be considered.

In addition to 2-bit conversion, it may be converted into 3-bit data such as (1 → 100, 0 → 001) to check whether the data string is a multiple of 3, or 4-bit conversion to see whether it is an even multiple or a multiple of 4. You may check whether or not.

Furthermore, the data string was deleted or added in the LAN controller in FIGS. 5 and 6, but this shows only one example of a protocol for applying this method. The same can be applied to a protocol in which data strings are neither deleted nor added within 4-n. This protocol is shown in FIG.

Further, this system can be applied to not only those connected in a loop shape as shown in FIG. 8 but also those connected in a digital chain shape where the Sn portion in FIG. 8 is not connected.

Also, in the multiple data link according to the present invention, LAN
The effect is great in detecting a bit abnormality in the controller 4-1, and a bit abnormality that occurs during transmission from the LAN controller 4-1 to the LAN controller 4-2 can also be detected by the error check code inspection circuit. it can.

〔The invention's effect〕

As described above in detail, in the multiplex data link according to the present invention, each peripheral processing device checks whether the number of bits of the data string is normal, and if a bit abnormality is detected in the data string, an error code is transmitted to the transmission data. Peripheral processing is provided by providing means for adding, in particular, by providing a data string length inspection circuit for checking whether or not the number of bits of the data string and the stop code is even, while making the number of bits of the data string into a plurality of bits. When an abnormality such as a missing 1 bit or an addition of 1 bit occurs in the data string inside the device, this abnormal bit can be detected and erroneous data transmission can be prevented. Then, this bit abnormality check can be easily and accurately performed even when it is necessary to transmit the signals to the control target of several thousand points for press or the like substantially equally.

[Brief description of drawings]

FIG. 1 is a block diagram showing a concrete configuration example of a LAN controller which constitutes a peripheral processing device in the embodiment of the multiple data link previously proposed by the applicant, and FIG. 2 is a block diagram showing the LAN controller shown in FIG. FIG. 3 is a timing chart showing an operation example, FIG. 3 is a schematic diagram showing a protocol example of a signal transmitted between LAN controllers in the embodiment, FIG. 4 is a block diagram of a multiple data link according to the present invention, and FIG. 6 is a schematic diagram showing a protocol example of an output data signal, FIG. 6 is a schematic diagram showing a protocol example of an input data signal, FIG. 7 is a schematic diagram showing a protocol example of a signal, and FIG. 8 is multiplex data to which the present invention is applied. FIG. 9 is a block diagram showing the structure of the link, and FIG. 9 is a schematic diagram showing a protocol of a transmission signal in the multiplex data link shown in FIG. 10 …… Machine controller, 2 _{1 to} 2n …… Sensor or actuator, 30,4-1 to 4-n …… LAN controller, 401 …… Reception circuit, 402 …… Start code detection circuit, 403 …… Stop code detection Circuit, 404 ... Error check circuit, 405 ... Error code detection circuit, 406 ... Data conversion circuit, 407 ... Error check code generation circuit, 408 ... Error code addition circuit, 409 ... Transmission circuit,
410 …… Data string length inspection circuit.

Claims (1)

[Claims] 1. When data of a plurality of sensors or actuators is communicated with one central processing unit and is centrally managed, it is determined whether or not an error has occurred for each of the plurality of sensors or actuators. The sensor or actuator corresponding to each data is checked while checking the content of this error check code by inputting a signal having at least an error check code transmitted together with said data for checking and checking whether or not an error has occurred. A peripheral data processing unit for transmitting and receiving data to and from the peripheral device is provided, and a data string is provided to each of the peripheral data processing units by a multiple data link in which these peripheral data processing units are connected via the central processing unit. Check if the number of bits is normal, and if a bit error is detected in the data string, send an error code to the transmission data. In a multiple data link error check method provided with a means for adding, a data string length inspection circuit for checking whether or not the number of bits of the data string and the number of bits of the stop string are even, while making the number of bits of the data string double Multiple data link characterized by being provided.