JPH088579B2 - Series controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention concentrates terminal elements such as sensors and actuators that are widely used in various industrial machines (press machines, various NC machines, robots, etc.) and automated guided vehicles. Regarding a control device to be managed, in particular, the device is integrated with a large number of node controllers that directly extract outputs from data input target terminals (sensors) or output signals to data output target terminals (actuators). The present invention relates to implementation of a signal transmission protocol and a node controller configuration of a serial control device which is divided into a main controller to be managed and which is connected in series to realize centralized management of each terminal.

[Conventional technology]

For example, in a press machine, when it is attempted to electrically control the series of press operations while detecting the state of each part of the machine through various sensors and controlling the drive through an appropriate actuator, these sensors and actuators The number of controls through is enormous (usually, there are 3000 control points). Further, among these many control points, there are not a few that require simultaneity and relevance in the control. Therefore, a control device has been introduced which can centrally manage all of the above-mentioned sensors and actuators and can collectively perform the state detection and state control of each machine part that is required each time.

FIG. 23 shows an example of a conventional control device that realizes such integrated control in a press machine or the like.

In FIG. 23, 10 is a machine controller that centrally controls the target machine as the control device, and 21 to 2n.
Is a sensor or actuator arranged above each part in the machine, and KL is a signal line arranged between the machine controller 10 and the sensors or actuators 21 to 2n.

That is, in the machine shown in FIG. 23, a signal line for signal transmission / reception is arranged between the machine controller 10 and each sensor or actuator 21 to 2n, for example,
If 21 is a sensor and wants that sensor output,
When the data from the sensor 21 is received by the machine controller 10 through the corresponding signal line and is monitored, and when 22 is an actuator and its drive control is executed, the corresponding signal is transmitted. A signal for controlling the drive mode is transmitted from the machine controller 10 to the actuator 22 through a line. The same applies when the sensor output of another sensor is desired or when the drive mode of another actuator is controlled.

Further, FIG. 24 shows another example of the conventional control device which also realizes the above-mentioned integrated control.

That is, in the device shown in FIG. 24, m (m <n) relay controllers are provided between the machine controller 10 and each sensor or actuator 21 to 2n.
31 to 3 m are arranged, and each of these relay controllers 31 to 3 m relays some sensor outputs or actuator drive signals. Even in this case, the basic management mode of the sensor output or the actuator drive signal is the same as that shown in FIG. 23 except that the necessary information for signal exchange is exchanged between the machine controller and the relay controller. It is similar to the example shown in.

[Problems to be Solved by the Invention]

For example, in the device shown in FIG. 23, separate signal lines are arranged between one machine controller and a large number of sensors or actuators to exchange signals for the sensor output monitor or actuator drive control. Since this has been done, the machine controller, which centrally manages sensor outputs or actuator drive signals of these many sensors or actuators, is provided with a very large number of signal lines.

This not only makes it difficult to connect this machine controller to each sensor or actuator, but also causes miswiring.In addition, the bundle of these signal lines is bulky and very heavy. , Its handling was extremely inconvenient.

In the device shown in FIG. 24, the number of signal lines to the machine controller described above can be reduced, and the number of lines as a whole can be shortened, but the total number of signal line lines can be reduced. It does not decrease fundamentally.

Therefore, even when the configuration shown in FIG. 24 is used, the above-mentioned essential problem cannot be solved.

The present invention has been made in view of the above circumstances, and it is possible to simultaneously perform state detection by these sensors and state control by actuators no matter how many terminal elements such as sensors and actuators should be centrally managed. It is an object of the present invention to provide a control device that ensures a rational and highly efficient operation of these terminal elements by drastically reducing the number of wirings, regardless of the need for reliability and relevance.

[Means for solving the problem]

In the present invention, in order to exchange signals between a large number of first terminals (for example, sensors) to be data input targets and second terminals (for example, actuators) to be data output targets and one control means, Corresponding to the first and second terminals, or the first terminal or the second terminal,
The first to n-th plurality of node controllers for directly receiving the output data from the first terminal or outputting the data to the second terminal, each of which is one or a plurality of management units, are provided, and A main controller that controls and manages the first and second terminals is provided corresponding to the control means, and the main controller and the first to nth node controllers are connected in series in a ring shape via signal lines. In addition, with the sequential propagation of the frame signal emitted from the main controller to the first to nth node controllers, the first terminal data accepted by the node controller is taken into the frame signal, or the main controller is received. Through the same frame signal to the corresponding node controller of the output data to the second terminal pre-allocated Ri divided to perform the. Then, at this time, the main controller, in one frame of the frame signal, outputs a first identification code for indicating the start position of the first terminal data and the output data to the second terminal. At least the second identification code for indicating the head position is transmitted, and the node controller transmits the first identification code based on the recognition of the first and second identification codes included in the frame signal. The data is added to the frame signal or the output data from the same frame signal to the corresponding second terminal is extracted.

[Action]

By using such a control device configuration and a protocol for signal transmission / reception, the connection between the main controller and each of the first and second terminals (to be exact, each node controller) is performed by connecting the input line and the output line respectively. It is realized by only two signal lines (substantially one each by the above series connection).

In addition, the main controller is the first or second
In transmitting and receiving a signal (data) to and from the terminal of the above, only one node controller electrically closest to the node controller connected in series with the frame is connected to the above frame. By sending a signal, based on the above-mentioned agreement with each node controller, data input or data output for all terminals to be managed can be automatically and efficiently achieved. Become.

〔Example〕

FIG. 1 shows a basic configuration of a serial controller according to the present invention.

In FIG. 1, reference numeral 10 denotes a machine controller 21S described above for integrally controlling a target machine such as a press.
~ 2nS is a group of sensors that are grouped into 1st to nth groups for a large number of sensors arranged in each part of the machine, 21A to 2nA is a large number of actuators arranged in each part of the target machine. The actuator group 30 is divided into the first to n-th groups, and the machine controller 10 serves as means for collecting sensor data and transmitting actuator control data of the serial controller of the embodiment.
The main controllers, 41 to 4n, which are arranged in the above, serve as data relay means of the serial control device, and each of the nodes of the control system have the sensor group 21S to 2nS and the actuator group 21A.
It is a node controller that directly allocates ~ 2nA and manages them. The main controller 30 and the node controllers 41 to 4n described above are basically connected in series in a ring shape through appropriate signal lines in the manner shown in FIG.

That is, in this serial controller, the main controller
A frame signal (signal SO) having a predetermined form for collecting sensor data and distributing actuator control data is sent from 30 to the node controller 41 electrically closest to this, and each signal of this frame signal is sent. "Node controller 41 → node controller 42 → ...
→ node controller 4n → main controller 30 ", the sensor group data to be managed by each node controller is fetched into the frame signal and is pre-allocated to the same frame signal through the main controller 30. Further, the above-mentioned actuator control data is distributed to each corresponding node controller. As a result, when the frame signal emitted from the main controller 30 as the signal SO is returned to the main controller 30 as the signal Sn, all of the actuator control data collectively mounted on the frame signal corresponds to each The sensor data of all the sensors that are assigned to the node controller and that are to be managed are captured in the same frame signal through the corresponding node controller. In the meantime, in each node controller, for each sensor group to be managed, its sensor output is always captured, and each time the frame signal arrives, the captured sensor output is used as data of a predetermined mode to acquire the sensor signal of the frame signal. The actuator group is added to a predetermined position, and each time the same frame signal arrives, the control data for the actuator group included in the predetermined position is extracted at a predetermined timing and converted into a predetermined actuator drive signal. Then, the drive of each corresponding actuator is actually controlled.

Note that, as a configuration of the serial control device in question, in FIG. 1, for convenience of illustration, <a> all node controllers connected in series to the main controller collectively manage both the sensor group and the actuator group.

Although only the configuration is shown, other than that, <B> a first type node controller that manages both the sensor group and the actuator group together, a second type node controller that manages only the sensor group, and an actuator group only A third type node controller for managing
At least two kinds of node controllers among the kinds of node controllers are mixed and serially connected to the main controller.

<C> All the node controllers connected in series to the main controller manage only the sensor group.

<D> All the node controllers connected in series to the main controller manage only the actuator group.

<E> In the case where all the node controllers connected in series to the main controller manage only the actuator group, the nth node controller 4n at the final stage and the main controller 30 are separated, and so-called daisy chain series connection is made. Becomes

The configuration and the like are also appropriately adopted according to the actual conditions of the target machine.

Further, in the above, as a more general aspect, it is assumed that the sensors or actuators are grouped into several groups and managed by each node controller as a group. However, each of these sensors or actuators is a single node controller. It may be managed by.

Next, with reference to FIG. 2, a signal transfer method between the main controller and each node controller, which is suitable for the serial control device according to the present invention, that is, a protocol for signal transmission will be described.

In each signal frame shown in FIG. 2, "STI", "D"
“I”, “DI _q ”, “STO”, “DO”, “DO _q ”, “SP”, and “ERR” respectively indicate the start position of STI: input data (sensor data). A start code for input data that is added in advance to the same frame from the main controller as a bit string having a predetermined logical structure.

DI: A string of input data taken in the same frame via each node controller.

DI _q : q-th input data (column) captured in the same frame via the q-th node controller.

STO: A start code for output data that is added in advance to the same frame from the main controller as a bit string having a predetermined logical structure different from the above-mentioned "STI" to indicate the start position of the output data (actuator control data).

DO: A string of output data extracted from the same frame via each node controller.

It is output from the main controller following "STO".

DO _q : qth output data (column) extracted from the same frame via the qth node controller.

SP: The same sequence from the main controller as a bit sequence having a predetermined logical structure different from the above “STI” or “STO” to indicate the end position of the data sequence existing in the same frame or to be captured in the same frame. A stop code that is added to the frame in advance.

ERR: A code consisting of a predetermined bit string for prompting the next-stage controller to perform appropriate processing regarding a data error during frame signal transmission, that is, an error processing code. Here, mainly as a code for checking the occurrence of data error during frame signal transmission,
Assume an error check code generated and added by each controller of the main and node based on the contents of the data string transmitted to the next stage.

The details of various protocols implemented in the serial control device will be listed below.

Here, for the sake of convenience, the required node controller structures will be described by taking as an example the data transfer mode implemented in the qth node controller 4q counting from the first node controller 41.

<a> Regarding “STI” and “STO” above, when they are transmitted in the order of “STI” → “STO” in time, “STI” of the input frame signal is detected and immediately after that Input data (sensor data) or input data string "DI _q " is added, and immediately after that, "STO" of the same frame signal is detected and output data (actuator control data) to itself or output data string. A method for determining the node controller structure so as to extract "DO _q " (see FIG. 2 (a)). In this case, "DI" is "STI"
After that, the data from the node controller in the subsequent stage (the distance from the main controller on the signal transmission is far) is taken in sequence, and “DO” continues to “STO”, and then the data in the previous stage (from the main controller on the signal transmission). The output data to the node controller is set in advance.

<B> Similarly, when transmitting in the order of “STI” → “STO”, the “STO” of the input frame signal is detected and immediately before that, the input data of itself or the input data string “DI _q ” is sent. A method of deciding the node controller structure so that the output data to itself or the output data string "DO _q " is extracted immediately after the same "STO" (see FIG. 2 (b)). In this case, "DI" is followed by "STI" and the data from the preceding node controller is sequentially fetched, and "DO" is followed by "STO" and is followed by the output data to the preceding node controller. Is preset.

<C> Similarly, when transmitting in the order of "STI" → "STO", "STO" of the input frame signal is detected and "DI _q " which is its own input data or input data string is added immediately before that. Then, the method of determining the node controller structure so as to detect the "SP" of the same frame signal and extract the output data or the output data string "DO _q " to itself from immediately before that (refer to Fig. 2 (c)). ). in this case,
"DI" is followed by "STI", and the data from the node controller at the previous stage is sequentially fetched, and "DO" is
Subsequent to "STO", the output data to the subsequent node controller is set in reverse order.

<D> Similarly, when transmitting in the order of “STI” → “STO”, the “STI” of the input frame signal is detected and immediately after that, its own input data or the input data string “DI _q ” is added. However, the method of determining the node controller structure so as to detect the "SP" of the same frame signal and extract the output data or the output data string "DO _q " to itself from immediately before that (refer to Fig. 2 (d)). ). in this case,
After "STI", "DI" is sequentially loaded with data from the node controller in the subsequent stage, and "DO" is
Subsequent to "STO", the output data to the subsequent node controller is set in reverse order.

<E> Regarding “STI” and “STO” above, when they are transmitted in the order of “STO” → “STI” in time, the “STO” of the input frame signal is detected and immediately after that Output data or output data string "DO _q "
To detect the "STI" of the same frame signal, and immediately after that, add the input data or the input data string "DI _q ", which is the sequence, to determine the node controller structure (Fig. 2 ( See e)). In this case, "DO"
Continues to "STO", the output data to the previous node controller is set in sequence, and "DI" is
Subsequent to "STI", data from the node controller in the subsequent stage is sequentially fetched.

<F> Similarly, when transmitting in the order of “STO” → “STI”, the “STI” of the input frame signal is detected, and immediately before that, “DO _q ”, which is the input data or output data sequence to itself. Method to determine the node controller structure so that the input data or the input data string “DI _q ” is added immediately after “STI” (second
FIG. (F)). In this case, the output data to the subsequent node controller is set in reverse order to the “DO” following the “STO”, and the “DI” follows the “STI” to the data from the subsequent node controller in order. It is captured.

<G> Similarly, when transmitting in the order of “STO” → “STI”, the “STI” of the input frame signal is detected, and the output data or output data string “DO _q ” is output immediately before that. A method of deciding the node controller structure so that “SP” of the same frame signal is detected and its own input data or input data sequence “DI _q ” is added immediately before that (refer to FIG. 2 (g)). ). in this case,
After "STO", "DO" is preset with the output data to the subsequent node controller, and "DI"
In succession to "STI", the data from the node controller at the previous stage is sequentially fetched.

<H> Similarly, when transmitting in the order of “STO” → “STI”, immediately after detecting “STO” of the input frame signal, output data to itself or “DO _q ” which is an output data string is detected. Method of determining the node controller structure so as to detect "SP" of the same frame signal and add "DI _q " which is its own input data or input data string immediately before that (see Fig. 2 (h)) ). in this case,
After "STO", "DO" is set in advance with the output data to the node controller at the previous stage.
In succession to "STI", the data from the node controller at the previous stage is sequentially fetched.

<I> In particular, in the serial controller configuration shown as <c> above, the main controller 30 selects “STI” and “SP”.
When transmitting only "ERR" and "ERR", the node controller structure is designed to detect the "STI" of the input frame signal and add its own input data or the input data string "DI _q " immediately after that. (See FIG. 2 (i)). In this case, "DI" is sequentially loaded with data from the node controller in the subsequent stage, following "STI".

<J> Similarly, in the configuration of <c>, when only “STI”, “SP” and “ERR” are transmitted from the main controller 30, “SP” of the input frame signal is detected and immediately before that. A method of determining the node controller structure so as to add “DI _q ”, which is its own input data or input data string (see FIG. 2 (j)). in this case,
After "STI", "DI" is sequentially loaded with data from the node controller at the previous stage.

<K> Especially in the serial controller configuration of <d> or <e> described above, the main controller 30 selects “STO”, “D
When only "O", "SP" and "ERR" are transmitted, "STO" of the input frame signal is detected and immediately after that, the output data to itself or the output data string "DO" is output.
A method of determining the node controller structure so that " _q " is extracted (see FIG. 2 (k)). In this case, "DO" is
Subsequent to "STO", the output data to the previous node controller is set in advance.

<L> Similarly, in the configuration of <d> or <e>, from the main controller 30 to “STO”, “DO”, “S”
When transmitting only "P" and "ERR", the node that detects "SP" of the input frame signal and extracts "DO _q " which is the output data or output data sequence to itself immediately before that A method for determining the controller structure (see FIG. 2 (l)). In this case, “DO” is set in advance with output data to the node controller in the subsequent stage in order following “STO”.

In this serial controller, any one of the twelve protocols shown as <a> to <l> above is selectively adopted according to the configurations shown as <a> to <e>. It Even when any one of these protocols is adopted, the required data exchange between the main controller and each node controller that constitutes the serial controller can be achieved well. In practical use, such data exchange between the main controller and each node controller is repeatedly executed in a sufficiently short time period that can smoothly control a series of operations of a target machine such as a press.

Note that, here, an on-off sensor that outputs a 1-bit signal as a logical value "1" or "0" as the sensor, and a 1-bit drive having a logical value "1" or "0" as the actuator. A binary drive actuator that operates in a binary manner based on a signal is assumed. For these reasons, in the embodiment, the “STI”,
When “STO” and “SP” are configured, for example, with a logical structure as shown in Table 1 below, the on-board data (“DI”, “ DI _q ”,“ DO ”,“ D
O _q )) is constructed, for example, as shown in Table 2, and even if these data are arranged in any manner, the "STI", "STO"
And "SP" is properly identified.

If the structures of “STI”, “STO”, and “SP” are as shown in Table 1, the number of consecutive ON data (data of logical value “1”) is less than “5” (preceding node Only when the output of the controller is less than "4",
As the frame mounting data, 1-bit data of "1" or "0" can be used as in the actual data.

As the "ERR", for example, a code having a fixed length of about 16 bits (the content changes according to the content of the data string each time) is prepared.

FIG. 3 is a node controller that manages both a sensor group and an actuator group when adopting the configuration <a> or <b> as a serial controller configuration and the protocol <a> as a protocol. An example of a suitable node controller configuration is shown below.

This node controller 4q, which is assumed to be the q-th node counting from the first node controller 41, has the node controller 4 (q-
An input circuit for inputting a frame signal which is supposed to be appropriately modulated and transmitted from 1) and demodulating it into a desired form.
401, an STI detection circuit 402 for detecting the above-mentioned "STI" having the logical structure as shown in Table 1 from the demodulated frame signal, and the same from the same frame signal as shown in Table 1, for example. The first and second two STO detection circuits 403a and 403b for detecting the above "STO" having the logical structure as described above, and the above-mentioned logical structure as shown in Table 1 from the same frame signal. The first and second two SP detection circuits 404a and 404b for detecting "SP" and the transmission signal from the preceding node controller 4 (q-1) based on the above "ERR" included in the same frame signal An error check circuit 405 for checking whether or not an error has occurred is placed in one path of the same frame signal and serial- (k ×
l) Data extraction circuit 406 for outputting in both forms of bit parallel (k: number of actuators in actuator group 2qA, l: number of data bits per actuator-see Table 2), and input frame The signal (here, the serial output of the data extraction circuit 406) is (i × j)
Bit shift circuit 407 that shifts only bits (i × j)
And (i: the number of sensors in the sensor group 2qS, j: the number of data bits per sensor-see Table 2), and the input frame signal (here, the serial output of the data extraction circuit 406 is the same). The (ERR) based on the (i × j−k × l) bit shift circuit 408 that shifts by (i × j−k × l) bits and the data sequence (“DI”, “DO”) in the frame signal. A new code "ERR '" is generated and output, and "SP" is input from the frame signal input to this.
ERR ′ generation circuit 409 that outputs an ERR ′ transmission completion signal after a bit time of “ERR ′” and an output frame signal as the node controller 4q concerned are modulated as required, and the next-stage node controller 4 is detected. Output data 410 sent to (q + 1) and the sensor output added from the sensor group 2qS are “frame mounted data” as illustrated in Table 2 above.
A data generation circuit 411 for converting the data into a data and outputting the data, and a latch circuit 412 for latching the (k × l) -bit parallel output of the data extraction circuit 406 at a predetermined timing,
The (k × l) -bit data latched by the latch circuit 412 is fetched at a predetermined timing and the actuator group 2q
An actuator drive signal generation circuit 413 that generates and outputs only k actuator drive signals corresponding to the k actuators in A, and a code detection output (here, STI
The “STI” detection output from the detection circuit 402) is received and is delayed by (i × j) bits and is output (i × j) bit delay circuit 414, and the code detection output (here, the first ST).
The "STO" detection output from the O detection circuit 403a) is received and delayed by (k × l−0.5) bits (k × l)
-0.5) The bit delay circuit 415 and the code detection output (here, "SP" detection output by the first SP detection circuit 404a) are also received and delayed by the time T _ERR (bit time of "ERR"). The output T _ERR delay circuit 416, the STI detection circuit 402, (i × j) bit delay circuit 414, (k × l-0.
5) Each output from the bit delay circuit 415, the second STO detection circuit 403b, the T _ERR delay circuit 416, and the second SP detection circuit 404b, the error check completion signal from the error check circuit 405, and the ERR from the ERR ′ generation circuit 409. ′ An internal controller 417 which receives the transmission completion signals and controls the switching of the first to seventh switch circuits SW11 to SW17 in the same node controller 4q, respectively.

In the node controller 4q, the switch circuit SWO has the above-mentioned number of bits (i × j) and (k × l).
When the relation of (i × j) − (k × l) ≧ 0 (1), it is switched to the “0-a” side in advance, and the relation is (i × j) − (k × l). When <0 ... (2), the mode switch is switched to the “0-b” side in advance.

The α bit offset circuit 418 arranged on the “0-b” side of the switch circuit SWO is (i × j) − (k × l) + α = 0 ... (3) The (i × j) bit shift circuits 407 and (i × j−k) are passed through the data extraction circuit 406 by α bits.
Xl) This is a circuit that apparently advances the frame signal applied to the bit shift circuit 408.

Further, the input circuit 401 has an impedance matching circuit, an input amplifier, a demodulation circuit, etc., when signals are exchanged between the controllers electrically via a metal cable (twice spare cable, coaxial cable, etc.). When the signal transmission / reception is optically performed via an optical fiber, the optical / electrical converter and the demodulation circuit (Manchester demodulation circuit, CMI demodulation circuit, etc.) are provided.

On the other hand, the output circuit 410 also has a configuration having a modulation circuit and a driver circuit when the signals are exchanged electrically between the controllers as described above, and when the signals are transmitted and received optically, the modulation circuit is provided. And an electro-optical converter.

The error check circuit 405 is a well-known circuit that performs the error check by a CRC check method, a vertical / horizontal parity check method, or the like.

FIG. 4 shows the node controller 4q shown in FIG.
FIG. 4 is a table showing the input / output logic of the internal controller 417 in FIG. 4 (the internal controller is a circuit in which the control logic is preassembled with the input / output characteristics shown in the table), and as shown in FIG. By way of example, when the above-mentioned formula (1) is satisfied by the switch circuit switching control,
If the SWO is on the "0-a" side, the same node controller 4
With the input of the frame signal, q operates in the manner shown in FIG.

In FIG. 5, the hatched portions are the portions that are selectively output as the elements forming the transmission frame signal to the next-stage node controller 4 (q + 1).

As is clear from FIG. 5, in the node controller 4q shown in FIG. 3, the above (i × j) and (k
By adjusting the phase (time) of the input frame signal according to the bit relationship with xl), the sensor data “DI _q ” is taken in the frame signal and the actuator control data “DO _q ” of Extraction from frame signals and batch execution (execution with some time lags ...) are possible.

The control data “DO _q ” is taken into the actuator drive signal generation circuit 413 only when the normal error check completion signal is output (FIGS. 5 (s) and (q)). As a result, problems such as "erroneous control of the actuator based on abnormal data (error data)" can be satisfactorily avoided.

Although illustration is omitted in FIGS. 3 to 5 for convenience of explanation, when an error occurrence is detected by the error check circuit 405, the error check circuit 405 detects the occurrence of an error through the ERR ′ generation circuit 409 or another circuit. An appropriate code indicating that is added as ERR 'or as a separate code to the output frame signal. In this case, usually, a circuit for detecting the presence of this newly added code portion from the input frame signal is further included.

FIG. 6 shows the node controller 4q shown in FIG.
The transmission transition of the frame signal assuming that the above is applied to the configuration of <A> will be shown for reference.

Similar to FIG. 3, FIG. 7 shows a sensor group and an actuator group when the configuration <a> or <b> is used as the serial controller configuration and the protocol <a> is used as the protocol. 7 shows another example of a node controller configuration suitable as a node controller that manages both of the above.

Note that in FIG. 7, the same circuit elements as those shown in FIG. 3 are designated by the same reference numerals, and duplicate description of these circuit elements will be omitted (described later). The same applies to the explanations after FIG. 11).

By the way, the node controller 4q, which is also in the qth position here, has the input circuit 40a as shown in FIG.
1, STI detection circuit 402, STO detection circuit 403, first and second
SP detection circuits 404a and 404b, error check circuit 40
5, (i × j) bit shift circuit 407, ERR ′ generation circuit 40
9, output circuit 410, data generation circuit 411, latch circuit (provided here has a serial-parallel conversion function) 41
2 ′, actuator drive signal generation circuit 413, (i × j)
In addition to the bit delay circuit 414 and the T _ERR delay circuit 416,
The input frame signal (here, the output signal of the switch circuit SW22) is shifted by (k × 1) bits (k ×
l) The bit shift circuit 420 and the code detection output (here, the “STI” detection output by the STI detection circuit 402 and the “STO” detection output by the STO detection circuit 403) are received and this (k
Xl) bit delay circuit (421) that outputs a delayed signal and a code detection output (here, the “SP” detection output by the second SP detection circuit 404b) are received and this is (T
_ERR + k × l) an amount corresponding to the delay output (T and _ERR + k × l) delay circuit 422, the STI detecting circuit 402, (i × j) bit delay circuit 414, (k × l) bit delay circuit 421, STO detection Each output from the circuit 403, the T _ERR delay circuit 416, the second SP detection circuit 404b, and the (T _ERR + k × l) delay circuit 422, and the error check completion signal from the error check circuit 405, E
An internal controller that receives the ERR 'transmission completion signals from the RR' generation circuit 409 and controls the switching of the first to seventh switch circuits SW21 to SW27 inside the same node controller.
423 and, respectively.

FIG. 8 is a table showing the input / output logic of the internal controller 423 in the node controller 4q shown in FIG. 7, and this node is controlled by the switch circuit switching control shown in FIG. 8 by the internal controller 423. The controller 4q operates in the manner shown in FIG. 9 in response to the input of the frame signal.

In FIG. 9 as well, the hatched portions are the portions that are selectively output as the constituent elements of the transmission frame signal to the next-stage node controller 4 (q + 1).

As is clear from FIG. 9, in the node controller 4q shown in FIG. 7, the phase of the input frame signal is appropriately adjusted, and the sensor data “DI _q ” is first captured in the frame signal. After that, this sensor data “DI
Further adjust the phase of the frame signal captured by " _q ",
It is intended to be a circuit that executes extraction of the actuator control data “DO _q ” from the same frame signal.

Note that the node controller shown in FIG. 3 described above has the same consideration for taking in the control data “DO _q ” to the actuator drive signal generation circuit 413, handling for error occurrence, and the like.

FIG. 10 shows the node controller 4q shown in FIG.
The transmission transition of the frame signal assuming that the above is applied to the configuration of <A> will be shown for reference.

FIG. 11 shows the case where the previous <b> or <c> configuration is adopted as the serial controller configuration and the <a> or <d> or <e> or <f> or <i> protocol is adopted as the protocol. 2 shows an example of a node controller configuration suitable as a node controller that manages only a sensor group.

Again, this node controller 4q, which is supposed to be at the qth position, has input circuits 401, S, as shown in FIG.
TI detection circuit 402, first and second SP detection circuits 404a and 404b, error check circuit 405, (i × j) bit shift circuit 407, ERR ′ generation circuit 409, output circuit 410, data generation circuit 411, (i Xj) bit delay circuit 414, and T
_In addition to the _ERR delay circuit 416, the STI detection circuit 402, (i ×
j) Bit delay circuit 414, T _ERR delay circuit 416, and second S
Each output from the P detection circuit 404b, the error check completion signal from the error check circuit 405, and the ERR ′ generation circuit 40
Receiving the ERR 'transmission signals from 9 respectively, the first to fourth switch circuits SW31 to SW34 in the same node controller are received.
And an internal controller 424 for controlling the switching of the above.

FIG. 12 is a table showing the input / output logic of the internal controller 424 in the node controller 4q shown in FIG. 11, and this node is controlled by the switch circuit switching control as shown in FIG. 12 by the internal controller 424. The controller 4q operates in the manner shown in FIG. 13 with the input of the frame signal.

Also in FIG. 13, the hatched portions are the portions that are selectively output as the elements constituting the transmission frame signal to the next-stage node controller 4 (q + 1).

As is clear from FIG. 13, in the node controller shown in FIG. 11, the “ST
Only "I" and "SP" are detected, and the sensor data "DI _q " is captured immediately after "STI", and the above "STP" and "DO" are present in the same input frame signal. However, these are the same as the next-stage node controller 4
It is passed as a transmission signal to (q + 1).

FIG. 14 shows the configuration of <b>, <d>, or <e> as a serial controller configuration, and the protocol of <a>, <b>, <e>, <h>, or <k> as a protocol. FIG. 3 shows an example of a node controller configuration suitable as a node controller that manages only the actuator group when adopting.

This node controller 4q, which is supposed to be the qth,
As shown in FIG. 14, the input circuit 401, the STO detection circuit
403, SP detection circuit 404, error check circuit 405, data extraction circuit 406, ERR ′ generation circuit 409, output circuit 410, latch circuit 412, actuator drive signal generation circuit 413, (k ×
l) bit shift circuit 420, (k × l−0.5) bit delay circuit 415, T _ERR delay circuit 416, (k × l) bit delay circuit
421 and (T _ERR + k × l) delay circuit 422, in addition to the STO detection circuit 403, (k × l) bit delay circuit 421,
(K × l−0.5) bit delay circuit 415, SP detection circuit 404, T
_ERR delay circuit 416 and (T _ERR + k × l) delay circuit 422
Each output from the device, the error check completion signal from the error check circuit 405, and ERR ′ from the ERR ′ generation circuit 409.
Each of the internal controllers 425 is configured to receive a transmission completion signal and control switching of the first to sixth switch circuits SW41 to SW46 in the same node controller.

FIG. 15 is a table showing the input / output logic of the internal controller 425 in the node controller 4q shown in FIG. 14, and this node is controlled by the switch circuit switching control as shown in FIG. With the input of the frame signal, the controller 4q operates in the manner shown in FIG.

Also in FIG. 16, the hatched portions are the portions that are selectively output as the elements that form the transmission frame signal to the next-stage node controller 4 (q + 1).

As is clear from FIG. 16, the node controller shown in FIG.
By extracting only "O" and "SP", the actuator control data "DO _q " can be extracted from immediately after "STO", and the "STI" and "D
Even if "I" exists, these are passed as they are as a transmission signal to the next stage node controller 4 (q + 1). The mechanism for taking in the control data “DO _q ” to the actuator drive signal generation circuit 413 is the same as the above-mentioned third mechanism.
It is similar to the node controller shown in the figure or FIG.

FIG. 17 shows the case where the configuration of <b> or <c> described above is applied as the serial controller configuration, and the protocol of <b> or <c> or <g> or <h> or <j> is applied as the protocol. 2 shows an example of a node controller configuration suitable as a node controller that manages only a sensor group.

This node controller 4q, which is supposed to be the qth,
As shown in FIG. 17, the input circuit 401, the STI detection circuit
402, SP detection circuit 404, error check circuit 405, (i ×
j) In addition to the bit shift circuit 407, the ERR ′ generation circuit 409, the output circuit 410, the data generation circuit 411, and the (i × j) bit delay circuit 414, the input frame signal is added to the “S”.
A T _SP shift circuit 426 that shifts by a time T _SP that is a bit time of “P” and a code detection output (here, SP detection circuit 404
“SP” detection output) is accepted and this is set as time (T _SP + T
_ERR) by delaying (the T _SP + T _ERR) delay circuits 427, code detection output (here depends on SP detecting circuit 404 "SP" detection output (i × j) by the bit delay circuit 414 (i × j)
T _SP that outputs a signal delayed by a bit) by delaying time T _SP
Delay circuit 428, the STI detection circuit 402, SP detection circuit 404,
(T _SP + T _ERR ) delay circuit 427, (i × j) bit delay circuit
414 and each output from the T _SP delay circuit 428, the error check completion signal from the error check circuit 405, ER
An internal controller that receives the ERR 'transmission completion signals from the R'generation circuit 409 and controls the switching of the first to fourth switch circuits SW51 to SW54 in the same node controller.
429 and, respectively.

FIG. 18 is a table showing the input / output logic of the internal controller 429 in the node controller 4q shown in FIG. 17, and this node is controlled by the switch circuit switching control as shown in FIG. 18 by the internal controller 429. With the input of the frame signal, the controller 4q operates in the manner shown in FIG.

In FIG. 19 as well, the hatched portions are the portions that are selectively output as the constituent elements of the transmission frame signal to the next-stage node controller 4 (q + 1).

As is apparent from FIG. 19, in the node controller shown in FIG. 17, the "ST
Only "I" and "SP" are detected, and the sensor data "DI _q " is captured just before "SP", and the above "STO" and "DO" exist in the same input frame signal. However, these are the same as the next-stage node controller 4
It is passed as a transmission signal to (q + 1).

The node controller 4q shown in FIG. 17 is
Especially when it is adopted in the protocol of <b> or <c>, an STO detection circuit (403) is added separately, and based on the detection of “STO” by this circuit, the sensor data “ The control logic of the internal controller 429 is changed so that “DI _q ” is acquired.

FIG. 20 shows the configuration of <b>, <d>, or <e> as a serial controller configuration, and the protocol of <c>, <d>, <f>, <g>, or <l> as a protocol. FIG. 3 shows an example of a node controller configuration suitable as a node controller that manages only the actuator group when adopting.

Similarly, this node controller is assumed to be the qth
4q is the input circuit 401, the first
And second STO detection circuits 403a and 403b, SP detection circuit 4
04, error check circuit 405, data extraction circuit 406, ER
R ′ generation circuit 409, output circuit 410, latch circuit 412, actuator drive signal generation circuit 413, (k × l−0.5) bit delay circuit 415, T _ERR delay circuit 416, T _SP shift circuit 426, and T _SP delay circuit In addition to 428, it receives a (k × l + T _SP ) delay circuit 430 that delays the input frame signal by (k × l + T _SP ), and a code detection output (here, “SP” detection output by the SP detection circuit 404). And this (k × l + T _SP + T
_ERR ) delay circuit (k × l + T _SP + T _ERR ) delay circuit 431
And the first and second STO detection circuits 403a and 403b, SP
Detection circuit 404, (k × l−0.5) bit delay circuit 415, T _SP
Each output from the delay circuit 428, the (k × l + T _SP + T _ERR ) delay circuit 431, and the T _ERR delay circuit 416, the error check completion signal from the error check circuit 405, and the ERR ′ transmission completion from the ERR ′ generation circuit 409. Accept each signal,
First to seventh switch circuits inside the same node controller
Internal controller 432 that controls the switching of SW61 to SW67
And, respectively.

FIG. 21 is a table showing the input / output logic of the internal controller 432 in the node controller 4q shown in FIG. 20. This node is controlled by the switch circuit switching control as shown in FIG. With the input of the frame signal, the controller 4q operates in the manner shown in FIG.

Also in FIG. 22, the hatched portions are the portions that are selectively output as the constituent elements of the transmission frame signal to the next stage node controller 4 (q + 1).

As is clear from FIG. 22, the node controller shown in FIG.
By extracting only "O" and "SP", the actuator control data "DO _q " can be extracted from immediately before "SP", and the "STI" and "DI" in the same input frame signal can be extracted.
Are present, they are passed as they are as transmission signals to the next-stage node controller 4 (q + 1).

When the node controller 4q shown in FIG. 20 is adopted for the protocol of <f> or <g>, the STI detection circuit (402) is added separately, and the above-mentioned “STI detection circuit” by this circuit is added. The control logic of the internal controller 432 is changed so that the actuator control data “DO _q ” is extracted immediately before based on the detection of “.

In addition, also in this node controller 4q, the actuator drive signal generation circuit 413 of the control data "DO _q "
The mechanism relating to the incorporation into the node controller is the same as that of the node controller shown in FIG. 3 or FIG. 7 or FIG.

As described above, some node controller configurations applied to the serial controller configuration <a> to <e> and the protocols <a> to <l> are shown as an example. Node controllers applied to other combinations omitted above, for example, in the serial controller configuration of <a> or <b>, <b> or <c> or <d> or <e> or <f> or As for the node controller that manages both the sensor group and the actuator group when the protocol of <g> or <h> is adopted, the target code from the input frame signal is the same as that of each node controller illustrated above. ("STI", "STO", "S
This can be easily configured by arbitrary phase adjustment or the like of the same frame signal based on the detection of "P").

The main controller that constitutes the serial controller
Although the illustration of the specific configuration of 30 is omitted, for example, the signal SO is output in the form shown in FIG. 6 (a) or FIG. 10 (a), and FIG. ) Or the
As long as it is a circuit that can take in the signal Sn that is fed back in the manner shown in FIG. 10 (f) (in the daisy-chain configuration of <e>, only the signal SO is output), it is shown in FIG. This can also be arbitrarily and easily configured according to the form of various frame signals. In such a serial control device, the configuration of each node controller is determined according to the protocol relating to signal transfer.

Further, in the above description, the terminal element directly managed by each node controller is the sensor or the actuator, but the terminal element to be data input to the serial control device, or the same serial control. Of course, any other terminal may be used as long as it is a terminal element to which data is output from the device.

〔The invention's effect〕

As described above, according to the present invention, rational and highly efficient operation management of a terminal is realized with a very simple signal line wiring structure.

For this reason, even for a machine having a very large number of terminals, the space for wiring can be reduced, and the machine itself can be downsized.

Each node controller that directly manages the terminal,
Since no address or the like is required, no consideration is given to the signal transmission system even when terminals are added, deleted, or replaced, and the machine can be easily modified.

Many excellent effects such as etc. can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an outline of the configuration of an embodiment of a serial control device according to the present invention, and FIG. 2 is a concept of various frame signal forms and signal transfer protocols adopted in the serial control device. 3 is a schematic diagram showing FIG. 3, FIG. 7 and FIG. 11 and FIG.
FIGS. 17 and 20 are block diagrams showing an example of the configuration of a node controller applied to the same serial controller, and FIG. 4 is an input / output logic of the internal controller in the node controller shown in FIG. 5 is a timing chart showing an example of the operation of the node controller shown in FIG. 3, and FIG. 6 is a diagram showing the operation between the controllers of the serial controller constituted by the direct connection of the node controllers shown in FIG. 8 is a time chart schematically showing the transmission transition of the frame signal in FIG.
FIG. 9 is a chart showing the input / output logic of the internal controller in the node controller shown in FIG. 9, FIG. 9 is a time chart showing an operation example of the node controller shown in FIG.
7 is a time chart schematically showing the transition of frame signal transmission between the controllers of the serial controller constituted by the series connection of the node controllers shown in FIG. 7, and FIG. 12 is the node controller shown in FIG. 13 is a chart showing the input / output logic of the internal controller, FIG. 13 is a time chart showing an operation example of the node controller shown in FIG. 11, and FIG. 15 is an input / output logic of the internal controller in the node controller shown in FIG. Chart showing,
FIG. 16 is a timing chart showing an operation example of the node controller shown in FIG. 14, FIG. 18 is a table showing input / output logic of the internal controller in the node controller shown in FIG. 17, and FIG. 19 is FIG. 21 is a timing chart showing an example of the operation of the node controller shown in Fig. 21, Fig. 21 is a table showing the input / output logic of the internal controller in the node controller shown in Fig. 20, and Fig. 22 is the operation of the node controller shown in Fig. 20. Timing chart showing an example,
FIG. 23 and FIG. 24 are block diagrams each showing an example of a conventional control device. 10 …… Machine controller, 21S to 2nS …… Sensor group, 21
A to 2nA: Actuator group, 30: Main controller, 41 to 4n, 4q: Node controller, 401: Input circuit, 402: STI detection circuit, 403: STO detection circuit, 404 ...
... SP detection circuit, 405 ... error check circuit, 406 ... data extraction circuit, 407 ... (i x j) bit shift circuit, 4
08 …… (i × j−k × l) bit shift circuit, 409 …… E
RR 'generation circuit, 410 ... output circuit, 411 ... data generation circuit, 412 ... latch circuit, 413 ... actuator drive signal generation circuit, 414 ... (i x j) bit delay circuit, 415 ...
… (K × l−0.5) bit delay circuit, 416 …… T _ERR delay circuit, 417,423,424,425,429,432 …… Internal controller, 4
18 …… α bit offset circuit, 420 …… (k × l) bit shift circuit, 421 …… (k × l) bit delay circuit, 4
22 …… (T _ERR + k × l) delay circuit, 426 …… (T _SP shift circuit), 427 …… (T _SP + T _ERR ) delay circuit, 428 …… T _SP delay circuit, 430 …… (k × l + T _SP ) Shift circuit, 431 …… (k
× l + T _SP + T _ERR ) Delay circuit, SWO, SW11 to SW17, SW21 to SW
27, SW31 to SW34, SW41 to SW46, SW51 to SW54, SW61 to SW67 ...
Switch circuit, AD _{1 to} AD ₄ ... AND gate, OR ₁ , OR ₂ ...
OR gate.

Claims (30)

[Claims] 1. The first and second means for transmitting and receiving signals between a large number of first terminals to be data input targets and second terminals to be data output targets and one control means.
Corresponding to the first terminal, the first terminal, or the second terminal, accepting output data from the first terminal with one or more of them as management units, or outputting data to the second terminal. A plurality of first to n-th node controllers that directly execute the operations are provided, and a main controller that integrally manages the first and second terminals is provided corresponding to the control means. ~ The n-th node controller is connected in series in a ring shape via each signal line, and is received by the node controller as the frame signal emitted from the main controller is sequentially propagated to the 1st to n-th node controllers. First done
Of the terminal data of the terminal device into the frame signal or distributing the output data to the second terminal pre-allocated to the frame signal to the corresponding node controller through the main controller. The main controller indicates, in one frame of the frame signal, a first identification code for indicating the start position of the first terminal data and a start position for the output data to the second terminal. And transmitting the second identification code of the frame signal of the first terminal data based on the recognition of the first and second identification codes included in the frame signal. To the corresponding second terminal or output data from the same frame signal to the corresponding second terminal. Serial control apparatus according to claim. 2. The frame signal is composed of frames in the order of a first identification code, a second identification code, and an output data string to a second terminal when output from the main controller. 1) The serial control device described. 3. The node controller adds the first terminal data to be managed immediately after the first identification code of the input frame signal, and adds the second terminal code immediately after the second identification code. The serial control device according to claim (2), wherein the terminal output data is extracted as output data to the second terminal to be managed. 4. The node controller adds the first terminal data to be managed immediately before the second identification code of the input frame signal, and adds the second terminal code immediately after the second identification code. Second output data for the terminal of the management target
The serial control device according to claim 2, wherein the serial control device is extracted as output data to the terminal. 5. The main controller further comprises a third identification code for indicating an end position of the second terminal output data string in one frame of the frame signal, and sends the third identification code. The node controller adds the first terminal data to the frame signal based on the recognition of at least two codes of the first to third identification codes included in the frame signal, or from the frame signal. The serial control device according to claim (2), wherein the output data to the corresponding second terminal is extracted. 6. The node controller adds the first terminal data to be managed immediately before the second identification code of the input frame signal and adds the second terminal immediately before the third identification code. The serial controller according to claim (5), wherein the terminal output data is extracted as output data to the second terminal to be managed. 7. The node controller adds first terminal data to be managed immediately after the first identification code of an input frame signal, and adds second terminal data immediately before the third identification code. The serial controller according to claim (5), wherein the terminal output data is extracted as output data to the second terminal to be managed. 8. The node controller, for each of the first and second terminals that it manages, i: number of first terminals j: number of data bits per first terminal k: second terminal Number l: the number of data bits per second terminal, where (i × j) − (k × 1) ≧ 0, the input frame signal is shifted by (i × j) bits. First shift means, second shift means for shifting the input frame signal by (i * j)-(k * 1) bits, and first shift means for detecting the first identification code from the input frame signal. Detection means, second detection means for detecting the second identification code from the shift signal by the first shift means, and detection output by the first detection means delayed by (i × j) bits. A delay means, and at least Based on the detection output of the first detection means, all data related to the first terminal to be managed based on the detection output of the first detection means, and the first shift based on the delay output of the delay means. The shift signal by the second shift means based on the detection output of the second detection means,
The serial control device according to claim 3, wherein each of the serial control devices selectively outputs as an input frame signal to the next-stage node controller. 9. The node controller, with respect to the first and second terminals, when (i × j) − (k × 1) <0, (i × j) − (k × 1) + α = 9. The serial control device according to claim 8, further comprising offset means for apparently advancing a frame signal input to the first and second shift means by an amount of α bits to be 0. 10. The first and second terminals respectively managed by the node controller are: i: number of first terminals j: number of data bits per first terminal k: second terminal Where l is the number of data bits per second terminal, the first shift means for shifting the input frame signal by (i × j) bits, and the first frame means for shifting the input frame signal from the first frame means From the first detection means for detecting the identification code, the first delay means for delaying the detection output by the first detection means by (i × j) bits, and the shift signal by the first shift means. Second detection means for detecting the second identification code; second delay means for delaying and outputting the detection output by the second detection means by (k × 1) bits; Based on its first identification From the detection signal output timing of the first detection means to the delay signal output timing of the first delay means, all data regarding the first terminal to be managed is stored in the delay signal of the first delay means. After the output timing, the first shift means selects and outputs the shift signals respectively by the first shift means.
Selection means and second shift means for shifting the selection signal (k × l) bits by the first selection means, and in the initial state, the shift signal by the second shift means is selectively output to output the second signal. Second selection means for selectively outputting the selection signal by the first selection means based on the delayed output of the delay means of 1., and inputting the selection signal by the second selection means to the next stage node controller, respectively. Output as a frame signal. The serial control device according to claim 3. 11. The node controller, for each of the first terminals to be managed, wherein i is the number of first terminals and j is the number of data bits per first terminal, the input frame signal is ( a first shift means for shifting by i × j) bits; a detecting means for detecting the first identification code from the input frame signal; and a detection output by this detecting means delayed by (i × j) bits. A delay unit, at least the first identification code based on the input of the frame signal, all data regarding the first terminal to be managed based on the detection output of the detection unit, and the delay output of the delay unit. The serial control according to claim (3) or (7), wherein the shift signal by the shift means is selectively output as an input frame signal to the next stage node controller based on Location. 12. The node controller, for each of the second terminals to be managed, where k is the number of second terminals, l is the number of data bits per second terminal, and the input frame signal is ( shift means for shifting by k × l) bits, detecting means for detecting the second identification code from the input frame signal, and delay means for delaying the detection output by this detecting means by (k × l) bits. A shift signal by the shift means based on the input of the frame signal and an input frame signal based on the delayed output of the delay means are respectively selected and output as input frame signals to the next stage node controller. 3) or the serial controller according to (4). 13. The node controller, for each of the first terminals to be managed, wherein: i: number of first terminals j: number of data bits per first terminal The first shift means for shifting by the number of bits of the second identification code, and the shift signal by the first shift means are further (i ×
j) second shifting means for shifting by bits, detecting means for detecting the second identification code from the input frame signal, and delay means for delaying the detection output by the detecting means by (i × j) bits. And at least the shift signal by the first shift means based on the input of the frame signal, all data regarding the first terminal to be managed based on the detection output of the detection means, 7. The serial control device according to claim 4, wherein the shift signal by the second shift means is selectively output as an input frame signal to the next-stage node controller based on the delayed output. 14. The node controller, with respect to each of the second terminals to be managed, where k is the number of second terminals, and l is the number of data bits per second terminal, the input frame signal is The first shift means for shifting the number of bits of the third identification code and the shift signal by the first shift means are further (k ×
l) at least a second shift means for shifting the bit and a detection means for detecting the third identification code from the input frame signal, and the shift signal by the second shift means based on the input of the frame signal. The serial control device according to claim 6 or 7, wherein the shift signal from the first shift means is selectively output as an input frame signal to the next-stage node controller based on the detection output of the detection means. 15. The node controller includes a first-type node controller that manages first and second terminals, a second-type node controller that manages only the first terminal, and a second-type node controller. A third type of node controller that manages the terminal of, and three types of node controllers, and at least two types of the node controllers are serially connected to the main controller in series. 3) or (4) or (6) or (7). 16. The first-type node controller respectively manages first and second terminals, i: the number of first terminals j: the number of data bits per first terminal k: Number of second terminals l: number of data bits per second terminal, where (i × j) − (k × l) ≧ 0, the input frame signal is (i × j) First shift means for shifting only by bits, second shift means for shifting the input frame signal by (i × j−k × l) bits, and detecting the first identification code from the input frame signal. First detection means, second detection means for detecting the second identification code from the shift signal by the first shift means, and detection output by the first detection means for (i × j) bits. A first delay means for delaying output; The first identification code based on the input of the frame signal, all the data relating to the first terminal to be managed based on the detection output of the first detection means, and the first data based on the delayed output of the delay means. The shift signal by the first shift means, the shift signal by the second shift means based on the detection output of the second detection means,
Each of the second-type node controllers selectively outputs as an input frame signal to the next-stage node controller, and with respect to each of the first terminals managed by: a: the number of first terminals b: per first terminal And a third shift means for shifting the input frame signal by (a × b) bits, and a third detecting means for detecting the first identification code from the input frame signal. A second delay means for delaying the detection output of the third detection means by (a × b) bits, and outputting the first identification code based on the input of the frame signal to the third delay means. Based on the detection output of the detection means, all data regarding the first terminal to be managed, and based on the delay output of the second delay means, the shift signal by the third shift means, The second-stage node controller selectively outputs the frame signal as an input frame signal, and the third-type node controller respectively manages the second terminals, c: the number of second terminals, d: per second terminal And a fourth shift means for shifting the input frame signal by (c × d) bits, and a fourth detecting means for detecting the second identification code from the input frame signal. A third delay means for delaying the detection output of the fourth detection means by (c × d) bits and outputting the shift signal by the fourth shift means based on the input of the frame signal, The serial control device according to claim 15, wherein the input frame signal is selectively output as an input frame signal to the next-stage node controller based on the delay output of the third delay means. . 17. The node controller of the first type is (ixj)-(kx) when (ixj)-(kxl) <0 with respect to the first and second terminals. 17. The serial control device according to claim 16, further comprising: offset means for apparently advancing a frame signal input to the first and second shift means by an α bit for l) + α = 0. 18. The first-type node controller respectively relates to first and second terminals managed by: i: number of first terminals j: number of data bits per first terminal k: Number of second terminals l: When the number of data bits per one second terminal is set, first shift means for shifting the input frame signal by (i × j) bits, and A first detecting means for detecting the identification code of No. 1, a first delay means for delaying and outputting the detection output by the first detecting means by (i × j) bits, and a shift by the first shift means. Second detection means for detecting the second identification code from the signal; second delay means for delaying the detection output of the second detection means by (k × l) bits; Its first identification based on input The over-de, from the detection signal output timing of the first detecting means to the delayed signal output timing of the first delay means, all data regarding the first terminal to be managed, the first
After the delay signal output timing of the delay means, the first selecting means for selectively outputting the shift signal by the first shifting means and the selection signal by the first selecting means are shifted by (k × l) bits. A second shift means for selectively outputting the shift signal by the second shift means in the initial state, and selectively outputting the select signal by the first select means based on the delay output of the second delay means. And a second selection unit for outputting a selection signal by the second selection unit as an input frame signal to the next-stage node controller, and the second-type node controller manages the first terminal respectively. With respect to a: the number of first terminals, b: the number of data bits per first terminal, the input frame signal is shifted by (a × b) bits. A third shift means, a third detection means for detecting the first identification code from the input frame signal, and a second delay for delaying the detection output of the detection means by (a × b) bits. And a first identification code based on the input of the frame signal, all data relating to the first terminal to be managed based on the detection output of the third detection means, the third identification code, The shift signal by the third shift means is selectively output as an input frame signal to the next-stage node controller based on the delay output of the delay means, and the third type node controller respectively controls the second terminal Where c is the number of second terminals, and d is the number of data bits per second terminal, the input frame signal is shifted by (c × d) bits. Shift means, fourth detecting means for detecting the second identification code from the input frame signal, and fourth delay means for delaying the detection output of the fourth detecting means by (c × d) bits. And a shift signal by the fourth shift means based on the input of the frame signal, an input frame signal based on the delayed output of the fourth delay means, and an input frame signal to the next-stage node controller, respectively. The serial control device according to claim 15, wherein the serial control device selectively outputs the serial control signal. 19. The frame signal, when output from the main controller, comprises frames in the order of a second identification code, a second terminal output data string, and a first identification code. The serial control device described. 20. The node controller extracts output data for a second terminal of an input frame signal immediately after the second identification code as output data to a second terminal to be managed, The serial control device according to claim (19), wherein the first terminal data to be managed is added immediately after the first identification code. 21. The node controller extracts output data for a second terminal of the input frame signal immediately before the first identification code as output data to a second terminal to be managed, The serial control device according to claim 19, wherein the first terminal data to be managed is added immediately after the first identification code. 22. The main controller further comprises a third identification code for indicating an end position of the first terminal data string in one frame of the frame signal, and sends the third identification code, The controller adds the first terminal data to the frame signal based on the recognition of at least two codes of the first to third identification codes included in the frame signal, or responds from the frame signal. The serial control device according to claim 19, wherein the output data to the second terminal is extracted. 23. The node controller extracts output data for a second terminal of an input frame signal immediately before the first identification code as output data to a second terminal to be managed, The serial control device according to claim (22), wherein the first terminal data to be managed is added immediately before the third identification code. 24. The node controller extracts output data for the second terminal of the input frame signal immediately after the second identification code as output data to the second terminal to be managed, The serial control device according to claim (22), wherein the first terminal data to be managed is added immediately before the third identification code. 25. When signals are exchanged between a large number of terminals to which data is to be input and one control means, one or a plurality of terminals corresponding to the terminals are used as management units. First to directly execute the acceptance of output data
A plurality of n-th node controllers are provided, and a main controller that integrally manages the terminal is provided corresponding to the control means, and the main controller and the first to n-th node controllers are respectively provided via signal lines. Are connected in series in an annular manner, and the terminal data accepted by the node controller is taken into the frame signal as the frame signal emitted from the main controller is sequentially propagated to the first to nth node controllers. A serial controller, wherein the main controller is a first controller for indicating a start position of the terminal data in one frame of the frame signal.
Of the first identification code and the second identification code for indicating the terminal position of the terminal data string, and sends the identification code, and the node controller outputs the first identification code and the second identification code included in the frame signal. At least the second of them
A serial controller characterized in that terminal data is added to the frame signal based on recognition of the identification code of. 26. With respect to each terminal to be managed, the node controller, wherein i is the number of terminals and j is the number of data bits per terminal, the input frame signal corresponds to the number of bits of the second identification code. The first shift means for shifting only by the shift signal, and the shift signal by the first shift means are further (i ×
j) second shifting means for shifting by bits, detecting means for detecting the second identification code from the input frame signal, and delay means for delaying the detection output by the detecting means by (i × j) bits. And at least a shift signal by the first shift means based on the input of the frame signal, and all data regarding a terminal to be managed based on the detection output of the detection means to the delay output of the delay means. The serial control device according to claim (25), wherein the shift signal by the second shift means is selectively output as an input frame to the next-stage node controller based on the basis. 27. When signals are exchanged between a large number of terminals to which data is to be output and one control means, one or more terminals corresponding to the terminals are used as management units. A plurality of first to nth node controllers that directly execute data output are provided, and a main controller that integrally manages the terminal is provided corresponding to the control means. n node controllers are connected in series via respective signal lines, and the frame signals generated from the main controller are sequentially transmitted to the 1st to n-th node controllers, and are converted to the frame signals through the main controller. A serial control device for distributing output data to a terminal allocated in advance to each corresponding node controller, comprising: The controller, in one frame of the frame signal, includes a first identification code for indicating a head position of output data to the terminal and a second identification code for indicating an end position of the terminal output data string. The node controller is provided with at least an identification code and transmits the identification code, wherein the node controller includes at least a second identification code of the first and second identification codes included in a frame signal.
A serial controller characterized in that the output data from the frame signal to the corresponding terminal is extracted based on the recognition of the identification code. 28. The node controller, for each terminal to be managed, where k is the number of terminals, l is the number of data bits per terminal, and the input frame signal is equal to the second identification code and the number of bits. The first shift means for shifting only by the shift signal by the first shift means and (k ×
l) at least a second shift means for shifting the bit and a detection means for detecting the second identification code from the input frame signal, and the shift signal by the second shift means based on the input of the frame signal. 28. The serial controller according to claim 27, wherein the shift signals from the first shift means are selectively output as input frame signals to the next-stage node controller based on the detection output of the detection means. 29. The serial controller according to claim 27, wherein the main controller and the first to nth node controllers are connected in series in a ring shape. 30. The main controller and the first to n-th node controllers are serially connected to the first to n-th node controllers in the form of a daisy chain, with the main controller being the head. Alternatively, the serial control device according to (28).