JPH0828657B2 - Up-down counter device - Google Patents

Description

The present invention relates to an up / down counter device that realizes a counting function in a semiconductor device such as a microcomputer.

[Conventional technology]

FIG. 2 shows the structure of a conventional up-down counter device (two-phase processing counter device). A and B are pulse inputs with a phase difference input to the counter. Reference numeral 1 denotes a counter, which has a UD input capable of controlling whether to count up or down. 2 is an AND circuit, which is a pulse input signal A and an output a of the count clock generation circuit 4.
Is input and the output b of the AND circuit 2 becomes the clock input signal T of the counter 1 and is input to the counter 1. The counter 1 counts the output of the AND circuit 2. Reference numeral 4 is a count clock generation circuit that generates a clock a by the input pulse signal B and the output c of the up / down control circuit 5. Reference numeral 5 is an up-down control circuit, which has pulse signals A and B.
To output the up / down control signal d, and also to output the signal c to be input to the count clock generation circuit 4.

It is assumed that the pulse input signals A and B are out of phase with each other, and that the phase of B is behind that of A as shown in FIG. The operation of the counter 1 counts up when the rising edge of the pulse B from "L" to "H" is input after the pulse A rises from "L" to "H", and the pulse A is "L". After rising from "to" H ", pulse" H "
When the falling edge of "L" is input from, it operates to count down.

First, when the rising edge of "L" to "H" is input to A and is input to the up / down control circuit 5, the level of B is taken in at the rising edge of "L" to "H" of A, and the level of Output the inversion on d. While A is at "L" level,
The inverted signal of the signal of B is output to d. The count clock generation circuit 4 detects that the rising edge from "L" of "A" to "H" comes after the rising edge of "B" from "L" to "H". If the level of B does not change to "H" while A is "H" from the time when "H" rises, a pulse of "L" level is output from a while A is "H". To do. The output a outputs the "H" level while A is the "L" level.

Next, the clock b input to the counter 1 becomes a “H” pulse when A and a are “H”, and is input to the counter 1. If the counter 1 counts up at the x edge of B as shown in the waveform of FIG. 2, if the counter 1 counts up when the falling edge of the clock b is input when the up / down control signal d is “H”. Since a falling edge is generated in the clock b and d is at the "H" level, counting is performed at the edge of x. With such a relationship between the pulse inputs of A and B, the up-count operation is always performed at the rising edge of B.

[Problems to be Solved by the Invention]

In the conventional technique, the rising edge of the pulse of A is detected, the rising edge of B after that is detected, and the count effective edge of the counter 1 (falling edge of b here) is generated at the rising edge portion thereof. When pulse B, which once rises from "L" to "H", falls from "H" to "L" while A is at "H" level, the count valid edge of counter 1 is generated at the falling edge. I couldn't.

For example, at the rising edge of y of B, as in the rising edge of x, the valid edge of the counter 1 is generated, and the up / down control signal d is set to the “H” level until the valid edge of the counter 1 is generated. Since it is kept, the y-edge counts up like the x-edge. This causes no problem as the operation of counting up at the rising edge after A has risen. However, considering the case where the phase relationship between A and B becomes opposite while A is at "H" level, after B rises once during A is "H", as at the edge of z, for example. , "H"
, The output a of the count clock generating circuit 4 rises to "H" before A falls to "L". That is, as shown in FIG. 2, since the count valid edge does not occur at the falling edge point of the count clock b corresponding to z of the pulse B, the counter value does not change. Therefore, in the conventional configuration, when the phases of the pulse inputs of A and B are inverted at the time of E in FIG. 2, the counter counts up to the point E and counts down after the point E. Since the falling edge of B came in the meantime, but that edge could not be down-counted, there was a problem in that there was a deviation between the effective count edge number and the count value.

The present invention has been made to solve the above-mentioned problems, and the effective edge of the counter is generated even at the falling edge of z of the pulse input B shown in FIG. 2, and the counter at this time is also generated. By setting the up / down control signal of 1 to count down, when the phase relationship between the pulses A and B is opposite at the point E as shown in FIG. 2, the effective edge of the falling edge of the pulse B is Generate a count clock pulse to the counter for
It is an object of the present invention to obtain an up / down counter device in which a count effective edge number of the pulse B and a count value of the counter do not deviate from each other.

[Means for solving the problem]

In the up-down counter device according to the present invention, the conventional basic idea is that the rising edge of the pulse B after the rising edge of the pulse A is effective, whereas the rising edge and the falling edge of the pulse B are effective. A corresponding count clock source is generated for both edges of, and the count valid clock is selected in the count clock source, and the up / down control signal for the selected count valid clock is input to the pulse input B. This is a counter operation that is performed by using.

[Action]

In the present invention, since the count clock is selected from both the rising edge and the falling edge of the pulse input signal B, even when the phases of the pulse input signals A and B are reversed in opposite directions, the pulse clock is The edge of the input signal B can be made to be the effective clock of the count clock.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, reference numeral 1 denotes a counter, which has a UD input capable of controlling whether to count up or count down. Reference numeral 2 denotes an AND circuit, which detects a rising edge and a falling edge of the pulse input signal B and generates a pulse at the edge, and an output a of an edge pulse generating circuit 3;
The other pulse input signal A is input, and the output b of the AND2 is connected to the count input T of the counter 1. Three
Is a double-edge pulse generation circuit, which detects both edges of the pulse input signal B and outputs a pulse to the output a. The pulse input signal B is connected to the UD input that determines up-counting or down-counting of the counter 1.

It is assumed that the pulse input signals A and B are out of phase with each other, and that the phase of B is behind that of A as shown in FIG. The operation of this counter 1 is to count up when the rising edge of "L" to "H" of the pulse B is input while the pulse A is "H", and to fall from "H" to "L". When is input, it operates to count down.

First, when a rising edge (x) from “L” to “H” is input to B while A is “H”, the edge pulse generation circuit 3
Then, a pulse such as a in FIG. 1 (b) is generated. This pulse is input to the AND circuit 2. At this time, since the pulse input signal A is at "H" level, the output b of the AND circuit 2 outputs a pulse as it is and is input as the count clock of the counter 1. If the counter 1 counts up when the UD input is at "H" level and counts down when it is at "L" level, when the pulse of b corresponding to the pulse of "a" is input to the counter 1, a pulse is input to UD. Since the "H" level of signal B is input, counter 1
If the falling edge of the count clock input signal T is the count valid edge, the pulse counts up at the falling edge of the pulse.

Next, when A falls to "L" and then B falls, a pulse is generated at the output a of the edge pulse generation circuit 3, but since A is "L" in AND2, it is output to AND output b. Does not output the pulse of a and remains at the "L" level, and there is no input to the counter.

Then, when A rises again and the rising edge y from “L” to “H” is input from B during the “H” level,
A clock input is given to the counter 1 in the same way as for the edge x. Also at this time, UD is at "H" level because B is input, and the counter 1 counts up corresponding to the edge y.

Now, while this A is "H", when the falling edge z comes after the rising edge y of B once, a pulse is similarly output from the edge pulse generating circuit 3 to a, and AN
Input to D circuit 2. At this time, A is "H", so AND
The output b of the circuit 2 outputs the pulse of a as it is and becomes the clock input of the counter 1. At this time, since UD is the signal B, it becomes "L" level, and the counter 1 counts down the edge z.

Therefore, when both the rising and falling edges of the pulse B come while the pulse A is "H", the counter performs up-counting and down-counting. Therefore, the count result during that time is when the edge x is counted. Same value as. Therefore, immediately after the phases of A and B are reversed, the falling edge of pulse B input during “H” of pulse A can be down-counted, and the counter value continuously changes corresponding to the valid edge. It became a value.

Although the counter 1 is up-counted when UD is "H" and down-counted when UD is "L" in the above embodiment, the polarities may be opposite. Also, counter 1
Although the count effective edge of is set to fall, the same effect can be obtained even if it is considered to be rise. Further, the AND circuit 2 may be another circuit as long as the same logic can be obtained. In the above description, the phase in which B rises after A rises is taken as an example, but a completely similar idea holds even if the phase in which B progresses is considered.

Also, the case where one rising edge and one falling edge of B came between "H" of A was considered, but the same effect can be obtained no matter how many times the pair of both edges is inserted. Furthermore, the order of the rising and falling of B may be the order of falling and rising. Moreover, although it has been described that B rises and falls when A is “H”, even when B rises and falls when A is “L”, the polarity is changed and the same effect as above is obtained. can get.

〔The invention's effect〕

As described above, according to the present invention, with respect to the reference pulse signal A, a pulse is generated by detecting both the rising and falling edges of one pulse B having a phase shift, and the generated pulse is generated. Is selected as an effective clock to the counter by the pulse signal A, and the up-counting and down-counting of the counter are controlled by using the pulse B. Therefore, the phase relationship between the pulses of A and B is reversed. However, the counter can correctly count the count valid pulse according to the phase, and pulse B
There is an effect that an up-down counter device can be obtained in which there is no deviation between the count effective edge number and the count value of the counter.

[Brief description of drawings]

FIG. 1 is a diagram showing a two-phase processing counter device according to an embodiment of the present invention, and FIG. 2 is a diagram showing a conventional two-phase processing counter device. Reference numeral 1 is a counter, 2 is an AND circuit, 3 is a both-edge pulse generation circuit, 4 is a count clock generation circuit, and 5 is an up / down control circuit. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (1)

[Claims] 1. An up / down counter device for inputting a second pulse signal having a phase difference with respect to the first pulse input signal as a reference, and whether the counter counts up with the second pulse signal. A double-edge pulse generation circuit that has an input for determining whether to down-count and that generates a pulse at both the rising and falling edges of the second pulse signal, and an edge pulse generated by the both-edge pulse generation circuit An up / down counter device comprising a logic circuit which selects a count valid clock by the first pulse and uses an edge pulse of its output as a count clock input to the counter.