JPH0827602B2 - Grayscale display circuit for display panel - Google Patents

Description

The present invention relates to a gray scale display circuit for driving a liquid crystal display panel or the like.

[Conventional technology]

A display panel device using a liquid crystal or the like can have a large screen and high image quality by increasing or miniaturizing the pixels of the panel screen, but at the same time, displaying each pixel in a gray scale or a gradation makes it possible to obtain a natural and high quality image. Obtainable. This gradation is, for example, 16 steps, so that the display data is composed of 4 bits. FIG. 5 shows a circuit which has been conventionally used for such gradation display.

A large number of pixels 2 are arranged in a simplified display panel 1, and each pixel 2 includes a vertical scanning line 3 in the horizontal direction in the drawing and a horizontal scanning line 4 in the vertical direction in the drawing, as is well known. It is located at the intersection.

In the case of a display panel, when a certain vertical scanning line 3 is scanned, as is well known, there is a pixel 2 within a display range shown by 5 in FIG. Usually, the display driving is performed all at once during the display period, and the circuit shown on the lower side of the drawing is a gradation display circuit within the predetermined display period for the predetermined display range 5. When the number of gradations is 16, as described above, the display data VD having a 4-bit structure is loaded into the shift register 20 shown in the lower part of the figure by the shift pulse SP. The shift register 20 is composed of four shift registers 21 to 24 each having a stage corresponding to each pixel 2 in the display range 5.

After loading the display data VD to be displayed in the display range 5 in the shift register 20, the latch command LS is given all at once to the latches 60 of the 4-bit configuration provided corresponding to the respective stages, and The display data VD to be displayed in the pixel 2 is read from the corresponding stage and stored therein, and then the pulse width signal generation circuit 70 shown on the left side of the drawing displays the display period VD as shown in FIG.
A count pulse CP in which Td is divided by 16 of the gradation number is given.

The pulse width signal generation circuit 70 is composed of a four-stage counter 71 that receives the count pulse CP and an encoder circuit 72 that receives the outputs of the four stages, and as shown in FIG. 6 (b), the cycle of the clock pulse CP. It generates four pulse width signals PS0 to PS3 each having a pulse width of 1, 2, 4, and 8 times dT.

The display command circuit 80 is a kind of pulse width modulation circuit provided for each latch 60, and outputs the above-mentioned pulse width signal PS of 4 bits and the 4 bits of display data VD stored in the corresponding latch 60. For example, it is composed of four AND gates which receive the corresponding bits of the both at two inputs respectively, and an OR gate which receives four outputs from these AND gates, and has a pulse width corresponding to the value of the display data VD. Generate display command DS. FIG. 2C shows an example of this waveform when the value of the display data VD is 5. As shown in the figure, the display command DS in this case includes two pulses corresponding to the pulse width signals PS0 and PS2, respectively, and the total of both pulse widths corresponds to the display data value of 5 and is the clock pulse. CP
It is 5 times the period dT.

The display output circuit 90 which receives this display command DS is actually shown as a switch in the figure, but is actually configured as a transistor circuit, and has the same waveform as the display command DS and has a display output of a voltage Vd suitable for display by the scanning line 4 And sends it to the corresponding pixel 2 in the display range 5 which is scanned by the scanning line 3.

[Problems to be Solved by the Invention]

As can be seen from the above, the gradation display circuit is
VD is converted into a display output waveform having a pulse width corresponding to the value and applied to each pixel 2, but in the conventional circuit described above,
The number of circuit elements per pixel is large, and it is necessary to simplify the circuit configuration in order to integrate a gradation display circuit capable of driving a larger number of pixels. That is, in the conventional circuit, the display output circuit 90
Apart from the above, the number of gradations is 16 and the display data is 4 as described above.
In the case of the bit configuration, four stages in the shift register 20 per pixel, a latch 60 having a 4-bit configuration, and a display command circuit 80 including five logic gates are required.

The present invention has been made in view of the above circumstances, and an object thereof is to simplify the configuration of a gradation display circuit.

[Means for solving the problem]

According to the present invention, the object is to provide a gradation display circuit for performing gradation display of a predetermined gradation number in a predetermined display range within a predetermined display period as described above, with a stage corresponding to each pixel in the display range. A shift register, a counter that receives a count pulse in which the display period is divided by the number of gradations, and sequentially counts it within this period, and the count value of this counter and the display data value are the sum of both values and the number of gradations. It is composed of an adder circuit that switches the output state according to the above to give to the first stage of the shift register, and a flip-flop that is provided for each stage of the shift register and switches the output state according to the state change of the stage output and in synchronization with the count pulse. Then, a plurality of pieces of display data to be display-set in the display range are sequentially given to the adder circuit by repeating the number of gradations within the display period, and the display data given to the adder circuit is switched. And in a state in which the shift pulse with the same period was applied to the shift register, it is accomplished by the gradation display in the corresponding pixels in the display range in response to changes in the status of the display period of the output of each flip-flop.

[Action]

According to the present invention, as described above, the count value of the counter that counts the count pulses obtained by dividing the display period by the number of gradations while sequentially applying the display data to the adder circuit by the number of gradations within the display period. And the display data value is equal to or greater than the number of gradations, the state of a single output which is a carry signal from the adder circuit is switched to display 1 bit of the display data originally having a plurality of bits. Since the signal is converted into the signal of, the shift register for receiving the signal need only have a 1-bit configuration.

This shift register is of course provided with a stage corresponding to each pixel within the display range, but a flip-flop is provided for each stage in order to generate a display command for the pixel from the stage output,
The output state is switched according to the state change of the stage output and in synchronization with the count pulse, and the output of this flip-flop is used as it is as a display command in which the display data is pulse width modulated. Therefore, in the circuit of the present invention, all of the conventional latches having a plurality of bits and the display command generating circuit need only one flip-flop having a 1-bit structure.

〔Example〕

Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings. FIG. 1 is a circuit diagram of an embodiment of a gradation display circuit for a display panel according to the present invention, and FIG. 2 shows the waveforms of the main signals.

The display panel 1 is the same as that shown in FIG. 5 described above. A large number of pixels 2 are arranged on the inner surface of the display panel 1, for example, in 400 rows and 640 columns. All of the 640 pixels lined up in one line or a range obtained by dividing them into a fraction. Less than,
It is assumed that the number of pixels in the display range 5 is n. In the case of the present invention, the shift register 10 shown in the lower right part of the drawing has a 1-bit configuration, has a stage corresponding to each pixel 2 within this display range, and is driven by the shift pulse SP. In the case of the present invention, the frequency of this shift palace SP is a value obtained by multiplying the update frequency of the screen display of the display panel by the number of array rows of pixels, the number of pixels in the display range and the number of gradations, and this frequency is the operation of the shift register. The number of pixels n in the display range 5 is set so as to be within the possible range.

On the other hand, the display period assigned to the display range 5 is the reciprocal of the frequency obtained by multiplying the update frequency of the screen display by the pixel array matrix, as can be easily understood. The counter 30 which constitutes the present invention receives the count pulse CP having a cycle in which the display period is divided by the number of gradations, and in practice, it is most suitable to have the same number of stages as the number of bits of display data.
In this example, it is assumed that the number of gradations is 16 and the display data has a 4-bit structure, and the counter 30 has a 4-stage structure as shown in the figure. FIG. 2 (d) shows the four-stage output CD of this counter 30.
0 to CD3, and thus the count value CD sequentially rises from 0 to 15 within the display period Td.

In addition to the 4-bit count value CD, the adder circuit 40 of the present invention multiplies n pieces of 4-bit display data Dr corresponding to the number of pixels in the display range 5 by the number of gradations within the display period. In return, that is, the shift pulse SP in Fig. 2 (a)
Each time the display data Dr is received, the value and the count value CD are added, and a 1-bit output signal Dc whose state is switched depending on whether the result is 16 or more gradations is issued. .

In other words, this adder circuit 40 displays the display data Dr of 4 bits each.
If only the carry of the addition result of the count value CD and the count value CD is generated as the 1-bit output signal Dc, the normal 5
It can be configured with a much simpler circuit than a bit output adder circuit. As can be seen from the above, the output signal Dc is generated in synchronization with the shift pulse SP, applied to the first stage of the shift register 10, and then sequentially transmitted to the subsequent stages by the shift pulse SP.

The n flip-flops 50 constituting the present invention are provided facing each stage of the shift register 10. For example, the simplest RS flip-flop in which two NOR gates are combined is used for this, and the set operation is performed by the counter 30. An AND gate 51 is provided associated with this for synchronizing with the clock pulse CP for. The AND gate 51 receives the output of each stage of the shift register 10 at one input and the strobe pulse SB shown in FIG. 2 (b) having the same frequency as the clock pulse CP at the other input. Note that the clock pulse
The CP is slightly shifted in timing from the strobe pulse SB by a simple delay element 31 for the convenience of the entire operation.

Each flip-flop 50 is reset by receiving a start pulse RP at its reset input at the beginning of each display period, as shown in FIG.
Is output to the set input, and the Q output is issued as the display command DS in this example. The display output circuit 90 that receives this display command DS is the same transistor switch circuit as the conventional one.

The control pulse generation circuit 110 receives the shift pulse SP and produces the strobe pulse SB, the clock pulse CP and the start pulse RP from the shift pulse SP, and as can be easily understood, it can be easily constructed by one counter. The display data circuit 120 is a 4-bit output shift register circuit in the video signal circuit for supplying display data to the gradation display circuit according to the present invention. The adder circuit 40 displays the above n display data Dr. In order to be able to supply repeatedly during the period, the four output shift registers are divided into n stages, for example, and the output from each final stage is divided into the first stage as shown in the figure. A return circulation path can be formed at any time.

The original 4-bit display data VD is loaded into the four n-stage shift registers 121 in the display data circuit 120 before the start of each display period Td. By forming a path and applying the same shift pulse SP as that for the shift register 10, the n pieces of 4-bit display data Dr are sequentially repeated to the adder circuit 40 and 16 times within the display period Td. Output to the adder circuit 40.

At the beginning of the display period Td, the flip-flops 50 are reset all at once by the start pulse RP as described above,
The counter 30 starts counting clock pulses CP. Initially, the count value CD of the counter 30 is 0, and in this state, when the adder circuit 40 receives n display data Dr and issues a corresponding output signal Dc, n is stored in the shift register 10.
The individual output signals Dc are loaded. At the same time that the adder circuit 40 receives the next display data Dr, the count value of the counter 30
CD becomes 1, and in this state, when n more output signals Dc are issued, the shift register 10 is in the same loaded state as after the first n, and the same operation is repeated thereafter.

Now, as the count value CD of the counter 30 sequentially rises as described above, the larger the value of the display data Dr, the faster the sum of the count value CD and the count value CD reaches the gradation number 16 and the corresponding output signal Dc For example, the state changes from “L” to “H”, and conversely, the smaller the value of the display data Dr, the slower the corresponding state change of the output signal Dc. Therefore, in the loaded state after the shift register 10 receives the output signals Dc n by n as described above, the output signal Dc corresponding to the display data Dr having a large value in each stage becomes "H". However, the output signal Dc corresponding to the display data Dr having a small value is still "L".

The above-mentioned strobe pulse SB is for notifying the flip-flop 50 of such a state change of the output signal Dc, and every time the output signal Dc is loaded into the shift register 10 by n, the next clock pulse CP causes the counter 30 to output the counter 30. Count value CD
It is given to the AND gate 51 just before is changed. The flip-flop 50 is synchronized with this and the corresponding shift register 10
Receives the stage output of the set input, which is from "L" to "H"
It is set when is changed to and changes the state of the display command DS.

FIG. 2 (e) shows the waveform of this display command DS.
Display commands corresponding to the display data Dr or the values 0 to 15 of the original VD are indicated by DS0 to DS15, respectively. In this way, the circuit of the present invention converts the original display data VD into the display command DS having the pulse width corresponding to the value. As can be seen by comparing FIG. 2 (e) with FIG. 6 (c), the display command DS according to this embodiment is composed of a single pulse, and the conventional display output circuit 90 for receiving the command has a single pulse. This is advantageous in preventing such unnecessary switching operation.

FIG. 3 shows an embodiment in which the circuit of the present invention is combined with a conventional circuit, and the waveform diagram corresponding to this is shown in FIG. In this embodiment, the circuit of the present invention is applied to 3 bits of the display data VD, and the conventional circuit is applied to 1 bit, so that the frequency of the shift pulse SP shown in FIG. It is half of the case in the figure. The shift register 10 in FIG. 3 is driven by this shift pulse SP, but in this embodiment, another shift register 20 is provided. Both have a 1-bit configuration and each have n stages.

The counter 30 has a three-stage configuration, receives the count pulse CP having a cycle twice that in the case of the previous example, and adds the count value CD composed of three stage outputs CD0 to CD2 shown in FIG. 4 (d). Circuit 40
Give to. In addition to the count value CD, the adder circuit 40 sequentially outputs the n pieces of display data Dr corresponding to the upper 3 bits in the 4-bit display data VD from the display data circuit 120 having a 3-bit structure within the display period Td. In this example, half the number of gradations is repeated eight times for reception. In this example also, the display data circuit
Prior to the start of the display period Td, the upper 3 bits of the n pieces of display data VD are loaded in 120 in advance, and at the same time, the least significant bits thereof are loaded in the shift register 20.

As in the previous embodiment, the shift register 10 receives the output signal Dc which is its carry from the adder circuit 40, and the AND gate 51 which receives the output of each stage has twice the output of the previous example as shown in FIG. 4 (b). The stage output is transmitted to the flip-flop 50 in synchronization with the strobe pulse SB having a cycle. The setting operation after the flip-flop 50 is reset by the start pulse PR in FIG. 4 (c) at the beginning of the display cycle Td is exactly the same as that in the previous embodiment.

Immediately after the n least significant bits of the display data VD are loaded in the flip-flop 20, the output of each stage is stored in the corresponding 1-bit latch 60, and the stored content is stored in one of the AND gates 81 through the display period Td. Given to input. To the other input of the AND gate 81, the pulse width signal generating circuit 70 to the pulse width signal PS shown in FIG.
Is given. This pulse width signal generation circuit 70 is the same circuit as that shown in FIG. 5 before receiving another clock pulse CP1 having a frequency twice that of the clock pulse CP described above, but in this embodiment, FIG. It is configured to emit a single pulse width signal PS with the same waveform as PS0 in b).

The output of the flip-flop 50, the output of the AND gate 81 and the input of the OR gate 82 are given, and the output of the OR gate 82 is given to the display output circuit 90 as the display command DS in this embodiment. As can be easily understood, these AND gate 81 and OR gate 82 correspond to the display command circuit 80 in the conventional circuit shown in FIG. The waveform of this display command DS is shown in FIG. 4 (f).

Also in FIG. 4 (f), the display commands corresponding to the display data VD values 0 to 15 are indicated by DS0 to DS15. Corresponds to the upper 3 bits in the display data VD, and the left pulse corresponds to the lowermost bit. The former is created via the shift register 10 etc. and the latter is created via the shift register 20 etc., and both are OR gates 82. It has been combined by.

As described above, in this embodiment, the number of circuit elements required per pixel is larger than that in the previous embodiment, but the shift register
A lower frequency shift pulse SP for 10 can be used to obtain an equivalent function. The frequency of the shift pulse SP can be lowered by handling, for example, 2 bits of the display data VD having a 4-bit structure by the circuit of the present invention and the remaining 2 bits by the conventional circuit. The circuit of the present invention can arbitrarily select whether to handle the upper bits or the lower bits in the display data.

As will be understood from this, the present invention is not limited to the above-described embodiments, but can be implemented in various modes.

〔The invention's effect〕

As described above, according to the present invention, the display data is sequentially applied to the adder circuit by repeating the number of gradations within the display period, and the counter is supplied with the count pulse in which the display period is divided by the number of gradations. , An output signal whose state is switched depending on whether the sum of the display data value and the count value of the counter is greater than or equal to the number of gradations is taken from the addition circuit. Since the signal is converted into the output signal of the adder circuit, the shift register for receiving the signal can be simplified to have a 1-bit configuration.

Furthermore, the flip-flop corresponding to each stage of the shift register is caused to switch the set / reset state in accordance with the state change of the stage output and in synchronization with the count pulse, so that the display command pulse-width-modulated for the display data is flip-flopted. It can be taken out from the output side of the chip as it is and used for driving the display of each pixel, whereby the conventional latch having a plurality of bits and the display command generating circuit can be replaced with a flip-flop having a one-bit structure.

Therefore, according to the present invention, the number of stages of the shift register required for one pixel and the number of circuit elements for extracting a display command from the stage output are reduced to make the configuration of the gray scale display circuit much simpler than before, and the number of gray scales is reduced. It is possible to reduce the area of the integrated circuit chip of the gradation display circuit of 8 or more to half or less.

Further, since the display command output from the circuit of the present invention is always a single pulse unlike the prior art, the number of switching operations of the transistors of the display output circuit is reduced to the necessary minimum,
Moreover, there is an advantage that gradation display of pixels can be made more accurate than in the past.

As can be seen from the description of the embodiment, in the case of the present invention, it is necessary to increase the frequency of the shift pulse for driving the shift register to a multiple of the conventional gray scale, but there is a margin in the drive limit frequency of the shift register conventionally. If there is a restriction from this aspect, the display range is appropriately divided to reduce the number of pixels included in one display range, and the display panels are driven in parallel by a plurality of gradation display circuits. The present invention can be implemented while taking advantage of the above effects.

[Brief description of drawings]

1 to 4 relate to the present invention, and FIG. 1 is a circuit diagram of an embodiment of a gradation display circuit for a display panel according to the present invention.
FIG. 4 is a waveform diagram of the main signals, FIG. 3 is a circuit diagram of an embodiment in which the circuit of the present invention is combined with a conventional circuit, and FIG. 4 is a waveform diagram of the main signals. From FIG.
FIG. 6 is a circuit diagram of a conventional gradation display circuit example, and FIG. 6 is a waveform diagram of its main signals. In these figures, 1: Display panel, 2: Pixel, 3, 4: Scan line, 5: Display range, 10:
Shift register, 20: shift register, 30: counter, 3
1: delay element, 40: adder circuit, 50: flip-flop, 51:
AND gate, 60: Latch, 70: Pulse width signal generation circuit,
71: Counter, 72: Encoder, 80: Display command circuit, 81: AND gate, 82: OR gate, 90: Display output circuit, 110: Control pulse generation circuit, 120: Display data circuit, 121: Shift register, CD, CD0 ~ CD3: Count value, CP, CP1: Count pulse, Dc: Output signal of adder circuit, Dr: Display data input to adder circuit, DS, DS0 to DS15: Display command, PS, PS0 to PS2: Pulse width signal , RP: Start pulse, SB: Strobe pulse, SP: Shift pulse, Td: Display period, VD: Display data, V
d: voltage for display output.

Claims (1)

[Claims] 1. A circuit for performing gradation display of a predetermined number of gradations within a predetermined display period in a display range composed of a plurality of pixels arranged in one direction on a display panel surface, within the display range. A shift register having a stage corresponding to each pixel of, a counter for receiving a count pulse in which a display period is divided by the number of gradations and sequentially counting it within this period, and a counter for receiving a count value of this counter and a display data value. An adder circuit that switches the output state according to the sum of the values and the number of gradations and gives it to the first stage of the shift register, and is provided for each stage of the shift register and is provided for each stage output state change and is synchronized with the count pulse. And a flip-flop for switching the output state, and sequentially supplies a plurality of display data to be display-set in the display range to the adder circuit by repeating the number of gradations within the display period. The shift pulse having the same cycle as the switching of the display data given to the arithmetic circuit is given to the shift register, and the gradation display of the corresponding pixel in the display range according to the state change of the output of each flip-flop in the display period. A gradation display circuit for a display panel, characterized in that