JPH0287188A - Display controller - Google Patents

Abstract

PURPOSE:To display an image plane consisting of an optional number of lines than the number of display liens of a display device at an optional vertical position on a display panel at all times by providing a means which generates a signal for varying and setting the number of blank feeding shift clock pulses, feeding lines with the blank feeding shift clock, and making no display in the blank feeding period. CONSTITUTION:A generation part 60 for a horizontal synchronizing signal as an interface signal to a matrix display device consists of a generating circuit 61 for the blank feeding shift clock, a generating circuit 62 for pulses of frequency which is an (n) times as high as a horizontal synchronizing signal, and a kick circuit 63 for the generating circuit 61. In this case, lines are fed on the display device by as many as the blank feeding shift clock pulses in the blank feeding period and no display is made throughout the period. For the purpose, this blank feeding period is so set that when the number of lines on the image plane is smaller than that of the display panel, parts of unnecessary lines at the upper and lower part of the display panel are fed in blank, thereby displaying the image plane in the center. Further, the image plane can easily be displayed at an optical desired vertical position.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a display control device for a matrix display device such as a plasma display.

[Summary of the Invention] The present invention provides a method for displaying a screen with fewer rows than the number of display rows on a matrix display device, by using a number of blank feed shift clocks equal to the number of row electrodes that are not used for display. means for generating a signal for setting the idle feed period during which the idle feed is generated by making the number of shift clocks for idle feed variable;
Lines are fed by the shift clock for jump feed, and no display is performed during the jump feed period, so that the screen is always displayed at any position in the vertical direction of the display panel by an arbitrary number of lines less than the number of display lines on the display device. , especially in the center.

"Prior Art" A matrix display device is known in which a plurality of row electrodes and a plurality of column electrodes are arranged perpendicularly to each other, and pixels are arranged at the intersections of the picture electrodes.

FIG. 4 shows an example of the configuration of a part of a driver of a plasma display as an example of a matrix display device.

In the figure, XO, Xi, X2. ,,,X (M-1> is a column electrode, for example, M=640. Also, YO.

Yl, Y2. ,,,Y (N-1) is the row electrode, and in the example shown in the figure, the intersection of the two electrodes (N=480) is the pixel (vixel)
becomes.

1 is a column shift register, which in the example shown in the figure consists of 640 stages of registers. 2 is a latch circuit for 640 stages that latches the output of each stage of this shift register 1. 3 is
This is a column drive circuit for supplying the outputs of each stage of the latch circuit 2 to column electrodes, respectively.

Reference numeral 4 denotes a row shift register, which in the illustrated example consists of 480 stages of registers. Reference numeral 5 denotes a row drive circuit for supplying the outputs of each stage of the row shift register to the row electrodes.

6 is a register for generating a mark signal which is a pulse for driving a row.

In this type of matrix display device, the interface signal when receiving a raster scan type cathode ray tube signal for display is generally a vertical synchronization signal VD (Fig. 5A).
, a horizontal synchronizing signal HD (B1 pixel data in the figure), a display timing signal DSPT (c in the figure) synchronized with the generation period of pixel data, and a pixel clock with a pixel data period.

As shown in FIG. 5C, the display timing signal DSPT is generated only during the vertical display period excluding the vertical blanking period, and is at a low level (hereinafter referred to as This low level period is called an assertion period). therefore,
This display timing signal DSPT coincides with the display area period, and the display timing signal DSPT is detected and the data at that time is displayed.

That is, the column shift 1 register 1 is supplied with pixel data through an input terminal 7, and is also supplied with a pixel clock or a shift clock SCX of pixel data through an input terminal 8, and the shift clock SCX sequentially shifts the pixel data. Transferred to register 1. This is performed only during the assertion period of the display timing signal DSPT.

One row of pixel data transferred to shift register 1 is
Row shift clock SCY supplied through input terminal 9
The signal is latched into the child circuit 2 by the following. This row shift clock SCY is a signal synchronized with the horizontal synchronization signal as shown in Figure 5, or the period from when the vertical synchronization signal VD is input until the assertion period of the display timing signal DSPT is detected. That is, the back porch period of the vertical synchronization signal is prevented from occurring.

One row of pixel data from the latch circuit IJ@2 is supplied to the column electrodes XO, XI, and X2° via the column drive circuit 3.
These column electrodes are driven. Then, as explained later,
Among the intersections with the row electrodes to which the mark signal is supplied, the intersections to which luminance data other than black is output from the column drive circuit 3 emit light.

1 after being latched from shift register 1 to latch circuit 2
Since the column electrodes are driven, light emission is delayed by one row in time with respect to the input time of pixel data.

On the other hand, the driving on the row side is as follows. Vertical synchronization signal VD
is supplied to the register 6 through the terminal 10. Further, a load pulse LP is supplied to this register 6 through the terminal 11 and further through the OR gate 12 within the pulse width period of the vertical synchronizing signal. Further, a row shift clock SCY through a terminal 13 is supplied to this register 6 through an OR gate 12. The output of this register 6 is supplied to the row shift register 4.
A row shift clock scY is supplied.

Therefore, when the first shift clock SCY arrives while the vertical synchronization signal VD is input, a mark signal is supplied to the first row electrode YO, and this row electrode YO is driven.

Thereafter, the row electrodes to which the mark signal is supplied are moved row by row by the row shift clock SCY. In this way, by the row shift clock scy, the call f! yo〜Y479
The screen is sequentially scanned up to the point where one screen is displayed.

[Problems to be Solved by the Invention] In the matrix display device as described above, the number of display lines corresponding to the number of scanning lines of a cathode ray tube is physically fixed by the number of row electrodes. However, when used as a display for an 0All device, etc., the number of lines displayed on the screen may be smaller than the number of lines displayed on a matrix display device. When an image signal with a small number of screen lines is supplied to a conventional matrix display device such as the one described above, the image will be jammed at the top of the display panel, and meaningless data will be displayed at the bottom. .

Moreover, if the vertical display period of the next screen starts before the mark signal is swept out from the last stage register of the row shift register 4, the mark signal will be supplied to two rows at the same time. A copy of the top of the screen is displayed at the bottom of the matrix display panel, making it unsightly.

When displaying a screen with fewer lines than the display panel of the matrix display device, it looks better if the display screen is in the center, and the lines that are not displayed are meaningless. It is desirable to avoid displaying inappropriate information.

Therefore, the following can be considered.

For example, the number of rows in the panel size of a matrix display device is 4.
80 and displaying a screen with only 400 lines in the vertical center, in this case, the display position should be lowered by 40 lines so that the top 40 lines and bottom 40 lines are not displayed. Just do it.

For this purpose, an assertion period for 40 rows is formed in the display timing signal DSPT immediately before the vertical display period which is a non-display area, and the row shift clock SCY is set for 40 rows in the assertion period immediately before the vertical display period. It is conceivable that this may cause an outbreak.

In this case, if the number of horizontal synchronization pulses supplied as an interface signal is less than the number of rows on the matrix display panel, pulses with a faster period than the horizontal synchronization pulses are
The 40-shot row shift clock is obtained.

During this 40-row shift, the image data is made "black" or the column or row drive circuit 3 or 5 is disabled to prevent the column or row electrodes from appearing in a meaningless display. Prevent data from being supplied to one or both parties.

Similarly, for the remaining 40 rows in the lower part of the display panel, a row shift clock is generated to sweep out the mark signal before the arrival of the next vertical synchronization signal, and a row shift clock is generated for the remaining 40 rows. period, the image data is "black"
or no data is provided to one or both of the column or row electrodes.

However, when the display timing signal is changed in this way, the display timing signal no longer matches the display area, making display control complicated. That is, since the display timing signal, which is an interface signal to the matrix display device, is changed, the matrix display device also requires a major change in its configuration.

Further, the number of lines on the screen to be displayed on the matrix display device is not necessarily constant, and various numbers of lines can be considered. If this number of different lines is less than the number of display lines of a matrix display device, in order to accommodate each of the screens with a small number of lines, it is necessary to It is necessary to change the number of shift clocks depending on the number of display lines. However, as mentioned above, it is quite difficult to provide the display timing signal with an assertion period even during the non-display area period and to generate the required number of shift clocks during the assertion period.
The configuration for this becomes complicated.

The present invention aims to provide a display control device that can avoid the above-mentioned drawbacks.

[Means for Solving the Problems] A display control device according to the present invention controls the display of a matrix display device in which pixels are arranged at the intersections of a plurality of row electrodes and a plurality of column electrodes. In a display control device that sequentially drives a number of row electrodes based on a shift clock of a predetermined cycle, a number of shift clocks for the number of row electrodes not used for display is defined as a number of shift clocks for the number of row electrodes that are not used for display. Means is provided for generating a null feed period signal which can be set as variable, and the row electrodes are driven during the blank feed period based on the blank feed shift clock, and no display is made during the blank feed period.

Further, the idle feed shift clock may have a higher frequency than the row shift clock during the display area period of the image signal.

[Function] Lines on the display device are sent by the number of shift clocks for jump feed during the jump feed period, and no display is performed during that period.Therefore, during this jump feed period, the number of lines on the screen is smaller than the number of lines on the display panel. In this case, if you set the extra lines at the top and bottom of the display panel to skip, the screen can be displayed in the center.

Since the number of shift clocks during the blank feed period is variable according to the number of lines on the screen, it is possible to always display the screen at the center of the display panel, no matter how many lines there are on the screen.

It is also easy to display it at any desired vertical position instead of the center.

Then, a blank feed period signal separate from the display timing signal is set, and this generates a number of blank feed shift clocks equal to the number of row electrodes not used for display. The signals can be used as usual. Therefore, only a simple additional circuit is required to change the configuration of the matrix display device.

In addition, the number of row shift clocks for jump feed can be easily changed by changing the length of the jump feed period or by changing the frequency of the shift clock, so it can always be used for screens with various numbers of lines. A screen can be displayed at a predetermined (eg, central) position.

By selecting the frequency of the shift clock for jump feed higher than the row shift clock of the display area, jump feed can be performed without reducing the actual number of displayed lines on the screen.

[Embodiment] FIG. 1 is a block diagram of an embodiment of a display control device according to the present invention, and FIG. 2 is a time chart for explaining this embodiment.

In this example, when a number of lines smaller than the number of display lines of the matrix display device is designated as a line on the display screen, that display screen can be automatically displayed at the center of the display panel.

When the screen is displayed in the center, the number of extra lines that appear at the top of the display panel is called the top margin, and the number of extra lines that appear at the bottom of the display panel is called the bottom margin.

In this example, the lines corresponding to the top margin and the bottom margin are skipped during the vertical blanking period of the image signal, and no display is performed during this blanking period.

In FIG. 1, reference numeral 20 denotes a vertical blanking period setting section, which includes a down counter 21 and a blanking period register 22.

30 is a vertical synchronization signal forming section, and a timing detection circuit 3
1, a vertical synchronizing signal generation position register 32, and a vertical synchronizing signal generating circuit 33.

Reference numeral 40 denotes a dog margin idle feed period signal forming section, which includes a timing detection circuit 41, a top margin start register 42, a down counter 43, a top margin period enable signal generation circuit 44, and a top margin register 45.

Reference numeral 50 denotes a bottom margin blank feed period signal generation unit, which includes a down counter 51, a bottom margin period enable signal generation circuit 52, and a bottom margin register 53.

Reference numeral 60 denotes a formation unit for a horizontal synchronization signal DPH as an interface signal to the matrix display device, which includes a generation circuit 61 for a row shift clock for blank feed and a generation circuit 61 for generating a row shift clock for blank feed, and
is a positive integer, and in this example, n=4, for example. ) pulse generation circuit 62 and generation circuit 61
It consists of a kick circuit 63 and an OR circuit 64 for combining with the horizontal synchronizing signal HD.

Reference numeral 70 denotes a row shift clock forming section, which includes a flip-flow 71 circuit 71 for forming gate signals, an OR circuit 72, and a gate circuit 73.

Reference numeral 80 denotes a disable signal generation circuit for not displaying the display during the idle feed period.

91 is a numeric keypad, 92 is an arithmetic means, and 93 is a synthesis circuit composed of an OR gate.

When the number of lines on the screen is input using the numeric keypad 91, the top margin and the bottom margin are calculated by the calculation means 92 and stored in advance in the top margin register 45 and bottom margin register 53, respectively. Further, the start time of the top margin blank feed period is also determined by the calculation means 92, and the start timing information is stored in the register 42.

A signal BLKS (FIG. 2A) indicating the start point of the vertical blanking period of the image signal is supplied to the load terminal of the down counter 21 of the vertical blanking period forming section 20 through the input terminal 101. Then, this down counter 21
The number of horizontal lines in the blanking period is preset from the register 22. On the other hand, a horizontal synchronizing signal HD (D in the figure) is supplied from the input terminal 102 to the clock terminal of the down counter 21. Therefore, the down counter 21 counts down the horizontal synchronization signal HD from the start of the vertical blanking period.

The count value of this down counter 21 is supplied to the timing detection circuit 31 of the vertical synchronization signal forming section 30, and is compared with the value of the generation position of the vertical synchronization signal from the register 32. When the two match, the coincidence pulse EQ1 (the Figure 2B) is obtained. This coincidence pulse EQI is supplied to the vertical synchronization signal generation circuit 33, from which a vertical synchronization signal DPV (FIG. 3C) for the matrix display device is obtained.

The count value from the town counter 21 is also determined by the timing detection time f? of the top margin blank feed period signal forming section 40. 841 and is compared with the start time information of the top margin blank feed period from the register 42, and when the two match, a match signal EQ2 (E in the figure) is obtained.

This match signal EQ2 is supplied to the load terminal of the down counter 43, and at the time of this match signal EQ2, the number of dog margin rows from the top margin register 45 is preset in the down counter 43. Further, the enable signal generation circuit 44 is triggered by the coincidence signal EQ2 from the timing detection circuit 42, and its output signal TPEN
(Fig. 2 F) becomes low level, and the down counter 4
3 is in an enabled state and becomes a countable state.

The signal TPEN is also supplied to a generation circuit 61 for a row shift clock for idle feeding via a synthesis circuit (OR circuit) 93, and this generation circuit 61 is enabled during the period when the signal TPEN is at a low level.

On the other hand, n=4 of the horizontal synchronizing signal from the pulse generation circuit 62
The pulse nHD of twice the frequency is supplied to the kick circuit 63, and the horizontal synchronizing signal HD is also supplied to this kick circuit 63, so that synchronization with the horizontal synchronizing signal HD is achieved. -1r
The hook path 63 kicks the idle feed shift clock generation circuit 61 with a pulse nHD while the generation circuit 61 is enabled by the signal TPEN, and outputs a pulse nH.
A clock n5C (G in FIG. 2) synchronized with D is generated.

However, in this case, the pulse nH that matches the horizontal synchronization signal
D will prevent you from kicking. This is because later, the clock SCP and the horizontal synchronization signal are synthesized by the OR circuit 64 and used as the row shift clock.

The pulse nSC from the idle feed shift clock generation circuit 61 is supplied to the OR circuit 64, and is combined with the horizontal synchronizing signal HD from the input terminal 102.

The output pulse DPH of this OR circuit 64 (FIG. 2; this signal corresponds to the conventional horizontal synchronizing signal of the interface signal supplied to the matrix display device) is supplied to the clock terminal of the down counter 43. therefore,
The down counter 43 sequentially counts down the pulse DPH from the start timing of the top margin period. Then, when the count value of the down counter 43 reaches "0", therefore, when the number of lines corresponding to the top margin is counted, the output signal TPE of the enable signal generating circuit 44 is
N (FIG. 2F) becomes high level, and the down counter 43 becomes disabled and stops counting.

The low level period of the output signal TPEN of the enable signal generation circuit 44 corresponds to the top margin idle feeding period,
During this period, row shift clocks for idle feed for the number of rows of the top margin are obtained from the OR circuit 64.

Next, the start time of the bottom margin coincides with the start time of the vertical blanking period.

A signal BLKS (FIG. 2A) indicating the start point of the vertical blanking period of the image signal through the input terminal 101 is supplied to the load terminal of the down counter 51 of the bottom margin blank feed period signal forming section 50, and the vertical blanking period is At the start of the ranking period, the number of bottom margin lines from the bottom margin register 53 is preset in the down counter 51. Further, the enable signal generation circuit 52 is triggered by the signal BLKS, and its output signal BTEN (second
H) in FIG. 1 becomes low level, and the down counter 51 becomes enabled and ready for counting.

The signal BTEN is also supplied to the idle feed row shift clock generation circuit 61 through the synthesis circuit 93, and the generation circuit 61 is enabled during the low level period of the signal BTEN. Therefore, the clock pulse n5C (FIG. 2G) is obtained from the generating circuit 61 even during the low level period of the signal BTEN. This pulse nSC
is combined with the horizontal synchronizing signal in the OR circuit 64 and then supplied to the tally terminal of the down counter 51. Therefore, the down counter 51 sequentially counts down the pulse DPH from the start timing of the bottom margin period. Then, when the count value of the down counter 51 reaches "0", and therefore the number of lines corresponding to the bottom margin is counted, the output signal BTEN (H in FIG. 2) of the enable signal generation circuit 52 becomes high level, and the down counter 51 reaches a high level. 51 becomes disabled and stops counting.

The low level period of the output signal BTEN of the enable signal generation circuit 52 corresponds to the bottom margin idle feeding period,
During this period, row shift clocks for idle feed for the number of rows of the bottom margin are obtained from the OR circuit 64.

A synthesis circuit 93 consisting of an OR gate outputs output signals TPEN and BTE of enable signal generation circuits 44 and 52.
A signal BLKLN (FIG. 2 J) indicating the idle feeding period of the top margin and bottom margin by adding N is obtained.

The vertical synchronizing signal DPV obtained as described above, the output pulse D P I of the combining circuit 64, and the signal BLKLN indicating the idle feed period from the combining circuit 93 are used as interface signals for pixel data DA, pixel clock SCX, and display. It is supplied to the matrix display device together with the timing signal DSPT.

The row shift clock generating section 70 and the disable signal generating circuit 80 are provided on the matrix display device side.

A pulse DPI is supplied to the gate circuit 73 of the row shift clock forming section 70. In addition, the flip-flop circuit 7
1 is reset by the signal BLKS (FIG. 2A) indicating the start point of the vertical blanking period of the image signal, and is also set by the display timing signal DSPT (FIG. 2K) through the terminal 103. Therefore, from the flip-flow 71 circuit 71, the signal GTI (L in FIG. 2) remains at a low level from the time when the first assertion period of the display timing signal arrives until the arrival of the next vertical synchronization signal.
is obtained. This signal GTI is supplied to an OR circuit 72. The OR circuit 72 is also supplied with a signal BLKLN which is at a low level during the idle feeding period. Therefore, from this OR circuit 72, a gate signal GT2 (FIG. 2M) which becomes low level during the top margin idle feed period and the period after the vertical display period in one vertical period is obtained. This gate signal GT2 is supplied to a gate circuit 73, which gates the pulse DPH during its low level period, thereby obtaining a row shift clock DPSCY (N in FIG. 2) including a shift clock for idle feeding.

The disable signal generation circuit 80, for example, generates two D flip-flops once f#I81 and 82, as shown in the example in the figure.
It can be composed of A pulse DPH is supplied to the clock terminals of the flip-flop circuits 81 and 82, and a display timing signal DS is supplied to the clear terminal of the flip-flop circuit F#181.
PT is supplied, and the output of the flip-flop 11 times #I81 is supplied to the D terminal of the flip-flop circuit 82. 79
An output Fl (O in FIG. 2) is obtained from the 717071 circuit 81. A disable signal DIS (FIG. 2P) is obtained from the flip-flop circuit 82 for preventing display from occurring in periods other than the vertical display period.

This disable signal DIS is delayed by about one horizontal period with respect to the display timing signal DSPT, but this is because the actual display is delayed by one horizontal period.

FIG. 3 shows the state in which the above signals are supplied to the matrix display device.

Row shift clock D from row shift clock forming section 70
PSCY is supplied to the latch circuit 2 through the terminal 9 and to the row shift register 4 through the terminal 13.

Further, the disable signal DIS is supplied to the column and row drive circuits 3 and 5 through terminals 14 and 15, respectively. These drive circuits 3 and 5 are in a disabled state during the low level period of the disable signal, so that no pixel data is supplied to the column electrodes, and no mark signal is supplied to the row electrodes. . In other words, display is not performed during the non-display area period including the blank feed period.

Therefore, prior to the vertical display period, the top margin is skipped using the shift clock for skipping that is faster than the shift clock for the display period, and no display is performed during this period. Thereafter, when the assertion period of the display timing signal arrives, actual display is performed from the row position lowered by the top margin. Then, when the display period ends, the fast feed shift clock performs the fast feed again, and the mark signal is removed from the row corresponding to the bottom margin, and no display is performed during this period.

Note that in order to prevent display from occurring, the disable signal DIS may be supplied to either the row or column drive circuit F#13 or F#5, or display may be prevented from occurring. In order to achieve this, instead of disabling the drive circuit 3.5, the pixel data may be left blank (black) during a period in which no display is performed.

In the above example, the screen is automatically displayed in the center of the display panel, so just by key-inputting the number of lines on the screen, the top margin and bottom margin can be calculated. Alternatively, you can enter either the top margin or the bottom margin and the number of lines on the screen manually. In this case, the screen can be displayed at any position in the vertical direction of the display panel.

Further, the blank feed period may be set to an arbitrary period.

In the above example, the frequency of the shift clock for blank feed is higher than the row shift clock of the display area, but the number of horizontal synchronization signals including the vertical blanking period must be less than the number of rows of the matrix display panel. There is no need to increase the frequency.

In addition, the frequency of the shift clock for jump feed is constant and the length of the jump feed period is changed, but conversely, the length of the jump feed period is constant and the frequency of the shift clock for jump feed is changed, and the display It is also possible to obtain a shift clock for blank feed that matches the number of rows that are not used. Note that the shift clock for blank feed obtained for the bottom margin in the above example only needs to drive the mark signal from the rows of the bottom margin, so it does not have to be equal to the number of rows of the bottom margin; That's fine.

Note that the blank feed period can also be set within the vertical display period depending on the purpose.

If the idea of this invention is developed, it can be applied not only to cases where the number of lines on the screen is smaller than the display panel as described above, but also to cases where the number of columns on the screen is small. That is, a blank feed period is provided in the horizontal blanking period, and during this period, blank data (black data) is transferred to the column shift register using a clock having a pixel clock cycle or a faster cycle. In this way, it is possible to create a portion that is not displayed on one or both of the left and right sides of the screen.

In this case, instead of transferring blank data to the column shift register during the idle feed period, the column drive circuit for a column that does not perform display may be used as an ice kneeple.

[Effects of the Invention] According to the present invention, since a means for generating a null-feeding period signal that generates a number of shift clocks for null-feeding corresponding to the number of row electrodes that are not used for display is provided, this null-feeding period signal When the number of lines on the screen is less than the display panel, if you set the jump period to skip the extra lines at the top and bottom of the display panel, you can display that screen in the center. can.

Furthermore, since the number of shift clocks during the blank feed period can be varied according to the number of lines on the screen, it is possible to always display the screen at the center of the display panel, no matter how many lines there are on the screen.

Furthermore, it is easy to display the image at any desired vertical position instead of the center.

Furthermore, in order to change the number of shift clocks for idle feeding, it is sufficient to simply change the length of the idle feeding period or the frequency of the shift clock for idle feeding, so there is an effect that a simple configuration is required.

Furthermore, a new idle feed period signal is provided so that the interface signals of conventional matrix display devices, such as display timing signals, can be used as is, so changes to the configuration of the display device can be made by simply installing an additional circuit. good.

Furthermore, by setting the shift clock for skipping to a higher frequency than the row shift clock for the display period, it is possible to perform skipping without reducing the number of lines actually displayed on the screen.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
The figure is a time chart for explanation, and Figure 3 is the first
FIG. 4 is a diagram illustrating an example of a matrix display device controlled according to the illustrated example. FIG. 5 is a diagram illustrating an interface signal to a conventional matrix display device. It is. 20; Vertical blanking period forming unit 30; Vertical synchronizing signal forming unit 40; Top margin blank feeding period signal formation 50: Bottom margin blank feeding period signal forming unit 60; Signal including blank feeding shift clock Formation unit 70; Row shift clock formation unit 80; Disable signal generation circuit Agent Masami Sato, patent attorney

Claims (2)

[Claims] (1) Controls the display of a matrix display device in which pixels are arranged at the intersections of a plurality of row electrodes and a plurality of column electrodes, and in which the row electrodes are shifted by a shift clock at a predetermined period during the display area period of an image signal. In a display control device that is sequentially driven based on the display control device, a blank feed period in which a number of blank feed shift clocks is generated according to the number of row electrodes that are not used for display is set such that the number of the blank feed shift clocks is variable. A display control device comprising means for generating an idle-feeding period signal for driving the row electrodes during the idle-feeding period based on the idle-feeding shift clock, and not displaying during the idle-feeding period. (2) The display control device according to claim 1, wherein the idle feed shift clock generated during the idle feed period has a higher frequency than the shift clock during the display area period of the image signal.