JP2006308900A - Display controller, display system, and display control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display controller, a display system, and a display control method that can drive scanning lines different in number from output bits. <P>SOLUTION: The display controller 540 includes a scanning line number setting register 200 where the number of scanning lines of an electrooptical device is set, an offset line number setting register 210 where offset periods are set in scanning line units, and a memory controller 142 as a display data supply section which supplies display data to a data driver 520 in units of one line. The memory controller 142 after supplying the display data to the data driver in units of one line for every horizontal scanning period at a frequency corresponding to the setting data in the scanning line number setting register 200 stops supplying the display data to the data driver for every horizontal scanning period at a frequency corresponding to the setting data in the offset line number setting register 210. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a display controller, a display system, and a display control method.

  In recent years, display devices using EL (electroluminescence) elements have attracted attention. In particular, an organic EL panel having an EL element formed of a thin film of an organic material is a self-luminous type, so that a backlight is not required and a wide viewing angle is realized. In addition, since it has a higher response speed than a liquid crystal panel, a color moving image display can be easily realized with a simple configuration.

  Such an organic EL panel is classified into a simple matrix type and an active matrix type similarly to the liquid crystal panel. When driving a simple matrix type organic EL panel, gradation control can be performed by pulse width modulation (hereinafter abbreviated as PWM). The display controller performs gradation control by outputting a control signal to a driver (data driver, scan driver) that drives the organic EL panel.

  By the way, as the horizontal and vertical drivers for driving the organic EL panel, ones whose output bit number matches the dot number of the organic EL panel are selected.

  FIG. 17 shows a first configuration example of a display system including a conventional organic EL panel.

  In FIG. 17, the organic EL panel 10 is driven by the scan driver 20 and the data driver 30. The data driver 30 drives the data line of the organic EL panel 10 based on the display data of the display area stored in the frame memory 42 built in the display controller 40. The scan driver 20 scans the scan line of the organic EL panel 10.

  As shown in FIG. 17, the scan driver 20 that scans the scan lines of the organic EL panel 10 is selected to have the number of output bits that matches the number of scan lines of the organic EL panel. When the number of output bits of the scan driver 20 is insufficient, the number of scan-side output bits is made equal to the number of scan lines by cascading a plurality of scan drivers.

  For example, Patent Document 1 discloses a technique for realizing display corresponding to video signals of various resolution standards on the premise of a scanning driver having an output bit number that matches the number of scanning lines.

  FIG. 18 shows a second configuration example of a display system including a conventional organic EL panel.

FIG. 18 shows a case where the number of output bits of the scan driver 22 is larger than the number of scan lines of the organic EL panel 10. In this case, a memory area corresponding to the number of output bits of the scan driver 22 is secured in the frame memory 42, and control is performed as if an organic EL panel having the same number of scan lines as the number of output bits of the scan driver 22 is driven. It was.
Japanese Patent Laid-Open No. 11-7269

  However, as described in the first configuration example, when a scan driver having the number of output bits that matches the number of scan lines is employed, the types of scan drivers that can be employed are limited. Therefore, the cost of the display system using the organic EL panel is increased. In particular, even if there is a scan driver that can be obtained at a low cost, it is very expensive to redesign a scan driver.

  Further, as described in the second configuration example, when the driving of the organic EL panel is controlled in a pseudo manner, it is necessary to secure a useless memory area in the frame memory. Therefore, it is difficult to reduce the cost of the display controller by reducing the capacity of the frame memory.

  As described above, it is desirable that a display system using the scan driver can be constructed without changing the design of the scan driver having the number of output bits different from the number of scan lines.

  The present invention has been made in view of the above technical problems, and an object of the present invention is to provide a display controller, a display system, and a display capable of driving a panel having a number of scanning lines different from the number of output bits. It is to provide a control method.

In order to solve the above problems, the present invention
A display controller for controlling a data driver that drives a data line of an electro-optical device,
A scanning line number setting register in which the number of scanning lines of the electro-optical device is set;
An offset line number setting register in which an offset period during which supply of display data to the data driver is stopped is set in units of scanning lines of the electro-optical device;
A display data supply unit for supplying display data to the data driver in units of one line;
The display data supply unit
After supplying display data to the data driver in units of one line for each horizontal scanning period by the number corresponding to the setting data in the scanning line number setting register, the number of times corresponding to the setting data in the offset line number setting register is 1 The present invention relates to a display controller that stops supplying the display data to the data driver every horizontal scanning period.

  In the present invention, after the display controller supplies the display data to the data driver in units of one line every horizontal scanning period for the number of times corresponding to the setting data in the scanning line number setting register, the setting data in the offset line number setting register The supply of display data to the data driver for each horizontal scanning period is stopped for the number of times corresponding to. Accordingly, when the number of scanning lines of the electro-optical device is smaller than the number of output bits of the scanning driver and the offset period is set before the display period (when the scanning driver is connected in order from the first scanning line in the scanning direction). In addition, an existing scan driver can be applied without changing the configuration of the scan driver. Further, it is not necessary to reserve a memory area in the frame memory, and the cost of the display controller can be reduced.

The present invention also provides
A display controller for controlling a data driver that drives a data line of an electro-optical device,
A scanning line number setting register in which the number of scanning lines of the electro-optical device is set;
An offset line number setting register in which an offset period during which supply of display data to the data driver is stopped is set in units of scanning lines of the electro-optical device;
A display data supply unit for supplying display data to the data driver in units of one line;
The display data supply unit
After the supply of the display data to the data driver for each horizontal scanning period is stopped by the number corresponding to the setting data of the offset line number setting register, the number of times corresponding to the setting data of the scanning line number setting register is 1 The present invention relates to a display controller that supplies display data to the data driver in units of one line for each horizontal scanning period.

  In the present invention, the display controller stops supplying the display data to the data driver for each horizontal scanning period by the number of times corresponding to the setting data in the offset line number setting register, and then sets the setting data in the scanning line number setting register. Display data is supplied to the data driver in units of one line for each horizontal scanning period corresponding times. Accordingly, when the number of scanning lines of the electro-optical device is smaller than the number of output bits of the scanning driver and the offset period is set after the display period (when the scanning driver is connected in order from the last scanning line in the scanning direction). The existing scan driver can be applied without changing the configuration of the scan driver. Further, it is not necessary to reserve a memory area in the frame memory, and the cost of the display controller can be reduced.

The present invention also provides
A display controller for controlling a data driver that drives a data line of an electro-optical device,
A scanning line number setting register in which the number of scanning lines of the electro-optical device is set;
An offset line number setting register in which an offset period during which supply of display data to the data driver is stopped is set in units of scanning lines of the electro-optical device;
An offset period setting register for designating whether the offset period is set before or after a display period in which a scanning line of the electro-optical device is scanned;
A display data supply unit for supplying display data to the data driver in units of one line;
When specified by the offset period setting register to set the offset period before the display period,
The display data supply unit
After supplying display data to the data driver in units of one line for each horizontal scanning period by the number corresponding to the setting data in the scanning line number setting register, the number of times corresponding to the setting data in the offset line number setting register is 1 Stop supplying the display data to the data driver for each horizontal scanning period;
When specified by the offset period setting register to set the offset period after the display period,
After the supply of the display data to the data driver for each horizontal scanning period is stopped by the number corresponding to the setting data of the offset line number setting register, the number of times corresponding to the setting data of the scanning line number setting register is 1 The present invention relates to a display controller that supplies display data to the data driver in units of one line for each horizontal scanning period.

  In the present invention, the display controller is provided with the offset period setting register so that the offset period can be set after or before the display period. When the number of output bits of the driver is smaller, the flexibility of connection between the scanning driver and the electro-optical device can be improved, and the mounting area can be made more efficient. At that time, the existing scan driver can be applied without changing the configuration of the scan driver. Further, it is not necessary to reserve a memory area in the frame memory, and the cost of the display controller can be reduced.

In the display controller according to the present invention,
A horizontal synchronization signal generating unit that generates a horizontal synchronization signal defining one horizontal scanning period;
The horizontal synchronization signal generator is
Regardless of the setting contents of the offset period setting register, the horizontal synchronization signal can be supplied to the data driver.

In the display controller according to the present invention,
A vertical synchronization signal generation unit that generates a vertical synchronization signal defining one vertical scanning period;
In the period of the same length as the vertical scanning period defined by the vertical synchronization signal, the display data supply stop operation is performed the number of times corresponding to the setting data of the offset line number setting register, and the scanning line number setting register The display data supply operation can be performed a number of times corresponding to the setting data.

The present invention also provides
A plurality of scan lines;
Multiple data lines,
An electro-optical device including a plurality of pixels;
A scan driver for scanning the plurality of scan lines;
A data driver for driving the plurality of data lines based on display data;
Including any of the display controllers described above,
This relates to a display system in which the number of output bits of the scan driver is greater than the number of scan lines.

In the display system according to the present invention,
Each pixel of the plurality of pixels is
An electroluminescent element specified by any one of the plurality of scan lines and any one of the plurality of data lines may be included.

  According to any one of the above-described inventions, it is possible to provide a display system capable of driving a panel having a number of scanning lines different from the number of output bits using an existing scanning driver and data driver.

The present invention also provides
A display control method for controlling a data driver for driving a data line of an electro-optical device,
Setting the number of scanning lines of the electro-optical device and setting an offset period in which the supply of display data to the data driver is stopped in units of scanning lines of the electro-optical device;
In the vertical scanning period defined by the vertical synchronization signal, display data is supplied to the data driver in units of one line every horizontal scanning period for the number of times corresponding to the setting data of the scanning line number setting register, and then the offset line The present invention relates to a display control method for stopping the supply of the display data to the data driver every horizontal scanning period by the number corresponding to the setting data of the number setting register.

The present invention also provides
A display control method for controlling a data driver for driving a data line of an electro-optical device,
Setting the number of scanning lines of the electro-optical device and setting an offset period in which the supply of display data to the data driver is stopped in units of scanning lines of the electro-optical device;
In the vertical scanning period defined by the vertical synchronization signal, after the supply of the display data to the data driver for each horizontal scanning period is stopped for the number of times corresponding to the setting data of the offset line number setting register, the scanning line The present invention relates to a display control method for supplying display data to the data driver in units of one line for each horizontal scanning period by the number of times corresponding to the setting data of the number setting register.

The present invention also provides
A display control method for controlling a data driver for driving a data line of an electro-optical device,
Setting the number of scanning lines of the electro-optical device and setting an offset period in which the supply of display data to the data driver is stopped in units of scanning lines of the electro-optical device;
Specifying whether the offset period is set before or after a display period in which a scanning line of the electro-optical device is scanned;
When it is specified that the offset period is set before the display period, one horizontal scan is performed for the number of times corresponding to the setting data of the scan line number setting register in the vertical scanning period defined by the vertical synchronization signal. After supplying display data to the data driver in units of one line for each period, supply of the display data to the data driver for each horizontal scanning period is stopped for the number of times corresponding to the setting data in the offset line number setting register And
When it is specified that the offset period is set after the display period, in the vertical scanning period specified by the vertical synchronization signal, one horizontal scanning period is performed for the number of times corresponding to the setting data of the offset line number setting register. After the supply of the display data to each data driver is stopped, the display data is supplied to the data driver in units of one line every horizontal scanning period for the number of times corresponding to the setting data of the scanning line number setting register. Related to the display control method.

In the display control method according to the present invention,
Regardless of whether the offset period is set before the display period or after the display period, a horizontal synchronization signal defining one horizontal scanning period can be supplied to the data driver.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. Display System FIG. 1 is a block diagram showing a configuration example of a display system according to this embodiment.

  The display system 500 includes an organic EL panel (display panel in a broad sense, electro-optical device in a broader sense) 510, a data driver (anode driver) 520, a scanning driver (cathode driver, line driver) 530, and a display controller 540. Note that it is not necessary to include all these circuit blocks in the display system 500, and some of the circuit blocks may be omitted. The display system 500 may be configured to include the host 550.

  The organic EL panel 510 is a simple matrix type. FIG. 1 shows an electrical configuration of the organic EL panel 510. That is, the organic EL panel 510 is an organic electroluminescence element connected to a plurality of scanning lines (cathode in a narrow sense), a plurality of data lines (anode in a narrow sense), and each scanning line and each data line. EL element.

  More specifically, the organic EL panel is formed on a glass substrate. A plurality of data lines DL1 to DLn (n is an integer of 2 or more) arranged in the X direction in FIG. 1 and extending in the Y direction are formed on the glass substrate. In addition, a plurality of scanning lines GL1 to GLm (m is an integer of 2 or more) arranged in the Y direction in FIG. 1 and extending in the X direction are formed on the glass substrate so as to intersect the data lines. When one pixel is composed of three color components, R component, G component, and B component, a set of R component data line, G component data line, and B component data line is used as one set, and the organic EL A plurality of sets of data lines are arranged on the panel 510.

  An organic EL element is formed at a position corresponding to the intersection of the data line DLj (1 ≦ j ≦ n, j is an integer) and the scanning line GLk (1 ≦ k ≦ m, k is an integer).

  FIG. 2 is an explanatory diagram of the structure of the organic EL element.

  In the organic EL element, a transparent electrode (for example, ITO (Indium Thin Oxide)) serving as an anode 602 provided as a data line is formed on a glass substrate 600. A cathode 604 provided as a scanning line is formed above the anode 602. An organic layer including a light emitting layer and the like is formed between the anode 602 and the cathode 604.

  The organic layer includes a hole transport layer 606 formed on the upper surface of the anode 602, a light emitting layer 608 formed on the upper surface of the hole transport layer 606, and an electron transport formed between the light emitting layer 608 and the cathode 604. Layer 610.

  When a potential difference between the data line and the scan line is applied (that is, when a potential difference is applied between the anode 602 and the cathode 604), holes from the anode 602 and electrons from the cathode 604 are generated in the light emitting layer 608. Rejoin. The energy generated at this time causes the molecules of the light emitting layer 608 to be in an excited state, and the energy released when returning to the ground state becomes light. This light passes through the anode 602 formed of a transparent electrode and the glass substrate 600.

  In FIG. 1, a data driver 520 drives a data line based on display data. At this time, the data driver 520 generates a PWM signal having a pulse width corresponding to the display data, and drives each data line based on the PWM signal.

  The scan driver 530 sequentially selects and scans each of the plurality of scan lines. As a result, a current flows through the organic EL element connected to the data line intersecting with the selected scanning line to emit light.

The display controller 540 controls the data driver 520 and the scan driver 530 according to the contents set by the host 550 such as a central processing unit (CPU). More specifically, the display controller 540 sets, for example, an operation mode for the data driver 520, and also generates gradations for generating a vertical synchronization signal YD, a horizontal synchronization signal LP, and a PWM signal generated internally. A clock GCLK, a dot clock DCLK, a discharge signal DIS (blanking adjustment signal in a broad sense), and display data D are supplied. A vertical scanning period is defined by the vertical synchronization signal YD. A horizontal scanning period is defined by the horizontal synchronization signal LP.

  Note that some or all of the data driver 520, the scan driver 530, and the display controller 540 may be formed on the organic EL panel 510.

1.1 Data Line Drive Circuit FIG. 3 shows a configuration example of the data driver 520 in FIG.

  The data driver 520 includes a shift register 522, a line latch 524, a PWM signal generation circuit 526, and a drive circuit 528.

  The shift register 522 includes a plurality of flip-flops in which each flip-flop is provided corresponding to each data line, and the flip-flops are sequentially connected. The dot clock DCLK from the display controller 540 is input to each flip-flop in common. In the first stage flip-flop of the shift register 522, for example, in order of 4 bits from the display controller 540, R component display data, G component display data, B component display data, R component display data,... Thus, it is input in synchronization with the dot clock DCLK. The display data for the R component is data for driving the data line for the R component. The display data for the G component is data for driving the data line for the G component. The B component display data is data for driving the data line for the B component. Then, the shift register 522 takes in each display data while shifting in synchronization with the dot clock DCLK.

  The line latch 524 latches the display data of one horizontal scanning unit fetched into the shift register 522 in synchronization with the horizontal synchronization signal LP supplied from the display controller 540.

  The PWM signal generation circuit 526 generates a PWM signal for driving each data line. More specifically, the PWM signal generation circuit 526 generates a PWM signal whose change point is specified by a grayscale clock based on display data corresponding to the data line. This PWM signal has a pulse width corresponding to the period of the number of grayscale clocks GCLK corresponding to the display data. For example, an independent gradation clock may be supplied for each of the R component, G component, and B component, and a PWM signal may be generated for each color component.

  The drive circuit 528 drives the data line based on the PWM signal generated by the PWM signal generation circuit 526. A discharge signal DIS from the display controller 540 is input to the drive circuit 528. By this discharge signal DIS, the horizontal display period within the horizontal scanning period defined by the horizontal synchronizing signal LP is specified. The horizontal display period is a period starting from the falling edge of the discharge signal DIS and starting from the rising edge of the next discharge signal DIS. The pulse of the horizontal synchronizing signal LP is output during the period when the discharge signal DIS is at the H level.

  The drive circuit 528 connects the data line to the ground potential when the discharge signal DIS is at the H level, and supplies a predetermined current to the data line only during a period corresponding to the pulse width of the PWM signal when the discharge signal DIS is at the L level.

  In the data driver 520, when the discharge signal DIS is at the H level, the display data in the next horizontal scanning period is latched in the line latch 524, thereby preventing the data line from being driven by the display data being rewritten.

1.2 Scan Driver FIG. 4 shows a configuration example of the scan driver 530 of FIG.

  The scan driver 530 includes a shift register 532 and a drive circuit 534.

  The shift register 532 includes a plurality of flip-flops in which each flip-flop is provided corresponding to each scanning line and each flip-flop is sequentially connected. A horizontal synchronization signal LP from the display controller 540 is commonly input to each flip-flop. The vertical synchronization signal YD from the display controller 540 is input to the first flip-flop of the shift register 532. The shift register 532 shifts the pulse of the vertical synchronization signal YD in synchronization with the horizontal synchronization signal LP.

Driving circuit 534 includes first to J (h + m ≦ J, h is an integer of 0 or more, J is an integer) scan line driver ₅₃₆ 1 _{~536 J} of. Each of the _{first to} Jth scan line driving units 536 _{1 to} 536 _J generates a selection pulse based on the output of each flip-flop of the shift register 532. As a result, the scan driver 530 selects the i-th (1 ≦ i <J, i is an integer) scan line driver 536 _i to select a scan line within one vertical scan period defined by the vertical synchronization signal. After generating the pulse, the (i + 1) th scan line driver 536 _{i + 1} can generate the selection pulse.

A discharge signal DIS from the display controller 540 is input to the drive circuit 534. Each of the first to J scan line driver ₅₃₆ 1 _{~536 J} driving circuit 534, discharge signal DIS is connected to the ground potential all scan lines at the H level, when the discharge signal DIS is at the L level Only the selected scanning line is connected to the ground potential, and the other scanning lines are connected to a predetermined potential.

1.3 Discharge Operation FIG. 5 shows an example of an electrical equivalent circuit diagram of the organic EL element.

  The organic EL element can be considered equivalent to a configuration including a parasitic capacitance C1 in which a resistance component R1 and a diode D1 are connected in series and connected in parallel with the diode D1. The parasitic capacitance C1 can be considered as a capacitance component corresponding to a depletion layer formed at the junction surface when a potential difference is applied between the anode 602 and the cathode 604. Thus, the organic EL element can be considered as a capacitive load.

  Therefore, in the display system 500, the discharge operation of the organic EL element of the organic EL panel 510 can be performed using the discharge signal DIS, and the influence of the previous horizontal scanning period can be eliminated.

  FIG. 6 is an explanatory diagram for explaining the discharge operation. However, the same parts as those in the display system shown in FIG.

  When the discharge signal DIS is at L level, the scan driver 530 sets only the selected scan line to the ground potential and connects the other scan line to the potential V-GL. Further, the data driver 520 supplies a predetermined current to the data line only for a period of a pulse width corresponding to each PWM signal. As a result, a current flows through the organic EL element connected to the selected scanning line.

  When the discharge signal DIS is at the H level, all the scanning lines are connected to the ground potential, and all the data lines are connected to the ground potential, so that the potentials at both ends of each organic EL element are equalized. Discharge is possible.

  By adjusting the length of the horizontal display period within the horizontal scanning period, it is possible to prevent flickering depending on the type of the organic EL panel and manufacturing variations, and to adjust the luminance. Thus, the blanking period can be adjusted using the discharge signal DIS, and the discharge signal DIS can be referred to as a blanking adjustment signal.

2. Display Controller FIG. 7 is a block diagram showing an outline of the configuration of the display controller 540 in this embodiment.

The display controller 540 is a host interface (InterFace: hereinafter abbreviated as I / F).
110, a driver I / F 120, a frame memory 130, a control unit 140, and a setting register unit 150.

  The host I / F 110 performs interface processing with the host 550. More specifically, the host I / F 110 controls transmission / reception of data and various control signals between the display controller 540 and the host 550.

  The driver I / F 120 performs interface processing with the data driver 520 and the scan driver 530. More specifically, the driver I / F 120 controls transmission and reception of data and various control signals between the display controller 540, the data driver 520, and the scan driver 530. The driver I / F 120 includes a driver signal generation unit 122 that generates various display control signals for the data driver 520 and the scan driver 530. The driver signal generation unit 122 generates various display control signals based on the setting data in the setting register unit 150.

  The frame memory 130 stores display data for one frame (for one vertical scan) supplied from the host 550 via the host I / F 110, for example. Setting data in the setting register unit 150 is set by the host 550 via the host I / F 110.

  The control unit 140 controls the host I / F 110, the driver I / F 120, the frame memory 130, and the setting register unit 150.

  In such a display controller 540, display data is read from the frame memory 130 at a constant reading cycle (for example, every 1/160 second), and the display data is sent to the data driver 520 via the driver I / F 120. Is output. Therefore, the display data write timing from the host 550 to the frame memory 130 and the display data read timing from the frame memory 130 to the data driver 520 are asynchronous. Such access control to the frame memory 130 is performed by a memory controller 142 (display data supply circuit in a broad sense) of the control unit 140.

  When the frame memory 130 is accessed from the host 550 via the host I / F 110, the memory controller 142 writes data into the frame memory 130 based on the address of the frame memory 130 designated by the host 550, Control to read data from the memory 130 is performed. The memory controller 142 performs control to supply display data for one vertical scan sequentially to the data driver 520 via the driver I / F 120 in units of one horizontal scan (one line unit).

By the way, in the present embodiment, the scan driver 530 performs the first to m-th scans of the organic EL panel 510 by the m scan-line drive units among the _first to J-th scan line drive units 536 _{1 to} 536 _J. The lines GL1 to GLm are scanned. Therefore, the display controller 540 in the present embodiment causes the organic EL panel 510 to scan by the scan driver 530 having the number of output bits that does not match the number of scan lines without wasting the capacity of the frame memory.

  FIG. 8 is an explanatory diagram of this embodiment. In FIG. 8, the same parts as those in FIG. 1 or FIG.

  As shown in FIG. 8, when the number of output bits of the scan driver 530 is larger than the number of scan lines of the organic EL panel 510, the display controller 540 allows the scan driver 530 to specify an offset period. In a display period other than the offset period, the display controller 540 supplies display data to the data driver 520 and supplies a vertical synchronization signal YD and a horizontal synchronization signal LP to the scan driver 530. In the offset period, the display controller 540 stops the supply of display data to the data driver 520 without accessing the frame memory 130, and the vertical synchronization signal YD and the horizontal synchronization signal are supplied to the scan driver 530 in the same manner as in the display period. Supply LP.

  By doing so, the scan of the organic EL panel 510 can be performed by the scan driver 530 having the number of output bits that does not match the number of scan lines without wasting the capacity of the frame memory 130.

  Hereinafter, a more specific configuration example of the display controller 540 will be described.

  FIG. 9 shows a block diagram of the main components of the display controller 540 of FIG.

  The setting register unit 150 may include a scanning line number setting register 200, an offset line number setting register 210, an offset period setting register 220, and a gradation pulse setting register 240.

  Setting data corresponding to the number of scanning lines of the organic EL panel 510 (electro-optical device) is set in the scanning line number setting register 200. In the offset line number setting register 210, setting data corresponding to an offset period in which the supply of display data to the data driver 520 is stopped is set for each scanning line of the organic EL panel 510.

  The gradation pulse setting register 240 is set with setting data for designating the interval of each pulse of the gradation clock GCLK.

  FIG. 10 is an explanatory diagram of the scanning line number setting register 200, the offset line number setting register 210, and the offset period setting register 220 in FIG.

In Figure 10, the first to J J of scanning lines driven by the scanning line driving unit ₅₃₆ 1 _{~536 J} of the scan driver 530 is schematically shown.

Setting data corresponding to the number of first to mth scanning lines of the organic EL panel 510 is set in the scanning line number setting register 200. If the first scan line driver 536 ₁ scans in the forward scan direction, the offset line number setting register 210, the setting data corresponding to the number of scanning line driving unit which is not connected to the scanning lines of the organic EL panel 510 is set Is done. In the offset period setting register 220, is the scanning line driving unit that drives the scanning lines of the organic EL panel 510 selected before the scanning line driving unit that is the target of the number of offset lines (after-offset period insertion)? Setting data is set to specify whether the scanning line driving unit that is the target of the number of offset lines is selected before the scanning line driving unit that drives the scanning lines of the organic EL panel 510 (inserted before the offset period). .

  FIG. 11 is an explanatory diagram of the gradation pulse setting register 240 shown in FIG.

  In the gradation pulse setting register 240, control data for defining the timing of the rising edge or the falling edge of each pulse of the gradation clock GCLK is set. The gradation pulse setting register 240 sets an interval tw1 between the reference timing that is the starting point of the horizontal display period and the edge (rising edge or falling edge) of the first gradation pulse. An interval tw2 between the edge of the first gradation pulse and the edge of the second gradation pulse of the gradation clock GCLK is set. In other words, the interval between the edge of the (i−1) th gradation pulse (2 ≦ i ≦ N, i is an integer) and the edge of the i-th gradation pulse of the gradation clock GCLK by the gradation pulse setting register 240. twi is set.

  Thus, since the timing of the edge of each gradation pulse of the gradation clock GCLK for specifying the changing point of the PWM signal can be individually set, for example, a fine gamma correction curve can be set.

  Returning to FIG. 9, the description will be continued. The memory controller 142 includes an address generation unit 300. The address generation unit 300 generates an address of the frame memory 130. More specifically, the address generation unit 300 generates an address for reading display data supplied to the data driver 520 from the frame memory 130 or an address for writing display data from the host 550 to the frame memory 130. . The address generator 300 updates the address for reading display data from the frame memory 130 with the vertical synchronization signal YD and the horizontal synchronization signal LP.

  The driver signal generation unit 122 includes a YD generation unit (vertical synchronization signal generation unit) 400, an LP generation unit (horizontal synchronization signal generation unit) 410, and a GCLK generation unit (gradation clock generation unit) 420. The YD generation unit 400 generates the vertical synchronization signal YD based on the setting data in the scanning line number setting register 200 and the offset line number setting register 210. The LP generator 410 generates the vertical synchronization signal YD based on the setting data in the scanning line number setting register 200 and the offset line number setting register 210. The GCLK generation unit 420 generates the gradation clock GCLK based on the setting data of the gradation pulse setting register 240. More specifically, the GCLK generation unit 420 determines the interval between the reference timing that is the starting point of the horizontal display period and the edge of the first gradation pulse, and the edge of the (i−1) -th gradation pulse and the i-th position. A gradation clock GCLK is set in which the interval from the edge of the gradation pulse is set based on the setting data of the gradation pulse setting register 240.

  The driver signal generation unit 122 can generate the dot clock DCLK and the discharge signal DIS. The dot clock DCLK is generated by dividing the system clock, for example. The discharge signal DIS has its rise timing and fall timing determined based on setting data in a discharge signal setting register (not shown).

  The dot clock DCLK, discharge signal DIS, vertical synchronization signal YD, horizontal synchronization signal LP, and gradation clock GCLK generated by the driver signal generation unit 122 are supplied to the data driver 520 or the scan driver 530.

  FIG. 12 is an explanatory diagram of a control example of the scan driver 530 when the display controller 540 specifies insertion before the offset period.

  FIG. 12 shows an example in which m is set in the scanning line number setting register 200, h is set in the offset line number setting register 210, and setting data specifying insertion in the preceding stage of the offset period is set in the offset period setting register 220.

Thus, selection pulses first to scan line driver ₅₃₆ 1 _{~536 h} of the h scanning driver 530 is generated, not supplied to the scan line of the organic EL panel 510, the second (h + 1) ~ a J The selection pulses generated by the scanning line driving units 536 _{h + 1 to} 536 _J are supplied to the first to mth scanning lines GL _< b _{> 1 to} GLm of the organic EL panel 510. Note the L (L <J, L is a natural number) was when selection pulses generated by the scan line driver 536 _L of, is sufficiently large J to be supplied to the scanning line GLm of the m organic EL panel 510 May be.

  FIG. 13 shows a timing chart of an operation example of the display controller 540 in which the insertion before the offset period is designated.

  In FIG. 13, it is assumed that the line number and valid signal valid are internal signals of the display controller 540. Also assume that J is equal to (m + h).

  The valid signal valid is inactive during the offset period, and the valid signal valid is active during the display period.

  When the offset period pre-stage insertion is designated by the offset period setting register 220 (when the offset period is designated to be set before the display period), the display controller 540 (memory controller 142) is defined by the vertical synchronization signal YD. In the vertical scanning period, display data is supplied to the data driver 520 in units of one line every horizontal scanning period by m times corresponding to the setting data of the scanning line number setting register 200. Thereafter, the display controller 540 stops the supply of display data to the data driver for each horizontal scanning period by h times, which is the number corresponding to the setting data in the offset line number setting register 210. That is, display data is supplied in units of one line only during the display period, and the display data supply operation is stopped during the offset period.

  Note that FIG. 13 shows an example in which display data is output from the horizontal scanning period immediately before the one vertical scanning period defined by the two vertical synchronization signals YD, but in this case as well, the length of one vertical scanning period is shown. Does not change. Therefore, even in the case of FIG. 13, in the vertical scanning period defined by the vertical synchronization signal YD, data is obtained in units of one line for each horizontal scanning period by m times corresponding to the setting data of the scanning line number setting register 200. After the display data is supplied to the driver 520, the supply of the display data to the data driver every horizontal scanning period can be stopped by h times corresponding to the setting data of the offset line number setting register 210.

  FIG. 14 is an explanatory diagram of a control example of the scan driver 530 when the display controller 540 designates post-offset period insertion.

  FIG. 14 shows an example in which m is set in the scanning line number setting register 200, h is set in the offset line number setting register 210, and setting data for specifying post-offset insertion in the offset period is set in the offset period setting register 220.

Thus, selection pulses first to scan line driver ₅₃₆ 1 _{~536 m} of the m scan driver 530 has generated is supplied to the scan line of the organic EL panel 510, the scanning of the (m + 1) ~ a J The selection pulses generated by the line driving units 536 _{m + 1 to} 536 _J are not supplied to the first to m-th scanning lines of the organic EL panel 510.

  FIG. 15 shows a timing chart of an operation example of the display controller 540 inserted after the offset period.

  In FIG. 15, it is assumed that the line number and valid signal valid are internal signals of the display controller 540. Also assume that J is equal to (m + h).

  The valid signal valid is inactive during the offset period, and the valid signal valid is active during the display period.

  When the offset period post-insertion is designated by the offset period setting register 220 (when the offset period is designated to be set after the display period), the display controller 540 (memory controller 142) is defined by the vertical synchronization signal YD. In the vertical scanning period, the supply of display data to the data driver 520 for each horizontal scanning period is stopped only h times corresponding to the setting data in the offset line number setting register 210. Thereafter, the display controller 540 supplies the display data to the data driver 520 in units of one line for each horizontal scanning period by m times corresponding to the setting data in the scanning line number setting register 200.

  Note that FIG. 15 shows an example in which display data is output from the horizontal scanning period one time after the one vertical scanning period defined by the two vertical synchronization signals YD, but in this case as well, the length of one vertical scanning period is shown. Does not change. Therefore, even in the case of FIG. 15, in the vertical scanning period defined by the vertical synchronization signal YD, the display to the data driver for each horizontal scanning period is performed h times, which is the number corresponding to the setting data of the offset line number setting register 210. After the supply of data is stopped, the display data is supplied to the data driver 520 in units of one line every horizontal scanning period by m times corresponding to the setting data of the scanning line number setting register 200.

  Accordingly, as shown in FIGS. 12 to 15, the number of times (h times) corresponding to the setting data of the offset line number setting register 210 within the same period as the vertical scanning period defined by the vertical synchronization signal YD. The display data supply stop operation and the display data supply operation for the number of times (m times) corresponding to the setting data of the scanning line number setting register 200 are performed.

  The display controller 540 also outputs the horizontal synchronization signal LP to the data driver regardless of the contents of the offset period setting register 220, that is, regardless of whether the offset period is set before the display period or after the display period. 520.

  As described above, by allowing the offset period to be set before or after the display period, the scan driver 530 having the number of output bits that does not match the number of scan lines does not waste the capacity of the frame memory 130. The organic EL panel 510 can be scanned. Further, according to the display controller 540 in the present embodiment, the existing data driver 520 and the scan driver 530 are used, and the scan of the organic EL panel 510 is performed by the scan driver 530 having the number of output bits that does not match the number of scan lines. It is possible to make it happen.

  FIG. 16 shows a timing chart of an example of PWM operation performed by the display controller 540 of the present embodiment. FIG. 16 shows a timing diagram of an operation example of the data driver 520 that generates a PWM signal using the gradation clock GCLK.

  When a pulse of the vertical synchronization signal YD is input from the display controller 540, one vertical scanning period is started. When the pulse of the horizontal synchronization signal LP is input from the display controller 540 during the period in which the vertical synchronization signal YD is at the H level, one horizontal scanning period is started. Further, the horizontal display period is started with the timing at which the discharge signal DIS from the display controller 540 changes from the H level to the L level as a reference timing. The horizontal display period ends when the next discharge signal DIS changes to the H level.

  In the horizontal display period, the display controller 540 outputs the dot clock DCLK and sequentially outputs display data in synchronization with the dot clock DCLK. Further, the GCLK generation unit 420 outputs the gradation clock GCLK within the horizontal display period based on the setting data of the gradation pulse setting register 240.

  The data driver 520 that has fetched the display data from the display controller 540 into the shift register 522 latches the display data in one horizontal scanning unit in the line latch 524 by the horizontal synchronization signal LP during the period when the discharge signal DIS is at the H level. Therefore, the data driver 520 generates the PWM signal PWMG corresponding to the display data in the horizontal scanning period next to the horizontal scanning period in which the display data from the display controller 540 is supplied. In FIG. 16, since the display data is “2”, the pulse width of the PWM signal PWMG is a period from the falling edge of the discharge signal DIS to the edge of the second gradation pulse. In this way, since the interval can be varied for each gradation pulse of the gradation clock, a PWM signal having a finely settable width can be generated.

  Further, the blanking period is adjusted by the discharge signal DIS to make the horizontal display period variable, and the interval between the grayscale pulses can be varied within the horizontal display period. Thereby, the pulse width of the PWM signal can be set as an absolute value according to the size of the organic EL panel 510 and the type of the organic EL element, so that desired gradation expression can be easily performed.

  In FIG. 16, it is described that the interval between the reference timing and the gradation pulse or the interval between the gradation pulses is set at the rising edge of each gradation pulse, but it is set at the falling edge of each gradation pulse. It may be.

  The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist of the present invention. For example, the present invention is not limited to being applied to driving the organic EL panel described above, but can be applied to driving liquid crystal display devices and plasma display devices.

  In the invention according to the dependent claims of the present invention, a part of the constituent features of the dependent claims can be omitted. Moreover, the principal part of the invention according to one independent claim of the present invention can be made dependent on another independent claim.

1 is a block diagram of a configuration example of a display system according to an embodiment. Explanatory drawing of the structure of an organic EL element. FIG. 2 is a block diagram of a configuration example of a data driver in FIG. 1. FIG. 5 is a block diagram of a configuration example of the scan driver in FIG. 4. The figure which shows an example of the electrical equivalent circuit of an organic EL element. Explanatory drawing for demonstrating discharge operation. The block diagram of the outline | summary of a structure of the display controller in this embodiment. Explanatory drawing of this embodiment. The block diagram of the principal part of the structure of the display controller of FIG. FIG. 10 is an explanatory diagram of a scanning line number setting register, an offset line number setting register, and an offset period setting register in FIG. 9. Explanatory drawing of the gradation pulse setting register of FIG. Explanatory drawing of the example of control of the scanning driver in the case of the offset period front stage insertion by the display controller of this embodiment. The timing diagram of the example of operation | movement of the display controller of an offset period front stage insertion. Explanatory drawing of the example of control of the scanning driver in the case of insertion after the offset period by the display controller of this embodiment. The timing diagram of the example of operation | movement of the display controller of an offset period latter stage insertion. The timing diagram of the operation example of PWM performed by the display controller of this embodiment. The figure of the 1st structural example of the display system containing the conventional organic electroluminescent panel. The figure of the 2nd structural example of the display system containing the conventional organic electroluminescent panel.

Explanation of symbols

10, 510 organic EL panel, 20, 22, 530 scan driver,
30, 520 data driver, 40, 540 display controller,
42, 130 frame memory, 110 host I / F, 120 driver I / F,
122 driver signal generation unit, 140 control unit, 142 memory controller,
150 setting register section, 200 scan line number setting register,
210 Offset line number setting register, 220 Offset period setting register,
240 gradation pulse setting register, 300 address generator, 400 YD generator,
410 LP generator, 420 GCLK generator, 500 display system,
522, 532 shift register, 524 line latch,
526 PWM signal generation circuit, 528, 534 drive circuit,
536 _{1 to} 536 _J first to Jth scanning line driving units, 550 host,
600 glass substrate, 602 anode, 604 cathode, 606 hole transport layer,
608 light emitting layer, 610 electron transport layer, D display data,
DCLK dot clock, DIS discharge signal,
DL1 to DLn, 1st to nth data lines, GCLK gradation clock,
GL1 to GLm 1st to mth scanning lines, LP horizontal synchronization signal,
YD vertical sync signal

Claims (11)

A display controller for controlling a data driver that drives a data line of an electro-optical device,
A scanning line number setting register in which the number of scanning lines of the electro-optical device is set;
An offset line number setting register in which an offset period during which supply of display data to the data driver is stopped is set in units of scanning lines of the electro-optical device;
A display data supply unit for supplying display data to the data driver in units of one line;
The display data supply unit
After supplying display data to the data driver in units of one line for each horizontal scanning period by the number corresponding to the setting data in the scanning line number setting register, the number of times corresponding to the setting data in the offset line number setting register is 1 A display controller, wherein supply of the display data to the data driver for each horizontal scanning period is stopped. A display controller for controlling a data driver that drives a data line of an electro-optical device,
A scanning line number setting register in which the number of scanning lines of the electro-optical device is set;
An offset line number setting register in which an offset period during which supply of display data to the data driver is stopped is set in units of scanning lines of the electro-optical device;
A display data supply unit for supplying display data to the data driver in units of one line;
The display data supply unit
After the supply of the display data to the data driver for each horizontal scanning period is stopped by the number corresponding to the setting data of the offset line number setting register, the number of times corresponding to the setting data of the scanning line number setting register is 1 A display controller for supplying display data to the data driver in units of one line for each horizontal scanning period. A display controller for controlling a data driver that drives a data line of an electro-optical device,
A scanning line number setting register in which the number of scanning lines of the electro-optical device is set;
An offset line number setting register in which an offset period during which supply of display data to the data driver is stopped is set in units of scanning lines of the electro-optical device;
An offset period setting register for designating whether the offset period is set before or after a display period in which a scanning line of the electro-optical device is scanned;
A display data supply unit for supplying display data to the data driver in units of one line;
When specified by the offset period setting register to set the offset period before the display period,
The display data supply unit
After supplying display data to the data driver in units of one line for each horizontal scanning period by the number corresponding to the setting data in the scanning line number setting register, the number of times corresponding to the setting data in the offset line number setting register is 1 Stop supplying the display data to the data driver for each horizontal scanning period;
When specified by the offset period setting register to set the offset period after the display period,
After the supply of the display data to the data driver for each horizontal scanning period is stopped by the number corresponding to the setting data of the offset line number setting register, the number of times corresponding to the setting data of the scanning line number setting register is 1 A display controller for supplying display data to the data driver in units of one line for each horizontal scanning period. In any one of Claims 1 thru | or 3,
A horizontal synchronization signal generating unit that generates a horizontal synchronization signal defining one horizontal scanning period;
The horizontal synchronization signal generator is
The display controller, wherein the horizontal synchronization signal is supplied to the data driver regardless of the setting contents of the offset period setting register. In any one of Claims 1 thru | or 4,
A vertical synchronization signal generation unit that generates a vertical synchronization signal defining one vertical scanning period;
In the period of the same length as the vertical scanning period defined by the vertical synchronization signal, the display data supply stop operation is performed the number of times corresponding to the setting data of the offset line number setting register, and the scanning line number setting register A display controller, wherein the display data is supplied a number of times corresponding to setting data. A plurality of scan lines;
Multiple data lines,
An electro-optical device including a plurality of pixels;
A scan driver for scanning the plurality of scan lines;
A data driver for driving the plurality of data lines based on display data;
A display controller according to any one of claims 1 to 5,
The display system, wherein the number of output bits of the scan driver is larger than the number of scan lines. In claim 6,
Each pixel of the plurality of pixels is
A display system comprising: an electroluminescent element specified by any one of the plurality of scanning lines and any one of the plurality of data lines. A display control method for controlling a data driver for driving a data line of an electro-optical device,
Setting the number of scanning lines of the electro-optical device and setting an offset period in which the supply of display data to the data driver is stopped in units of scanning lines of the electro-optical device;
In the vertical scanning period defined by the vertical synchronization signal, display data is supplied to the data driver in units of one line every horizontal scanning period for the number of times corresponding to the setting data of the scanning line number setting register, and then the offset line A display control method comprising: stopping the supply of the display data to the data driver every horizontal scanning period by the number of times corresponding to the setting data of the number setting register. A display control method for controlling a data driver for driving a data line of an electro-optical device,
Setting the number of scanning lines of the electro-optical device and setting an offset period in which the supply of display data to the data driver is stopped in units of scanning lines of the electro-optical device;
In the vertical scanning period defined by the vertical synchronization signal, after the supply of the display data to the data driver for each horizontal scanning period is stopped for the number of times corresponding to the setting data of the offset line number setting register, the scanning line A display control method, wherein display data is supplied to the data driver in units of one line every horizontal scanning period as many times as the number of times corresponding to the setting data of the number setting register. A display control method for controlling a data driver for driving a data line of an electro-optical device,
Setting the number of scanning lines of the electro-optical device and setting an offset period in which the supply of display data to the data driver is stopped in units of scanning lines of the electro-optical device;
Specifying whether the offset period is set before or after a display period in which a scanning line of the electro-optical device is scanned;
When it is specified that the offset period is set before the display period, one horizontal scan is performed for the number of times corresponding to the setting data of the scan line number setting register in the vertical scanning period defined by the vertical synchronization signal. After supplying display data to the data driver in units of one line for each period, supply of the display data to the data driver for each horizontal scanning period is stopped for the number of times corresponding to the setting data in the offset line number setting register And
When it is specified that the offset period is set after the display period, in the vertical scanning period specified by the vertical synchronization signal, one horizontal scanning period is performed for the number of times corresponding to the setting data of the offset line number setting register. After the supply of the display data to each data driver is stopped, the display data is supplied to the data driver in units of one line every horizontal scanning period for the number of times corresponding to the setting data of the scanning line number setting register. A display control method characterized by the above. In any one of Claims 8 thru | or 10.
Regardless of whether the offset period is set before the display period or after the display period, a horizontal synchronization signal defining one horizontal scanning period is supplied to the data driver. Method.

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