JP2006317535A - Display controller, display system, and display control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display controller, a display system, and a display control method for controlling a plurality of drivers so that a display panel of a large screen size can be driven while high luminance is maintained. <P>SOLUTION: The display controller 540 includes: a display memory 30 having a first and a second memory areas MAR1 and MAR2 wherein display data of a first rectangular and a second rectangular areas SAR11 and SAR12 are stored; a first display data output section 372 for supplying the display data read out of the first memory area MAR1 to a first data driver 520<SB>1</SB>for driving a data line of a first display area DAR11 of a first and a second display areas DAR11 and DAR12 provided in the arranging direction of scanning lines of the display panel; and a second display data output section 374 for supplying the display data read out of the second memory area MAR2 to a second data driver 520<SB>2</SB>for driving a data line of the second display area DAR12. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a display controller, a display system, and a display control method.

  In recent years, display devices using EL (electroluminescence) elements have attracted attention. In particular, an organic EL panel having an EL element formed of a thin film of an organic material is a self-luminous type, so that a backlight is not required and a wide viewing angle is realized. In addition, since it has a higher response speed than a liquid crystal panel, a color moving image display can be easily realized with a simple configuration.

  Such an organic EL panel is classified into a simple matrix type and an active matrix type similarly to the liquid crystal panel. When driving a simple matrix type organic EL panel, gradation control can be performed by pulse width modulation (hereinafter abbreviated as PWM). The display controller performs gradation control by outputting a control signal to a driver (data driver, scan driver) that drives the organic EL panel.

Incidentally, as with a liquid crystal panel (a liquid crystal display device in a broad sense), an organic EL panel having a larger screen size is required. However, when driving a simple matrix type organic EL panel, it is known that the higher the number of scanned electrodes (number of lines), the higher the luminance cannot be obtained. For this reason, it is difficult to manufacture an organic EL panel having a large screen size. In general, a large screen size is obtained by using a plurality of organic EL panels. The scanning lines of these organic EL panels are scanned by, for example, a plurality of cascade-connected scanning drivers, and the data lines of the organic EL panel are driven by, for example, a plurality of cascade-connected data drivers.
JP 2000-206936 A

  Patent Document 1 discloses a display device in which a display area of an organic EL panel is divided into two display areas in the arrangement direction of the data electrodes of the organic EL panel, and each display area is driven by each drive unit. . And while switching the drive part which supplies display data for every scanning electrode, a drive part is driven selectively, and the line which supplies display data to each drive part for every screen is changed. Thereby, the drive frequency of the drive part which drives a data electrode is suppressed.

  However, in this display device, when the number of scanning electrodes increases, it is not possible to suppress a decrease in luminance. Therefore, it is impossible to drive a display panel having a large screen size while maintaining high luminance.

  Moreover, even if a display device having a large screen size is obtained using a plurality of organic EL panels, it is possible to display only one screen by a plurality of cascade-connected drivers. Lack of superiority. Therefore, it is desirable that various image displays can be realized on the display device with a simpler configuration.

  The present invention has been made in view of the technical problems as described above, and an object of the present invention is to control a plurality of drivers so that a display panel having a large screen size can be driven while maintaining high luminance. To provide a display controller, a display system, and a display control method.

  Another object of the present invention is to provide a display controller, a display system, and a display control method for realizing various image displays with a simple configuration.

In order to solve the above problems, the present invention
A display controller for controlling first and second data drivers for driving a plurality of data lines of a display panel,
A display memory having first and second storage areas for storing display data of first and second rectangular areas in the display area of the display panel;
Of the first and second display areas provided in the direction in which the scanning lines of the display panel are arranged, the first data driver for driving the data lines in the first display area is provided with respect to the first data driver of the display memory. A first display data output unit for supplying display data read from one storage area;
A second display data output unit for supplying display data read from the second storage area of the display memory to the second data driver that drives the data lines of the second display area Related to the display controller.

In the display controller according to the present invention,
A display control signal generator that generates a vertical synchronization signal that defines one vertical scanning period, a horizontal synchronization signal that defines a horizontal scanning period, and a dot clock that defines the supply timing of display data of pixels;
The horizontal synchronization signal and the dot clock are commonly supplied to the first and second data drivers, and the vertical synchronization signal and the horizontal synchronization signal are scanned through the scanning lines of the first rectangular area. And the second scan driver that scans the scan lines of the second rectangular area.

  According to any one of the above inventions, display data is separately supplied to the first and second data drivers that drive the data lines in the first and second display areas provided in the direction in which the scanning lines are arranged. Can supply. By doing this, even if the number of scanning lines in each display area of the first and second display areas is small, each of the display areas can be scanned separately, and a window display can be displayed in each display area. One image can be displayed. Accordingly, it is possible to display an image as a panel having a large screen size while maintaining a high luminance by using a plurality of panels having a limited number of scanning lines.

  In particular, when one image is displayed using two panels, a shift in drive timing between both the panels becomes noticeable as image disturbance. Therefore, by making the synchronization signals for driving both panels the same, it is possible to realize various image displays with a simple configuration, preventing deterioration of image quality.

In the display controller according to the present invention,
An operation mode setting register for setting an operation mode of the display controller;
Combining display data read from the first storage area and display data read from the second storage area as display data of the area where the first and second rectangular areas overlap Including a synthesis processing unit for generating display data,
When the first mode is set by the operation mode setting register,
The display data read from the first storage area, the display data read from the second storage area, and the composite display data are output via the first display data output unit,
When the second mode is set by the operation mode setting register,
The display data read from the first storage area is output via the first display data output unit, and the display data read from the second storage area is output to the second display data. And outputting the composite display data as display data of an area where the first and second rectangular areas overlap through one of the first and second display data output sections. it can.

In the display controller according to the present invention,
When the second mode is set by the operation mode setting register,
After the display data after the combining process is generated by the combining processing unit, the display data read from the first storage area and the second storage area are read according to the scanning timing of the display panel. Data in which at least two of the display data and the composite display data are mixed can be output via one of the first and second display data output units.

  According to any one of the above-described inventions, in addition to the above effects, it is possible to provide a display controller that can be applied when one panel is driven by one data driver and one scan driver. Can contribute to the configuration.

The present invention also provides
A plurality of scan lines;
Multiple data lines,
A display panel including a plurality of pixels;
First and second scan drivers that scan the scan lines of the first and second display areas of the display panel;
First and second data drivers for driving the plurality of data lines;
Including any of the display controllers described above,
The display controller is
The present invention relates to a display system that supplies display data to the first and second data drivers.

The present invention also provides
Each display panel includes a plurality of scanning lines, a plurality of data lines, and a plurality of pixels, and the first and second display panels provided in the alignment direction of the scanning lines;
First and second scan drivers that scan the scan lines of the first and second display panels;
A first data driver that drives a plurality of data lines of the first display panel as data lines of the first display area;
A second data driver for driving a plurality of data lines of the second display panel as data lines of the second display region;
Including any of the display controllers described above,
The display controller is
The present invention relates to a display system that supplies display data to the first and second data drivers.

In the display system according to the present invention,
Each pixel of the plurality of pixels may include an electroluminescent element.

  According to any one of the above inventions, it is possible to provide a display system including a display controller that controls a plurality of drivers so that a display panel having a large screen size can be driven while maintaining high luminance. Further, according to the present invention, it is possible to provide a display system including a display controller that realizes various image displays with a simple configuration.

The present invention also provides
A display control method for controlling first and second data drivers for driving the data lines of a display panel including a plurality of scanning lines and a plurality of data lines,
Of the first and second display areas provided in the direction in which the scanning lines of the display panel are arranged, the first data driver for driving the data lines in the first display area is provided with the first display memory. In addition to supplying display data read from the storage area of
Supplying the display data read from the second storage area of the display memory to the second data driver that drives the data lines of the second display area;
The first and second data drivers are commonly supplied with a horizontal synchronization signal that defines one horizontal scanning period and a dot clock that defines the supply timing of pixel display data, and vertical synchronization that defines one vertical scanning period. Display control for supplying the signal and the horizontal synchronization signal in common to the first scan driver that scans the scan lines of the first display area and the second scan driver that scans the scan lines of the second display area Related to the method.

In the display control method according to the present invention,
Display data read from the first storage area, display data read from the second storage area, and display read from the first storage area when set to the first mode Supplying combined display data obtained by combining the data and the display data read from the second storage area to one data driver that drives the data lines of the display panel;
When the second mode is set, the display data read from the first storage area is output to the first data driver, and the display data read from the second storage area is output. Can be output to the second data driver.

In the display control method according to the present invention,
The display data read from the first storage area according to the scanning timing of the display panel after the composite display data is generated when the second mode is set, the second storage area Can output data in which at least two of the display data read from the display data and the display data after the synthesis processing are mixed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. Display System FIG. 1 shows a block diagram of a configuration example of a display system.

  The display system 500 includes an organic EL panel (display panel in a broad sense) 510, a data driver 520, a scan driver 530, and a display controller 540. Note that it is not necessary to include all these circuit blocks in the display system 500, and some of the circuit blocks may be omitted. The display system 500 may be configured to include the host 550.

  The organic EL panel 510 is a simple matrix type. FIG. 1 shows an electrical configuration of the organic EL panel 510. That is, the organic EL panel 510 includes a plurality of scanning lines (cathode in a narrow sense), a plurality of data lines (anode in a narrow sense), and each organic EL element (a display element in a broad sense). A plurality of organic EL elements connected to the line.

  More specifically, the organic EL panel is formed on a glass substrate. A plurality of data lines DL1 to DLn (n is an integer of 2 or more) arranged in the X direction in FIG. 1 and extending in the Y direction are formed on the glass substrate. Also, a plurality of scanning lines GL1 to GLm (m is an integer of 2 or more) arranged in the Y direction in FIG. 1 and extending in the X direction are formed on the glass substrate so as to intersect the data lines. When one pixel is composed of three color components of R component, G component, and B component, the organic EL is made by combining the data line for R component, the data line for G component, and the data line for B component. A plurality of sets of data lines are arranged on the panel 510.

  An organic EL element is formed at a position corresponding to the intersection of the data line DLj (1 ≦ j ≦ n, j is an integer) and the scanning line GLk (1 ≦ k ≦ m, k is an integer).

  FIG. 2 is an explanatory diagram of the structure of the organic EL element.

  In the organic EL element, a transparent electrode (for example, ITO (Indium Thin Oxide)) serving as an anode 602 provided as a data line is formed on a glass substrate 600. A cathode 604 provided as a scanning line is formed above the anode 602. An organic layer including a light emitting layer and the like is formed between the anode 602 and the cathode 604.

  The organic layer includes a hole transport layer 606 formed on the upper surface of the anode 602, a light emitting layer 608 formed on the upper surface of the hole transport layer 606, and an electron transport formed between the light emitting layer 608 and the cathode 604. Layer 610.

  When a potential difference between the data line and the scan line is applied, that is, when a potential difference is applied between the anode 602 and the cathode 604, holes from the anode 602 and electrons from the cathode 604 are recombined in the light emitting layer 608. To do. The energy generated at this time causes the molecules of the light emitting layer 608 to be in an excited state, and the energy released when returning to the ground state becomes light. This light passes through the anode 602 formed of a transparent electrode and the glass substrate 600.

  In FIG. 1, a data driver 520 drives a data line based on display data (gradation data). At this time, the data driver 520 generates a PWM signal having a pulse width corresponding to the display data, and drives each data line based on the PWM signal.

  The scan driver 530 sequentially selects a plurality of scan lines. As a result, a current flows through the organic EL element connected to the data line intersecting with the selected scanning line to emit light.

  The display controller 540 controls the data driver 520 and the scan driver 530 according to the contents set by the host 550 such as a central processing unit (CPU). More specifically, the display controller 540 sets, for example, an operation mode for the data driver 520, and also generates a grayscale clock GCLK and a dot clock for generating an internally generated horizontal synchronization signal LP and PWM signal. DCLK, discharge signal DIS, and display data are supplied. A horizontal scanning period is defined by the horizontal synchronization signal LP. Further, the display controller 540 sets, for example, an operation mode to the scan driver 530, and supplies the internally generated vertical synchronization signal YD, horizontal synchronization signal LP, and discharge signal DIS. A vertical scanning period is defined by the vertical synchronization signal YD.

  FIG. 1 shows a case where the organic EL panel 510 is driven using one data driver 520 and one scan driver 530. However, the organic EL panel 510 includes a plurality of data drivers 520 and a plurality of scan drivers. The same applies to the case of driving using 530.

  Further, some or all of the data driver 520, the scan driver 530, and the display controller 540 may be formed on the organic EL panel 510.

1.1 Data Driver FIG. 3 shows a configuration example of the data driver 520 in FIG.

  The data driver 520 includes a shift register 522, a line latch 524, a PWM signal generation circuit 526, and a drive circuit 528. The data driver 520 has a configuration that can be cascade-connected by connecting the shift register 522 in series with the shift register of another data driver.

  The shift register 522 includes a plurality of flip-flops in which each flip-flop is provided corresponding to each data line, and the flip-flops are sequentially connected. The dot clock DCLK from the display controller 540 is input to each flip-flop in common. In the first stage flip-flop of the shift register 522, for example, in order of 4 bits from the display controller 540, R component display data, G component display data, B component display data, R component display data,... Thus, it is input in synchronization with the dot clock DCLK. The display data for the R component is data for driving the data line for the R component. The G component display data is data for driving the data line for the G component. The B component display data is data for driving the data line for the B component. Then, the shift register 522 takes in each display data while shifting in synchronization with the dot clock DCLK.

  The line latch 524 latches the display data of one horizontal scanning unit fetched into the shift register 522 in synchronization with the horizontal synchronization signal LP supplied from the display controller 540.

  The PWM signal generation circuit 526 generates a PWM signal for driving each data line. More specifically, the PWM signal generation circuit 526 specifies the change point based on the display data corresponding to the data line by a grayscale clock (more specifically, the grayscale pulse of the grayscale clock). PWM signal is generated. This PWM signal has a pulse width corresponding to the period of the number of grayscale clocks GCLK corresponding to the display data.

  The drive circuit 528 drives each data line based on the PWM signal generated by the PWM signal generation circuit 526. A discharge signal DIS from the display controller 540 is input to the drive circuit 528. By this discharge signal DIS, the horizontal display period within the horizontal scanning period defined by the horizontal synchronizing signal LP is specified. The horizontal display period is a period starting from the falling edge of the discharge signal DIS and starting from the rising edge of the next discharge signal DIS. The pulse of the horizontal synchronizing signal LP is output during the period when the discharge signal DIS is at the H level.

  The drive circuit 528 connects the data line to the ground potential when the discharge signal DIS is at the H level, and supplies a predetermined current to each data line only for a period corresponding to the pulse width of each PWM signal when the discharge signal DIS is at the L level. To do.

  In the data driver 520, when the discharge signal DIS is at the H level, the display data in the next horizontal scanning period is latched in the line latch 524, thereby preventing the data line from being driven by the display data being rewritten.

1.2 Scan Driver FIG. 4 shows a configuration example of the scan driver 530 of FIG.

  The scan driver 530 includes a shift register 532 and a drive circuit 534. The scan driver 530 has a configuration in which the shift register 532 can be cascaded by connecting the shift register 532 in series with the shift register of another scan driver.

  The shift register 532 includes a plurality of flip-flops in which each flip-flop is provided corresponding to each scanning line and each flip-flop is sequentially connected. A horizontal synchronization signal LP from the display controller 540 is commonly input to each flip-flop. The vertical synchronization signal YD from the display controller 540 is input to the first flip-flop of the shift register 532. The shift register 532 shifts the pulse of the vertical synchronization signal YD in synchronization with the horizontal synchronization signal LP.

  In the case of cascade connection, the shift register 532 outputs the horizontal synchronization signal LP from the display controller 540 as a horizontal synchronization signal for the next scan driver. The shift register 532 outputs the vertical synchronization signal output from the last flip-flop among the plurality of flip-flops as the vertical synchronization signal for the next scan driver. These are input to the shift register of the next-stage scan driver that is cascade-connected. In the shift register of the scanning driver at the next stage, the pulse of the vertical synchronizing signal is shifted in the same manner as the shift register 532.

  The drive circuit 534 sequentially outputs a selection pulse to each scanning line based on the output of each flip-flop of the shift register 532. A discharge signal DIS from the display controller 540 is input to the drive circuit 534. The drive circuit 534 connects all scanning lines to the ground potential when the discharge signal DIS is at the H level, connects only the selected scanning line to the ground potential when the discharge signal DIS is at the L level, and connects the other scanning lines to the ground potential. Connect to a predetermined potential.

1.3 Discharge Operation FIG. 5 shows an example of an electrical equivalent circuit diagram of the organic EL element.

  The organic EL element can be considered equivalent to a configuration including a parasitic capacitance C1 in which a resistance component R1 and a diode D1 are connected in series and connected in parallel with the diode D1. The parasitic capacitance C1 can be considered as a capacitance component corresponding to a depletion layer formed at the junction surface when a potential difference is applied between the anode 602 and the cathode 604. Thus, the organic EL element can be considered as a capacitive load.

  Therefore, in the display system 500, the discharge operation of the organic EL element of the organic EL panel 510 can be performed using the discharge signal DIS, and the influence of the previous horizontal scanning period can be eliminated.

  FIG. 6 is an explanatory diagram for explaining the discharge operation. However, the same parts as those in the display system shown in FIG.

  When the discharge signal DIS is at the L level, the data driver 520 supplies a predetermined current to the data line only during a pulse width corresponding to each PWM signal. When the discharge signal DIS is at the H level, the data driver 520 connects all the data lines to the ground potential.

  When the discharge signal DIS is at L level, the scan driver 530 sets only the selected scan line to the ground potential and connects the other scan line to the potential V-GL. When the discharge signal DIS is at the H level, the scan driver 530 connects all the scan lines to the ground potential.

  Therefore, when the discharge signal DIS is at the L level, a current flows through the organic EL element connected to the selected scanning line. When the discharge signal DIS is at the H level, the potentials at both ends of each organic EL element are equal, and the organic EL element can be discharged.

  By adjusting the length of the horizontal display period within the horizontal scanning period, it is possible to prevent flickering depending on the type of the organic EL panel and manufacturing variations, and to adjust the luminance. Thus, the blanking period can be adjusted using the discharge signal DIS, and the discharge signal DIS can be referred to as a blanking adjustment signal.

2. 2. Display Controller 2.1 Outline FIG. 7 is a block diagram showing an outline of the configuration of the display controller 540 in the present embodiment.

  The display controller 540 includes a host interface (InterFace: hereinafter abbreviated as I / F) 10, a driver I / F 20, a display memory 30, a control unit 40, and a setting register unit 50.

  The host I / F 10 performs interface processing with the host 550. More specifically, the host I / F 10 controls transmission / reception of data and various control signals between the display controller 540 and the host 550.

  The driver I / F 20 performs interface processing with the data driver 520 and the scan driver 530. More specifically, the driver I / F 20 controls transmission / reception of data and various control signals between the display controller 540, the data driver 520, and the scanning driver 530. The driver I / F 20 includes a driver signal generation unit 22 that generates various display control signals for the data driver 520 and the scan driver 530. The driver signal generation unit 22 generates various display control signals based on the setting value of the setting register unit 50.

  The display memory 30 stores display data for one frame (for one vertical scan) supplied from the host 550 via the host I / F 10. The setting value of the setting register unit 50 is set by the host 550 via the host I / F 10.

  The control unit 40 controls the host I / F 10, the driver I / F 20, the display memory 30, and the setting register unit 50.

  In such a display controller 540, display data is read from the display memory 30 at a constant reading cycle (for example, every 1/160 second), and the display data is sent to the data driver 520 via the driver I / F 20. Is output. Therefore, the display data write timing from the host 550 to the display memory 30 and the display data read timing from the display memory 30 to the data driver 520 are asynchronous. Such access control to the display memory 30 is performed by the memory controller 42 of the control unit 40.

  Incidentally, a larger screen size of the organic EL panel 510 is required. However, when driving a simple matrix organic EL panel, it is known that the higher the number of scanning lines, the higher the luminance that cannot be obtained at high speed. For this reason, it is difficult to manufacture an organic EL panel having a large screen size. In general, a large screen size is obtained by using a plurality of organic EL panels. The organic EL panel 510 is scanned with scanning lines by a plurality of scanning drivers.

  FIG. 8 shows a block diagram of a configuration example of the display system of the present embodiment including a plurality of scan drivers. In FIG. 8, the same parts as those in FIG.

In FIG. 8, the above-described organic EL panel 510 is arranged so that the upper panel 510 ₁ (first display panel in a broad sense) and the lower panel 510 ₂ (lower sense in a broad sense) are arranged in the direction in which scanning lines are arranged. In this example, two display panels (second display panels) are provided, and a display panel having the number of scanning lines twice that of the organic EL panel 510 is driven. Incidentally, those having a top panel 510 ₁ and a lower panel 510 ₂ to the arrangement direction of the scanning lines may be considered as one of the display panels.

The upper panel 510 _first data line is driven by a first data driver 520 ₁ having the same configuration as that of the data driver 520 of FIG. The upper panel 510 _first scan line is scanned by the first scan driver 530 ₁ having the same configuration as the scan driver 530 of FIG. May be a display area of the upper panel 510 ₁ first display area (Layer 1 display area), the first display region is driven by a first data driver 520 ₁ and the first scan driver 530 ₁ It will be.

Lower panel 510 and _second data lines are driven by the second data driver 520 ₂ having the same configuration as that of the data driver 520 of FIG. Lower panel 510 and _second scanning lines are scanned by the second scan driver 530 ₂ having the same configuration as the scan driver 530 of FIG. May be a display area of the lower panel 510 ₂ second display area (Layer 2 display area), the second display area is driven by the second data driver 520 ₂ and the second scan driver 530 ₂ Will be. Note that the first and second scan drivers 530 ₁ and 530 ₂ are not cascade-connected.

The display controller 540 outputs display data PDA to the _first data driver 5201 via a first display data output unit (for example, a first display data output terminal) (not shown), and a second not shown. and outputs the display data output unit (for example, the second display data output terminals) displaying data PDB to the second data driver 520 ₂ via the. On the other hand, the display controller 540 supplies a horizontal synchronization signal LP and a dot clock DCLK as display control signals to the first and second data drivers 520 ₁ and 520 ₂ in common. Further, the display controller 540 supplies a vertical synchronization signal YD and a horizontal synchronization signal LP as display control signals to the first and second scan drivers 530 ₁ and 530 ₂ in common.

Figure 9 shows the upper panel 510 ₁ and a lower panel 510 ₂ relationships of Figure 8 schematically.

The upper panel 510 ₁ and a lower panel 510 ₂ as shown in FIG. 9, a common dot clock DCLK, driven in synchronism with the horizontal synchronizing signal LP and the vertical synchronization signal YD. At this time, the upper panel ₅₁₀₁ of the data line is driven based on the display data PDA, the lower panel 510 _{and second} data lines are driven based on display data PDB.

  FIG. 10 shows a timing chart of an operation example of the display controller 540 of the present embodiment.

  In FIG. 10, display data for one scan is output in the immediately preceding horizontal scanning period so that it can be captured by the next horizontal synchronizing signal LP. The display controller 540 can output the display data PDA and PDB separately.

As described above, the display controller 540 of this embodiment can supply the display control signal to the driver (driving device) that drives the display panel in common, and can output the display data separately. Therefore, in the display system shown in FIG. 8, a display panel having a large screen size can be driven while the number of scanning lines scanned by each of the first and second scanning drivers 530 ₁ and 530 ₂ is m. Accordingly, it is possible to provide a display controller that controls a plurality of drivers so that a display panel having a large screen size can be driven while maintaining high luminance.

  Furthermore, since the number of elements constituting the display system can be reduced and the first and second display areas are synchronized with the same signal, a high-quality image can be obtained without deterioration of the image quality due to a subtle phase difference. It can be displayed on a display panel having a screen size.

2.2 Operation Mode Further, the display controller 540 in the present embodiment has at least two types of operation modes. One of these operation modes is a normal mode (first mode), and the other is a dual line drive mode (second mode). The display controller 540 has an operation mode setting register (not shown), and the host 550 sets a setting value in the operation mode setting register. By doing so, the display controller 540 can operate in an operation mode corresponding to the set value.

  FIG. 11 is an explanatory diagram of the normal mode of the display controller 540 of the present embodiment. For example, as shown in FIG. 1, when the organic EL panel is driven by one data driver, the display controller 540 is set to operate in the normal mode.

  Accordingly, the scan line of the organic EL panel in the display area DAR is scanned by the scan driver 530. The data line of the organic EL panel in the display area DAR is driven by the data driver 520.

  The storage area of the display memory 30 of the display controller 540 has first and second storage areas MAR1 and MAR2. In the first storage area MAR1 of the display memory 30, display data of the first rectangular area SAR1 in the display area DAR of the organic EL panel is stored. In the second storage area MAR2 of the display memory 30, display data of the second rectangular area SAR2 in the display area DAR of the organic EL panel is stored. Display data corresponding to the position of each dot in the first rectangular area SAR1 is stored in each storage position of the first storage area MAR1. Display data corresponding to the position of each dot in the second rectangular area SAR2 is stored in each storage position of the second storage area MAR2.

  At the supply timing of the data line in the non-overlapping area of the second rectangular area SAR2 in the first rectangular area SAR1, the display controller 540 gives the data driver 520 the first storage area MAR1 corresponding to the area. Supply display data. The display controller 540 outputs this display data as display data PDA.

  Further, at the supply timing of the data line of the second rectangular area SAR2 that does not overlap with the first rectangular area SAR1, the display controller 540 supplies the display data of the second storage area MAR2 corresponding to the area. . The display controller 540 outputs this display data as display data PDA.

  Further, the display controller 540 combines the display data of the first and second storage areas MAR1 and MAR2 corresponding to the data line supply timing of the area OVAR where the first and second rectangular areas SAR1 and SAR2 overlap. The synthesized display data is supplied. The display controller 540 outputs this combined display data as display data PDA.

  FIG. 12 is an explanatory diagram of the dual line drive mode of the display controller 540 of the present embodiment. In FIG. 12, the same parts as those in FIG. 11 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  For example, as shown in FIG. 8, when each of the two organic EL panels constituting the organic EL panel is driven by a set of scan driver and data driver, the display controller 540 is set to operate in the dual line drive mode. Is done.

Accordingly, the first and second display areas DAR11 and DAR12 are provided in the direction in which the scanning lines of the organic EL panel are arranged. The scanning line of the organic EL panel in the first display area DAR11 is scanned by the _first scanning driver 5301. The data line of the organic EL panel in the first display area DAR11 is driven by the _first data driver 5201. The scanning line of the organic EL panel in the second display area DAR12 is scanned by the _second scanning driver 5302. The data line of the organic EL panel in the second display area DAR12 is driven by the _second data driver 5202.

In the dual line drive mode, scanning of the first and second display areas DAR11 and DAR12 starts simultaneously. The display controller 540, to the first data driver 520 ₁ and supplies the display data read from the first storage area MAR1 of the display memory 30. The display controller 540 outputs this display data as display data PDA.

The display controller 540, to the second data driver 520 _2, and supplies the display data read from the second storage area MAR2 of the display memory 30. The display controller 540 outputs this display data as display data PDB.

  In this way, in the normal mode, the organic EL panel can be driven using only display data provided for each rectangular area, and in the dual line drive mode, an organic having a large screen size while maintaining high luminance. The EL panel can be driven. Such an organic EL panel can realize various image displays with a simple configuration.

2.3 Configuration Example Hereinafter, a configuration example of the display controller 540 of FIG. 7 that realizes the above-described function will be described.

  FIG. 13 shows an outline of the configuration of the setting register unit 50 of FIG.

  The setting register section 50 can include an operation mode setting register 200, a display horizontal dot number setting register 202, a display line number setting register 204, a layer 1 display area setting register 206, and a layer 2 display area setting register 208. The setting register unit 50 does not have to include all of these, and a part thereof may be omitted.

  The operation mode setting register 200 is set by the host 550 with a setting value corresponding to the normal mode (first mode) or the dual line drive mode (second mode). The display controller 540 operates as described above in an operation mode corresponding to the setting value of the operation mode setting register 200. The setting register unit 50 outputs a mode setting signal MODE corresponding to the setting value of the operation mode setting register 200.

  A set value corresponding to the number of dots in the horizontal direction of the display area shown in FIG. 11 or 12 is set in the display horizontal dot number setting register 202 by the host 550. The setting register unit 50 outputs a display horizontal dot number setting signal DN corresponding to the setting value of the display horizontal dot number setting register 202.

  In the display line number setting register 204, a set value corresponding to the number of lines in the vertical direction of the display area shown in FIG. The setting register unit 50 outputs a display line number setting signal LN corresponding to the setting value of the display line number setting register 204.

  A setting value for setting the layer 1 display area as the first display area is set in the layer 1 display area setting register 206 by the host 550. The setting register unit 50 outputs a signal corresponding to the set value. In the present embodiment, the display start position and display end position on the diagonal line of the layer 1 display area, and the read start address L1ADR of the first storage area of the display memory 30 are designated. The display start position is specified by setting the horizontal display start coordinate SA1x and the vertical display start coordinate SA1y by the host 550. The display end position is specified by setting the horizontal display end coordinate SE1x and the vertical display end coordinate SE1y by the host 550.

  A set value for setting the layer 2 display area as the second display area is set by the host 550 in the layer 2 display area setting register 208. The setting register unit 50 outputs a signal corresponding to the set value. In the present embodiment, the display start position and display end position on the diagonal line of the layer 2 display area, and the read start address L2ADR of the second storage area of the display memory 30 are designated. The display start position is specified by setting the display start coordinate SA2x in the horizontal direction and the display start coordinate SA2y in the vertical direction by the host 550. The display end position is specified by setting the horizontal display end coordinate SE2x and the vertical display end coordinate SE2y by the host 550.

  FIG. 14 shows a block diagram of a configuration example of the memory controller 42 of FIG.

  The memory controller 42 includes a display memory address calculation unit 250, a display memory access unit 260, and a timing control unit 270.

  The display memory address calculation unit 250 obtains a relative address in the first storage area MAR1 of the display memory 30 using the set value of the layer 1 display area setting register 206. The display memory address calculation unit 250 obtains a relative address in the second storage area MAR2 of the display memory 30 using the set value of the layer 2 display area setting register 208. Since the number of bits of display data per dot and the size of each display area of the layer 1 display area and the layer 2 display area are known, the display memory address calculation unit 250 has a known configuration and a display start position and a display end. A relative address for specifying the storage position of the first and second storage areas MAR1 and MAR2 corresponding to the position can be generated.

  The display memory access unit 260 generates a read address for reading display data from the first and second storage areas MAR1 and MAR2 of the display memory 30. More specifically, the display memory access unit 260 uses the read start address L1ADR and the relative address in the first storage area MAR1 obtained by the display memory address calculation unit 250 to use the first storage area MAR1. A read address RDAR1 for reading display data from is generated. The display memory access unit 260 reads display data from the second storage area MAR2 using the read head address L2ADR and the relative address in the second storage area MAR2 obtained by the display memory address calculation unit 250. A read address RDAR2 is generated.

  The display memory access unit 260 outputs the read requests RDRQ1, RDRQ2 and the read addresses RDAR1, RDAR2 to the display memory 30 based on the control timing from the timing control unit 270, and the read approvals RDACK1, RDACK2 from the display memory 30 The read addresses RDAR1 and RDAR2 are updated based on the above.

  The timing control unit 270 uses the first display area designation signal L1VIEW indicating the display timing of the first display area and the second display area indicating the display timing of the second display area as the control timing described above. A display area designation signal L2VIEW is generated. The timing at which both the first and second display area designation signals L1VIEW and L2VIEW are designated at the same time is the display timing of the area where the first and second display areas overlap.

  FIG. 15 shows a block diagram of a configuration example of the timing control unit 270 of FIG.

  Timing control unit 270 includes a layer 1 display area designating unit 300 and a layer 2 display area designating unit 320. Since the configuration of the layer 2 display area designating unit 320 is the same as that of the layer 1 display area designating unit 300, the layer 1 display area designating unit 300 will be described below, and the description of the layer 2 display area designating unit 320 will be omitted. To do.

  The layer 1 display area designating unit 300 includes a line counter 302, a pixel counter 304, and magnitude comparators 306, 308, 310, and 312. The count values of the line counter 302 and the pixel counter 304 are initialized when the vertical synchronization signal YD becomes active.

  The line counter 302 counts the number of scanning lines scanned after the start timing of one vertical scanning period. More specifically, the line counter 302 counts up the count value in synchronization with the horizontal synchronization signal LP. The line counter 302 counts up to the number of lines specified by the display line number setting signal LN, and then the count value is initialized.

  The pixel counter 304 counts the number of pixels in the horizontal direction after the start timing of one horizontal scanning period. More specifically, the pixel counter 304 counts up the count value in synchronization with the dot clock DCLK. The pixel counter 304 counts up to the number of pixels corresponding to the number of dots specified by the display horizontal dot number setting signal DN, and then the count value is initialized.

  The magnitude comparator 306 compares the count value of the line counter 302 with the vertical display start coordinate SA1y, and activates the output when the count value of the line counter 302 is equal to or greater than the vertical display start coordinate SA1y.

  The magnitude comparator 308 compares the count value of the line counter 302 with the vertical display end coordinate SE1y, and activates the output when the count value of the line counter 302 is equal to or greater than the vertical display end coordinate SE1y.

  Therefore, when the output of the magnitude comparator 306 is active and the output of the magnitude comparator 308 is inactive, the scanning timing in the vertical direction of the layer 1 display area is reached. The output of the logic circuit 316 becomes active when the output of the magnitude comparator 306 is active and the output of the magnitude comparator 308 is inactive.

  The magnitude comparator 310 compares the count value of the pixel counter 304 with the horizontal display start coordinate SA1x, and activates the output when the count value of the pixel counter 304 is equal to or greater than the horizontal display start coordinate SA1x.

  The magnitude comparator 312 compares the count value of the pixel counter 304 with the horizontal display end coordinate SE1x, and activates the output when the count value of the pixel counter 304 is equal to or greater than the horizontal display end coordinate SE1x.

  Accordingly, when the output of the magnitude comparator 310 is active and the output of the magnitude comparator 312 is inactive, the horizontal scanning timing of the layer 1 display area is reached. The output of the logic circuit 318 becomes active when the output of the magnitude comparator 310 is active and the output of the magnitude comparator 312 is inactive.

  The first display area designating signal L1VIEW is a logical product operation result of the outputs of the logic circuits 316 and 318.

  The second display area designation signal L2VIEW can also be generated by replacing SA1y with SA2y, SE1y with SE2y, SA1x with SA2x, and SE1x with SE2x in the description of the layer 1 display area designating unit 300 described above.

  The display memory access unit 260 in FIG. 14 performs read access to the display memory 30 at the scanning timing designated by the first and second display area designation signals L1VIEW and L2VIEW generated by the timing control unit 270 as described above. .

  FIG. 16 shows an outline of the configuration of the driver signal generation unit 22 of FIG. A part of the configuration shown in FIG. 16 may be omitted.

  The driver signal generation unit 22 includes a GCLK generation unit (gradation clock generation unit) 350, a display control signal generation unit 360, and a display data supply processing unit 370.

  The GCLK generation unit 350 generates a gradation clock GCLK in which each edge (rise timing or fall timing) of each gradation pulse of a plurality of gradation pulses is set based on the setting value of the gradation pulse width setting register 352. To do. The gradation pulse width setting register 352 is also included in the setting register unit 50, and the host 550 can access the gradation pulse width setting register 352 and set a setting value. The GCLK generation unit 350 includes, for example, a counter, compares the setting value of the gradation pulse width setting register 352 with the count value of the counter, and generates a pulse based on the comparison result, whereby the edge of each gradation pulse is changed. A gradation clock GCLK having a plurality of gradation pulses set by the gradation pulse width setting register 352 can be generated.

  The display control signal generator 360 generates a dot clock DCLK having a frequency corresponding to the set value of the DCLK setting register 362. The DCLK setting register 362 is also included in the setting register unit 50 so that the host 550 can access the DCLK setting register 362 and set a setting value.

  The display control signal generator 360 generates a vertical synchronization signal YD having a period corresponding to the set value of the YD setting register 364. A YD setting register 364 is also included in the setting register unit 50 so that the host 550 can access the YD setting register 364 and set a setting value.

  The display control signal generator 360 generates a horizontal synchronization signal LP having a period corresponding to the set value of the LP setting register 366. An LP setting register 366 is also included in the setting register unit 50 so that the host 550 can access the LP setting register 366 and set a setting value.

  Further, the display control signal generator 360 generates a discharge signal DIS that becomes active at a timing corresponding to the set value of the DIS setting register 368. The DIS setting register 368 is also included in the setting register unit 50 so that the host 550 can access the DIS setting register 368 and set a setting value.

  The display control signal generation unit 360 includes a counter, for example, and compares the set value of each setting register with the count value of the counter, and can generate each of the display control signals based on the comparison result.

  The display data supply processing unit 370 includes first and second display data output units 372 and 374. The first display data output unit 372 is a first data driver that drives the data lines in the first display area among the first and second display areas provided in the direction in which the scanning lines of the organic EL panel are arranged. On the other hand, display data read from the first storage area of the display memory can be supplied. The second display data output unit 374 can supply the display data read from the second storage area of the display memory to the second data driver that drives the data lines of the second display area. ing.

  FIG. 17 shows a block diagram of a configuration example of the display data supply processing unit 370 of FIG.

  The display data supply processing unit 370 can include a display data output processing unit 376 and an overlay processing unit (composite processing unit in a broad sense) 378 in addition to the first and second display data output units 372 and 374. .

  The display data output processing unit 376 performs retiming processing on the display data from the display memory 30, and superimposes the display data after the retiming processing on the overlay processing unit 378, the first and second display data output units 372, Output to 374.

  The overlay processing unit 378 generates display data of an area where the first and second display areas overlap as composite display data. More specifically, the overlay processing unit 378 performs a process of overlaying the display data of the first display area and the display data of the second display area. As this processing, for example, the display data in the first display area is selected with priority, or conversely, the display data in the second display area is selected with priority, or the first and second display areas are displayed. The result of logical OR operation, logical product operation, exclusive OR operation, or exclusive OR operation is output, or the blend value α (0 ≦ 0) is displayed on one of the display data in the first and second display areas. [alpha] ≦ 1, [alpha] is a real number), and the other is multiplied by (1- [alpha]) to add both.

  The composite display data after such superposition processing is output to the first display data output unit 372 among the first and second display data output units 372 and 374.

  FIG. 18 is a block diagram showing a configuration example of the first and second display data output units 372 and 374 in FIG. In FIG. 18, the same parts as those in FIG. 17 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  The first display data output unit 372 includes a selection processing circuit SP and selectors SEL1, SEL2. The selection processing circuit SP receives the display data DA of the first display area, the display data DB of the second display area, and the composite display data DMix in dot units in synchronization with the dot clock DCLK. The setting register unit 50 includes a background display data setting register (not shown) for designating the color of the display area outside the first or second display area as the background color among the display areas of the organic EL panel. The display data BD corresponding to the background color set by the host 550 in the background display data setting register is input to the selection processing circuit SP.

  The selection processing circuit SP performs a selection process of the display data PDA output from the first display data output unit 372 based on the first and second display area designation signals L1VIEW and L2VIEW.

  FIG. 19 shows a truth table of an operation example of the selection processing circuit SP of FIG.

  When the first and second display area designation signals L1VIEW and L2VIEW are inactive, the selection processing circuit SP outputs display data BD corresponding to a background color set in a background display data setting register (not shown).

  When the first display area designation signal L1VIEW is inactive and the second display area designation signal L2VIEW is active, the selection processing circuit SP outputs the display data DB of the second display area.

  When the first display area designating signal L1VIEW is active and the second display area designating signal L2VIEW is inactive, the selection processing circuit SP outputs the display data DA for the first display area.

  When the first and second display area designation signals L1VIEW and L2VIEW are active, the selection processing circuit SP outputs the composite display data DMix.

  In FIG. 18, the selector SEL1 outputs the display data DA of the first display area when the first display area designation signal L1VIEW is active, and displays the background color when the first display area designation signal L1VIEW is inactive. Data BD is output. The selector SEL2 selects the output of the selector SEL1 when the mode setting signal MODE is active, and selects the output of the selection processing circuit SP when the mode setting signal MODE is inactive. Thus, the selector SEL2 can output data in which display data read from the first storage area, display data read from the second storage area, and composite display data are mixed.

  The second display data output unit 374 includes a selector SEL3. The selector SEL3 outputs the display data DB of the second display area when the mode setting signal MODE is active and the second display area designating signal L2VIEW is active, and in other cases, the selector SEL3 outputs to the background display data setting register (not shown). Display data BD corresponding to the set background color is output. In this manner, the selector SEL3 can output data in which display data read from the second storage area and display data of the background color are mixed.

  The first and second display data output units 372 and 374 sequentially output the data thus selected to the data driver in synchronization with the dot clock DCLK.

  Note that the present invention is not limited to the configuration of the present embodiment, and display data read from the first storage area, display data read from the second storage area, and composition according to the scanning timing of the display panel. It is only necessary that data in which at least two pieces of display data are mixed can be output via one of the first and second display data output units 372 and 374.

  In this way, the composite display data can be output via one of the first and second display data output units 372 and 374 as the display data of the area where the first and second rectangular areas overlap. Then, after generating the display data after the synthesis processing, the display data read from the first or second storage area and the data in which the composite display data is mixed are first changed according to the scanning timing of the display panel. And can be output via one of the second display data output units 372 and 374.

  As described above, display data can be separately supplied to the first and second data drivers that drive the data lines in the first and second display areas provided in the direction in which the scanning lines are arranged. By doing this, even when the number of scanning lines in each display area of the first and second display areas is small, each of the display areas is scanned separately, and a window display is displayed in each display area. One image can be displayed. Accordingly, it is possible to display an image as a panel having a large screen size while maintaining a high luminance by using a plurality of panels having a limited number of scanning lines.

  In particular, when one image is displayed using two panels, a shift in drive timing between both the panels becomes noticeable as image disturbance. Accordingly, the first and second display data output units 372 and 374 supply display data separately to drivers that drive the display system as shown in FIG. 8, while the vertical synchronization signal YD, the horizontal synchronization signal LP, and the like. By supplying the dot clock DCLK in common, even a panel with a limited number of scanning lines can drive a panel with a large screen size while maintaining high luminance.

  In addition, with a simple configuration, it is possible to realize various image displays while preventing deterioration of image quality.

2.4 Operation Example FIG. 20 shows a timing chart of an operation example of PWM performed by the display controller 540 of the present embodiment. FIG. 20 shows a timing chart of an operation example of the _first data driver 5201 that generates a PWM signal using the grayscale clock GCLK.

  When a pulse of the vertical synchronization signal YD is input from the display controller 540, one vertical scanning period is started. When the pulse of the horizontal synchronization signal LP is input from the display controller 540 during the period in which the vertical synchronization signal YD is at the H level, one horizontal scanning period is started. Further, the horizontal display period is started with the timing at which the discharge signal DIS from the display controller 540 changes from the H level to the L level as a reference timing. The horizontal display period ends when the next discharge signal DIS changes to the H level.

  In the horizontal display period, the display controller 540 outputs the dot clock DCLK and sequentially outputs gradation data in synchronization with the dot clock DCLK. In addition, the GCLK generation unit 350 outputs the grayscale clock GCLK having a pulse in which the timing of each edge is set based on the setting value of the grayscale pulse width setting register 352 within the horizontal display period.

  The data driver 520 that fetches the gradation data from the display controller 540 into the shift register 522 latches the gradation data in one horizontal scanning unit in the line latch 524 by the horizontal synchronization signal LP during the period when the discharge signal DIS is at the H level. To do. Therefore, the data driver 520 generates the PWM signal PWMG corresponding to the gradation data in the horizontal scanning period next to the horizontal scanning period in which the gradation data from the display controller 540 is supplied. In FIG. 20, since the gradation data is “2”, the pulse width of the PWM signal PWMG is a period from the falling edge of the discharge signal DIS to the edge of the second gradation pulse. In this way, since the interval can be varied for each gradation pulse of the gradation clock, a PWM signal having a finely settable width can be generated.

  Further, the blanking period is adjusted by the discharge signal DIS to make the horizontal display period variable, and the interval between the grayscale pulses can be varied within the horizontal display period. Thereby, the pulse width of the PWM signal can be set as an absolute value according to the size of the organic EL panel and the type of the organic EL element, so that desired gradation expression can be easily performed.

  In FIG. 20, the interval between the reference timing and the gradation pulse or the interval between the gradation pulses is set at the rising edge of each gradation pulse. However, the interval is set at the falling edge of each gradation pulse. It may be.

FIG. 20 shows an example of the operation of the _first data driver 5201. The same applies to the _second data driver 5202.

  The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist of the present invention. For example, the present invention is not limited to being applied to driving the organic EL panel described above, but can be applied to driving liquid crystal display devices and plasma display devices.

  In the invention according to the dependent claims of the present invention, a part of the constituent features of the dependent claims can be omitted. Moreover, the principal part of the invention according to one independent claim of the present invention can be made dependent on another independent claim.

The block diagram of the structural example of a display system. Explanatory drawing of the structure of an organic EL element. FIG. 2 is a block diagram of a configuration example of a data driver in FIG. 1. FIG. 2 is a block diagram of a configuration example of a scan driver in FIG. 1. The figure which shows an example of the electrical equivalent circuit of an organic EL element. The figure for demonstrating discharge operation. The block diagram of the outline | summary of a structure of the display controller in this embodiment. The block diagram of the structural example of the display system containing a some scanning driver. The figure which shows typically the relationship between the upper side panel of FIG. 8, and a lower side panel. The timing diagram of the example of operation of the display controller of this embodiment. Explanatory drawing of the normal mode of the display controller of this embodiment. Explanatory drawing of the dual line drive mode of the display controller of this embodiment. The figure which shows the outline | summary of a structure of the setting register part of FIG. FIG. 8 is a block diagram of a configuration example of the memory controller in FIG. 7. The block diagram of the structural example of the timing control part of FIG. The figure which shows the outline | summary of a structure of the driver signal generation part of FIG. The block diagram of the structural example of the display data supply process part of FIG. FIG. 18 is a block diagram of a configuration example of first and second display data output units in FIG. 17. The figure which shows the truth table of the operation example of the selection processing circuit of FIG. The timing diagram of the operation example of PWM performed by the display controller of this embodiment.

Explanation of symbols

10 host I / F, 20 driver I / F, 22 driver signal generator,
30 display memory, 40 control unit, 42 memory controller,
50 setting register section, 510 organic EL panel, 510 ₁ upper panel,
510 ₂ Lower panel, 520 Data driver,
520 ₁ first data driver, 520 ₂ second data driver,
530 scan driver, 530 ₁ first scan driver,
530 ₂ second scan driver, 540 display controller, 550 host,
DCLK dot clock, DN display horizontal dot number setting signal,
L1ADR, L2ADR start address, LN display line number setting signal,
LP horizontal synchronization signal, MAR1 first storage area, MAR2 second storage area,
OVAR overlap area, PDA, PDB display data,
SA1x, SA2x horizontal display start coordinates,
SA1y, SA2y vertical display start coordinates, SAR1 first rectangular area,
SAR2 second rectangular area, SE1x, SE2x horizontal display end coordinates,
SE1y, SE2y Vertical display end coordinates, YD Vertical synchronization signal

Claims (10)

A display controller for controlling first and second data drivers for driving a plurality of data lines of a display panel,
A display memory having first and second storage areas for storing display data of first and second rectangular areas in the display area of the display panel;
Of the first and second display areas provided in the direction in which the scanning lines of the display panel are arranged, the first data driver for driving the data lines in the first display area is provided with respect to the first data driver of the display memory. A first display data output unit for supplying display data read from one storage area;
A second display data output unit for supplying display data read from the second storage area of the display memory to the second data driver that drives the data lines of the second display area And a display controller. In claim 1,
A display control signal generator that generates a vertical synchronization signal that defines one vertical scanning period, a horizontal synchronization signal that defines a horizontal scanning period, and a dot clock that defines the supply timing of display data of pixels;
The horizontal synchronization signal and the dot clock are commonly supplied to the first and second data drivers, and the vertical synchronization signal and the horizontal synchronization signal are scanned through the scanning lines of the first rectangular area. And a second scanning driver that scans the scanning lines of the second rectangular area. In claim 1 or 2,
An operation mode setting register for setting an operation mode of the display controller;
Combining display data read from the first storage area and display data read from the second storage area as display data of the area where the first and second rectangular areas overlap Including a synthesis processing unit for generating display data,
When the first mode is set by the operation mode setting register,
The display data read from the first storage area, the display data read from the second storage area, and the composite display data are output via the first display data output unit,
When the second mode is set by the operation mode setting register,
The display data read from the first storage area is output via the first display data output unit, and the display data read from the second storage area is output to the second display data. And outputting the composite display data as display data of an area where the first and second rectangular areas overlap through one of the first and second display data output sections. Characteristic display controller. In claim 3,
When the second mode is set by the operation mode setting register,
After the display data after the combining process is generated by the combining processing unit, the display data read from the first storage area and the second storage area are read according to the scanning timing of the display panel. A display controller that outputs data in which at least two of the display data and the composite display data are mixed, via one of the first and second display data output units. A plurality of scan lines;
Multiple data lines,
A display panel including a plurality of pixels;
First and second scan drivers that scan the scan lines of the first and second display areas of the display panel;
First and second data drivers for driving the plurality of data lines;
A display controller according to any one of claims 1 to 4,
The display controller is
A display system for supplying display data to the first and second data drivers. Each display panel includes a plurality of scanning lines, a plurality of data lines, and a plurality of pixels, and the first and second display panels provided in the alignment direction of the scanning lines;
First and second scan drivers that scan the scan lines of the first and second display panels;
A first data driver that drives a plurality of data lines of the first display panel as data lines of the first display area;
A second data driver for driving a plurality of data lines of the second display panel as data lines of the second display region;
A display controller according to any one of claims 1 to 4,
The display controller is
A display system for supplying display data to the first and second data drivers. In claim 5 or 6,
Each of the plurality of pixels includes an electroluminescence element. A display control method for controlling first and second data drivers for driving the data lines of a display panel including a plurality of scanning lines and a plurality of data lines,
Of the first and second display areas provided in the direction in which the scanning lines of the display panel are arranged, the first data driver for driving the data lines in the first display area is provided with the first display memory. In addition to supplying display data read from the storage area of
Supplying the display data read from the second storage area of the display memory to the second data driver that drives the data lines of the second display area;
The first and second data drivers are commonly supplied with a horizontal synchronization signal that defines one horizontal scanning period and a dot clock that defines the supply timing of pixel display data, and vertical synchronization that defines one vertical scanning period. The signal and the horizontal synchronization signal are commonly supplied to a first scan driver that scans the scan lines of the first display area and a second scan driver that scans the scan lines of the second display area. A characteristic display control method. In claim 8,
Display data read from the first storage area, display data read from the second storage area, and display read from the first storage area when set to the first mode Supplying combined display data obtained by combining the data and the display data read from the second storage area to one data driver that drives the data lines of the display panel;
When the second mode is set, the display data read from the first storage area is output to the first data driver, and the display data read from the second storage area is output. Is output to the second data driver. In claim 9,
The display data read from the first storage area according to the scanning timing of the display panel after the composite display data is generated when the second mode is set, the second storage area A display control method comprising: outputting data in which at least two of display data read out from the display data and display data after the synthesis process are mixed.

Images