JP2004317576A - Driving circuit, driving method, electrooptical device, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform gradation display of pixels while maintaining the aperture rate of pixels at a high level. <P>SOLUTION: A driving circuit (a scanning driver) 100 is provided with a shift register 120 which sequentially designates a choosing period for choosing, for a plurality of pixels, whether a pixel 32 is to be made to emit light or to quench light based on a reference clock signal CLK, a memory circuit 140 which stores light emission information indicating whether the pixel 32 is to be made to emit light or quench light, and a selection circuit 160 for selecting, based on the light emission information during the selection period, whether the pixel is to be made to emit light or to quench light. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a driving circuit for driving an electro-optical element, a driving method, an electro-optical device, and an electronic apparatus.
[0002]
[Background technology]
2. Description of the Related Art As a conventional light emitting device that performs gradation display by controlling a light emitting time of a light emitting element, there is one disclosed in JP-A-2001-343933 (Patent Document 1). The light emitting device disclosed in Patent Document 1 has an erasing transistor that controls driving of a driving transistor that drives a light emitting element. Then, by driving the erasing transistor, light emission of the light emitting element is stopped, and the light emitting time of the light emitting element is controlled.
[0003]
[Patent Document 1]
JP 2000-343933 A
[0004]
[Problems to be solved by the invention]
However, in the light emitting device disclosed in Patent Document 1, since an erasing transistor and an erasing gate signal line must be provided in order to stop light emission of a light emitting element, there is a problem that an aperture ratio in a pixel is reduced. Had occurred.
[0005]
Therefore, an object of the present invention is to provide a driving circuit, a driving method, an electro-optical device, and an electronic device that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous embodiments of the present invention.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, according to a first aspect of the present invention, there is provided a drive circuit for driving a plurality of electro-optical elements, based on a reference clock, whether the electro-optical elements should emit light or be quenched. A shift register for sequentially selecting a selection period, which is a period for selection, for the plurality of electro-optical elements, a storage unit for storing light-emitting information indicating whether the electro-optical element should emit light or to extinguish, and A selection unit for selecting whether to perform extinction or not in the selection period based on the light emission information. Thus, the pixel including the electro-optical element can be displayed in a gray scale while the aperture ratio of the pixel is kept high.
[0007]
Preferably, the shift register generates a timing signal indicating the selection period by changing a logic value, and the storage unit updates the light emission information based on the change in the logic value. Thereby, light emission and non-light emission of the electro-optical element can be easily controlled.
[0008]
Further, the shift register sequentially generates a first timing signal and a second timing signal based on the reference clock, and the storage unit stores a first timing signal and a second timing signal based on the first timing signal. Updating first light-emitting information, which is the light-emitting information of the electro-optical element, and updating second light-emitting information, which is the light-emitting information of a second electro-optical element, based on the second timing signal It is preferable that the selection unit selects whether the first electro-optical element emits light or extinguishes the light based on the first emission information and the second timing signal. As a result, it is possible to secure a sufficient margin for the light emitting and quenching selection operation of the electro-optical element.
[0009]
In addition, the selection unit is, in synchronization with the timing signal, a light emission signal generation unit that generates a light emission signal whose phase changes based on the light emission information, and based on the timing signal and the light emission signal, the electro-optical element A selection signal generation unit that generates a selection signal for selecting light emission or extinction. Thus, light emission and extinction of the electro-optical element can be controlled by selecting a predetermined range in the selection period.
[0010]
In addition, the apparatus further includes a selection clock signal synchronized with the reference clock, and a selection clock signal generation unit that generates an inverted selection clock signal obtained by inverting the selection clock signal.The light emission signal generation unit, based on the light emission information, It is preferable that the light emission signal is generated by selecting and outputting one of the selection clock signal and the inverted selection clock signal. Thereby, the phase of the light emission signal can be easily controlled.
[0011]
Further, the selection clock signal is a signal indicating H logic and L logic, and it is preferable that a period indicating the H logic is different from a period indicating the L logic. As a result, it is possible to secure a sufficient time for writing data to the electro-optical element.
[0012]
Preferably, the electro-optical element is an organic electroluminescence element. Thereby, a non-light emitting period can be given to the organic electroluminescence element, and thus element deterioration can be reduced.
[0013]
According to a second aspect of the present invention, there is provided an electro-optical device including the driving circuit. Here, the electro-optical device generally refers to a device having an electro-optical element that emits light by an electric action or changes a state of external light, and controls a device that emits light by itself and a passage of external light. Including both. For example, as the electro-optical element, in addition to the above-described organic electroluminescent element, a liquid crystal element, an electrophoretic element, an electron emitting element that emits light by applying electrons generated by application of an electric field to a light emitting plate, and the like can be given.
[0014]
According to a third aspect of the present invention, there is provided an electronic apparatus including the above-described electro-optical device. Here, the electronic apparatus generally refers to an apparatus that performs a certain function by a combination of a plurality of elements or circuits, and includes, for example, an electro-optical device and a memory. Here, the electronic device can include one or more circuit boards. Although the configuration is not particularly limited, for example, an IC card, a mobile phone, a video camera, a personal computer, a head-mounted display, a rear or front type projector, a facsimile apparatus with a display function, a finder of a digital camera, and a portable TV , A DSP device, a PDA, an electronic organizer, an electronic bulletin board, a display for advertising, and the like.
[0015]
According to a fourth aspect of the present invention, there is provided a driving method for driving a plurality of electro-optical elements, wherein a selection period, which is a period for selecting whether to emit or extinguish the electro-optical elements, based on a reference clock. A setting step for sequentially determining a plurality of electro-optical elements, a storing step of storing light-emitting information indicating whether the electro-optical element should emit light or quenching, and a step of storing the electro-optical element to emit light or quenching based on the light-emitting information. And a selection step of selecting during a selection period.
[0016]
Preferably, in the setting step, a timing signal indicating the selection period is generated by changing the logical value, and in the storing step, the light emission information is updated based on the change in the logical value.
[0017]
The setting step sequentially generates a first timing signal and a second timing signal based on a reference clock, and the storing step includes a step of storing light emission information of the first electro-optical element based on the first timing signal. Is updated, and based on the second timing signal, the second emission information that is the emission information of the second electro-optical element is updated. The selecting step includes the first emission information and the first emission information. It is preferable to select whether the first electro-optical element emits light or extinguishes it based on the second timing signal.
[0018]
The selecting step includes a light emitting signal generating step of generating a light emitting signal whose phase changes based on the light emitting information, synchronized with the timing signal, and selecting light emitting or quenching of the electro-optical element based on the timing signal and the light emitting signal. And a selection signal generating step of generating a selection signal to be performed.
[0019]
The driving method further includes a selection clock signal synchronized with the reference clock, and a selection clock signal generation step of generating an inverted selection clock signal obtained by inverting the selection clock signal.The light emission signal generation step is based on light emission information. It is preferable to generate a light emission signal by selecting and outputting either the selected clock signal or the inverted selected clock signal.
[0020]
In the selection clock signal generation step, it is preferable to generate a clock signal indicating a H logic and an L logic as a selection signal, wherein the period indicating the H logic is different from the period indicating the L logic. Further, it is preferable that the electro-optical element is an organic electroluminescent element.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described through embodiments of the present invention with reference to the drawings, but the following embodiments do not limit the invention according to the claims and are described in the embodiments. Not all combinations of features are essential to the solution of the invention.
[0022]
FIG. 1 is a diagram showing an organic EL (Electro Luminescence) display device 10 which is an example of an electro-optical device according to an embodiment of the present invention. The organic EL display device 10 includes a scan driver 100 as an example of a drive circuit, a data driver 20, a display unit 30 having a plurality of pixels 32 including organic EL elements, a scan line 40, a data line 42, An EL power supply line 46 for supplying power to the EL element is provided.
[0023]
The scanning driver 100 includes a shift register 120, a memory circuit 140 as an example of a storage unit, and a selection circuit 160 as an example of a selection unit. The data driver 20 has a shift register 22, a first latch circuit 24, a second latch circuit 26, and a reset circuit 28. The output of the scan driver 100 is electrically connected to the plurality of scan lines 40, and the data driver 20 is electrically connected to the plurality of data lines 42. The pixel 32 includes a pixel 32R for displaying red (R), a pixel 32G for displaying green (G), and a pixel 32B for displaying blue (B). 40 and any of the data lines 42.
[0024]
Next, the operation of the data driver 20 will be described. After the reset circuit 28 supplies the reset signal RST to the data line 42 to reset the data line 42, the shift register 22 sequentially shifts the supplied start pulse SP to the subsequent stage in synchronization with the reference clock. Output sequentially. The first latch circuit 24 captures the image signals VIDR, VIDG, and VIDG corresponding to the respective pixels 32R, G, and B in synchronization with the output of the shift register 22, and holds data indicated by the image signals. . The data held in the first latch circuit 24 is supplied to the second latch circuit 26 based on the latch pulse LP. Then, the data held in the second latch circuit 26 is supplied from the scan driver 100 to the selected pixel 32 via the scan line 40 to switch between display and non-display of the pixel 32.
[0025]
FIG. 2 is a diagram illustrating an example of the pixel 32. The pixel 32 includes a selection transistor 52, a storage capacitor 54, a driving transistor 56, and an organic EL element 58. The selection transistor 52 has a gate electrically connected to the scanning line 40 and a source or drain electrically connected to the data line 42. The storage capacitor 54 has one end electrically connected to the drain or source of the selection transistor 52, and the other end electrically connected to the EL power supply line 46, and stores the charge supplied from the EL power supply line 46. I do. The drive transistor 56 has a gate electrically connected to the drain or source of the selection transistor 52 and the one end of the storage capacitor 54, and a source or drain electrically connected to the EL power supply line 46. The organic EL element 58 has one end electrically connected to the EL power supply line 46 via the drive transistor 56, and emits light based on the voltage supplied from the EL power supply line 46.
[0026]
The operation of the pixel 32 will be described. To the scanning line 40, a selection signal SEG indicating a light emitting state of the pixel 32 corresponding to the scanning line 40, for example, a selection period which is a period for selecting whether to emit or extinguish the pixel 32 is supplied from the scanning driver 100. Is done. The selection transistor 52 turns on the selection transistor 52 in accordance with the logical value indicated by the selection signal SEG supplied to the gate.
[0027]
A data signal DAT indicating light emission or extinction of the pixel 32 corresponding to the data line 42 is supplied from the data driver 20 to the data line 42. When the selection transistor 52 is conducting, the data signal DAT is supplied to the gate of the driving transistor 56. The drive transistor 56 supplies the voltage applied to the EL power supply line 46 to the organic EL element 58 by turning on the drive transistor 56 in accordance with the logical value indicated by the supplied data signal DAT. Thereby, the organic EL element 58 emits light based on the supplied voltage. The drive transistor 56 stops supplying the voltage from the EL power supply line 46 to the organic EL element 58 by turning off the drive transistor 56 according to the logical value indicated by the supplied data signal DAT. . Thereby, the organic EL element 58 is extinguished.
[0028]
The storage capacitor 54 holds a charge based on the voltage supplied from the EL power supply line 46 and is applied to the gate of the drive transistor 56 for a predetermined period after the selection transistor 52 is turned off. The voltage can be kept lower than the threshold value of the driving transistor 56. Therefore, even after the selection transistor 52 is turned off, the driving transistor 56 can be turned on for a predetermined period, so that a voltage can be supplied to the organic EL element 58. That is, after receiving the instruction to emit the organic EL element 58 from the scanning driver 100 and the data driver 20, the pixel 32 emits the organic EL element 58 until receiving the instruction to turn off the organic EL element 58. Can be.
[0029]
FIG. 3 is a diagram illustrating an example of a circuit configuration of the scan driver 100. The scan driver 100 includes a shift register 120, a memory circuit 140, a selection circuit 160, a reference clock generator 110 and an inverted reference clock generator 112, a start pulse generator 114, a selected clock signal generator 172, and an inverted selection It has a clock signal generator 174 and a reset signal generator 176. The scanning driver 100 has a plurality of outputs, and the scanning lines 40 are electrically connected to the outputs.
[0030]
The shift register 120 has a plurality of stages of holding circuits 122 provided corresponding to outputs of the shift register 120, respectively. The holding circuit 122 includes inverter circuits 124, 126, 128, and 132 and a NAND circuit 130. The holding circuit 122 changes the logical value of the input start pulse SP based on the change in the logical value of the reference clock signal CLK and / or the inverted reference clock signal ZCLK to the light emitting state of the pixel 32 corresponding to the holding circuit 122. The signal is output as the timing signal U indicating the selection period to be selected and is supplied to the holding circuit 122 in the subsequent stage.
[0031]
The memory circuit 140 has a plurality of latch circuits 142 provided corresponding to outputs of the shift register 120, respectively. The latch circuit 142 includes inverter circuits 144, 146, and 148, and a NOR circuit 150. The latch circuit 142 holds a predetermined logical value, and outputs the held logical value as light emission information indicating whether the pixel 32 corresponding to the latch circuit 142 should emit light or should be extinguished. The latch circuit 142 updates the light emission information by changing the held logic value based on the change in the logic value of the timing signal U received as an input, and outputs the updated light emission information.
[0032]
The selection circuit 160 includes a plurality of phase control circuits 162 that are examples of a light emission signal generation unit, and a NAND circuit 180 and an inverter circuit 182 that are examples of a selection signal generation unit. And The phase control circuit 162 includes an inverter circuit 164 and NAND circuits 166, 168, and 170. The phase control circuit 162 selects one of the selection clock signal INH and the inverted selection clock signal ZINH based on the light emission information received from the latch circuit 142, and outputs the selected signal as the light emission signal T indicating the light emission information. The NAND circuit 180 and the inverter circuit 182 generate a selection signal SEG indicating a period for selecting the scanning line 40 electrically connected to the corresponding pixel 32 by taking the logical product of the timing signal U and the light emission signal T. Then, the data is output to the scanning line 40.
[0033]
FIG. 4 shows a timing chart of the scanning driver 100. The operation of the scan driver 100 will be described with reference to FIGS. In the figure, the timing signal U output from the holding circuit 122 at the n-th stage (n is a positive integer) is referred to as a timing signal Un. The light emission signal T output from the phase control circuit 162 at the n-th stage is referred to as a light emission signal Tn. The selection signal SEG output to the scanning line 40 corresponding to the n-th holding circuit 122 and the phase control circuit 162 is referred to as a selection signal SEGn.
[0034]
First, in an initial state, the reset signal RST indicates H logic. As a result, the signal output from the latch circuit 142 indicates L logic, and the light emission signal T, which is the NAND of the signal and the selected clock signal INH, has the opposite phase to the selected clock signal INH in all the phase control circuits 162. Having.
[0035]
Next, after the reset signal RST is set to L logic, the start pulse SP is supplied to the shift register 120. Then, in response to the rising edges of the reference clock signal CLK and the inverted reference clock signal ZCLK, the logical value of the supplied start pulse SP indicates a selection period in which the light emission state of the pixel 32 corresponding to the holding circuit 122 is selected. The signal is output from the holding circuit 122 as the signal U, and is also supplied to the subsequent holding circuit 122. In the present embodiment, a period in which the timing signal Un indicates H logic (a half cycle of the reference clock signal CLK) is a selection period for selecting a light emitting state of the pixel 32 corresponding to the n-th holding circuit 122.
[0036]
Next, the timing signal Un output from the shift register 120 is supplied to the latch circuit 142. Then, according to the change in the logical value of the timing signal Un, the light emission information of the pixel 32 held in the n-th latch circuit 142 is updated. In the present embodiment, the light emission information held in the latch circuit 142 is updated by changing the logical value held in the n-th latch circuit 142 according to the rising edge of the timing signal Un. Specifically, in the initial state, L logic indicating extinction is held in the latch circuit 142. However, according to the rising edge of the supplied timing signal Un, the held logic value changes to L indicating extinction. The logic changes from logic to H logic indicating light emission, and is supplied to the phase control circuit 162. Here, the light emission information indicates, when the scanning line 40 corresponding to the latch circuit 142 is selected by the selection signal SEG, which is supplied to the corresponding pixel 32 and whether the pixel 32 emits light or is extinguished. Information.
[0037]
The phase of the light emission signal Tn changes according to a change in light emission information supplied to the phase control circuit 162. That is, in the initial state, the light emission signal Tn has the opposite phase to the selected clock signal INH, but the logical value supplied to the phase control circuit 162 changes from the L logic to the H logic, so that the logical value and the selected clock signal are changed. The phase of the light-emitting signal Tn, which is the NAND of the signal INH, is the same as the phase of the selected clock signal INH.
[0038]
Then, in the NAND circuit 180 and the inverter circuit 182, the logical product of the timing signal Un and the light emission signal Tn is taken, so that the first half of the selection period in which the timing signal Un indicates the H logic is selected. A selection signal SEGn indicating H logic is output to the scanning line 40 in the first half of the selection period.
[0039]
In the present embodiment, the data signal DAT output from the data driver 20 to the data line 42 corresponding to the scanning line 40 is synchronized with the timing signal U. The data signal DAT indicates data for causing the organic EL element 58 to emit light in the first half of the selection period indicated by the timing signal U, and indicates data for extinguishing the organic EL element 58 in the second half.
[0040]
Referring to FIG. 2, the selection transistor 52 is turned on and the drive transistor 56 is turned on during a period in which the selection signal SEGn indicates H logic, that is, a period during which the scanning line 40 to which the selection signal SEGn is supplied is selected. The organic EL element 58 emits light. Then, even after the selection transistor 52 is turned off, the organic EL element 58 emits light for a predetermined period due to the electric charge held in the storage capacitor 54. In the present embodiment, since the charge storage capacity of the storage capacitor 54 is sufficiently large, the organic EL element 58 emits light until an extinction instruction is received from the scanning driver 100 and the data driver 20.
[0041]
Next, returning to FIGS. 3 and 4, the operation of the scan driver 100 after the start pulse SP is supplied to the shift register 120 again will be described. When the start pulse SP is supplied to the shift register 120 again, the logic value of the timing signal Un changes from L logic to H logic according to the rising edge of the start pulse SP. Then, the light emission information in the latch circuit 142 is updated according to a change in the logical value of the timing signal Un. Specifically, the latch circuit 142 holds the H logic indicating light emission in response to the first rising edge of the timing signal Un, but holds the logic value held in accordance with the next rising edge of the rising edge. Is changed to L logic indicating extinction, thereby updating the emission information.
[0042]
When the light emission information is updated, the logic value supplied to the phase control circuit 162 changes from H logic to L logic, so that the light emission signal Tn is the logical product of the logical value and the selected clock signal INH. Therefore, the phase of the light emission signal Tn is opposite to the phase of the selected clock signal INH. Then, in the NAND circuit 180 and the inverter circuit 182, the logical product of the timing signal Un and the light emission signal Tn is taken, so that the latter half of the selection period indicated by the timing signal Un is selected. A selection signal SEGn indicating logic is output to the scanning line 40.
[0043]
In the present embodiment, the data signal output from the data driver 20 to the data line 42 corresponding to the scanning line 40 is synchronized with the timing signal, and the data signal for extinguishing the organic EL element 58 in the latter half of the selection period. 2, the driving transistor 56 is turned off and the organic EL element 58 is turned off. That is, the organic EL element 58 emits light during a period from the first rising edge of the selection signal SEGn to the next rising edge.
[0044]
By repeating the above operation at a desired timing, the light emission period of the organic EL element 58 can be controlled. Therefore, a gradation can be obtained by changing the light emission period of the organic EL element 58 in one frame displayed by the organic EL display device 10.
[0045]
FIG. 5 shows a timing chart of another example of the scanning driver 100. In the example described with reference to FIG. 4, the period in which the selected clock signal INH indicates the H logic is substantially the same as the period in which the selected clock signal INH indicates the L logic. It is different from the period indicating L logic. More specifically, the period indicating the H logic is longer than the period indicating the L logic, and the ratio is approximately 3: 1.
[0046]
Generally, when the pixel 32 emits light, that is, when data is written to the pixel 32, active and inactive data are supplied for emission. On the other hand, in the case of extinguishing the pixel 32, that is, in the case of erasing the data written in the pixel 32, it is sufficient to supply inactive data for light emission. Therefore, in general, when the pixel 32 emits light, it is preferable to secure a longer data writing time than when the pixel 32 is extinguished.
[0047]
According to the present example, the period during which the scanning line 40 is selected by the selection signal SEGn, that is, the period during which the selection signal SEGn indicates the H logic is set to different lengths when the pixel 32 emits light and when the pixel 32 emits light. Can be. Accordingly, when the pixel 32 emits light, a sufficient time for writing data from the data line 42 to the pixel 32 can be ensured, so that data can be supplied to the pixel 32 stably.
[0048]
FIG. 6 is a diagram illustrating another example of the circuit configuration of the scan driver 100. FIG. 7 shows a timing chart of the scanning driver 100 in this example. In this example, based on the timing signal Un output from the holding circuit 122 in the n-th stage, the light emission information held in the latch circuit 142 in the n-th stage is updated, and the timing signal output from the holding circuit 122 in the (n + 1) -th stage is updated. The selection signal SEGn is generated based on Un + 1. Specifically, in the NAND circuit 180 and the inverter circuit 182, the logical product of the light emission signal Tn output from the phase control circuit 162 in the nth stage and the timing signal Un output from the holding circuit 122 in the (n + 1) th stage is calculated. Thus, the selection signal SEGn is generated.
[0049]
According to this example, the emission information held in the holding circuit 122 can be updated in a predetermined selection period, and the scanning line 40 can be selected based on the emission information in another selection period. Therefore, since a sufficient time can be secured for updating the held information, a sufficient margin for selecting the scanning line 40 is secured. Therefore, the scanning driver 100 can be operated more stably.
[0050]
According to the present embodiment, there is no need to provide a reset line and a reset transistor in a pixel even when an organic EL display device is driven by time division driving. Therefore, an organic EL display device having a display portion with an extremely high aperture ratio can be provided. Further, according to the present embodiment, it is possible to switch between display and non-display of pixels by using a series of shift registers in the scanning driver. Therefore, even when driven by time-division driving, the area of peripheral circuits such as a scanning driver can be reduced, so that the organic EL display device can have a narrower frame and lower power consumption.
[0051]
FIG. 8 is a perspective view illustrating a configuration of a personal computer 1000 which is an example of an electronic apparatus including the electro-optical device of the invention. 6, a personal computer 1000 includes a display panel 1002 and a main body 1006 having a keyboard 1004. In the display panel 1002 of the personal computer 1000, the electro-optical device of the present invention is used.
[0052]
The examples and application examples described through the above embodiments of the present invention can be used in appropriate combination or with modifications or improvements depending on applications. The present invention is limited to the description of the above embodiments. Not something. It is apparent from the description of the appended claims that embodiments in which such combinations or changes or improvements are made can be included in the technical scope of the present invention.
[Brief description of the drawings]
FIG. 1 is a diagram showing an organic EL display device 10 which is an example of an electro-optical device according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating an example of a pixel 32.
FIG. 3 is a diagram showing an example of a circuit configuration of a scanning driver 100.
FIG. 4 shows a timing chart of the scanning driver 100.
FIG. 5 shows a timing chart of another example of the scanning driver 100.
FIG. 6 is a diagram showing another example of the circuit configuration of the scan driver 100.
FIG. 7 shows a timing chart of the scanning driver 100 in the present example.
FIG. 8 is a perspective view illustrating a configuration of a personal computer 1000 as an example of an electronic apparatus including the electro-optical device according to the invention.
[Explanation of symbols]
Reference Signs List 10 display device, 20 data driver, 22 shift register, 24 first latch circuit, 26 second latch circuit, 28 reset circuit, 30 display unit, 32 pixel, 40 scanning line, 42 data line, 46 power supply line, 52 selection transistor, 54 storage capacitor, 56 drive transistor, 58 organic EL element, 100 scan driver, 110 reference clock generator, 112 reference clock generation 114, start pulse generator, 120, shift register, 122, latch circuit, 122, holding circuit, 124, 126, 128, inverter circuit, 130, NAND circuit, 140, memory circuit, 142, latch circuit, 144, 146, 148: inverter circuit, 150: NAND circuit, 160: selection circuit, 162: phase control circuit, 1 4 Inverter circuit, 166, 168, 170 NAND circuit, 172 Selection clock signal generation section, 174 Inversion selection clock signal generation section, 176 Reset signal generation section, 180 NAND circuit, 182 Inverter circuit, 1000 Personal computer, 1002 display panel, 1004 keyboard, 1006 body, CLK reference clock signal, DAT data signal, INH selection clock signal, RST reset signal, SEG selection signal, SP start pulse, T ... Light emission signal, U ... Timing signal, ZCLK ... Inverted reference clock signal

Claims (11)

A drive circuit for driving a plurality of electro-optical elements,
Based on a reference clock, a shift register that sequentially determines a selection period that is a period for selecting whether to emit or extinguish the electro-optical element for the plurality of electro-optical elements,
A storage unit that stores light emission information indicating whether the electro-optical element should emit light or should be quenched,
A drive unit for selecting whether to emit or extinguish the electro-optical element in the selection period based on the emission information. The shift register generates a timing signal indicating the selection period by changing a logical value,
The drive circuit according to claim 1, wherein the storage unit updates the light emission information based on a change in the logical value. The shift register sequentially generates a first timing signal and a second timing signal based on the reference clock;
The storage unit updates first light emission information, which is the light emission information of the first electro-optical element, based on the first timing signal, and updates second light emission information based on the second timing signal. Updating second light emission information that is the light emission information of the electro-optical element,
3. The device according to claim 2, wherein the selection unit selects whether the first electro-optical element emits light or quenches based on the first light emission information and the second timing signal. 4. Drive circuit. The selection unit includes:
A light emission signal generation unit that generates a light emission signal whose phase changes based on the light emission information, synchronized with the timing signal,
The drive circuit according to claim 2, further comprising: a selection signal generation unit configured to generate a selection signal for selecting light emission or extinction of the electro-optical element based on the timing signal and the light emission signal. A selection clock signal synchronized with the reference clock, and a selection clock signal generation unit that generates an inverted selection clock signal obtained by inverting the selection clock signal;
5. The light emission signal generation unit according to claim 4, wherein the light emission signal generation unit generates the light emission signal by selecting and outputting one of the selected clock signal and the inverted selection clock signal based on the light emission information. 6. The driving circuit as described. The driving circuit according to claim 5, wherein the selection clock signal is a signal indicating H logic and L logic, and a period indicating the H logic is different from a period indicating the L logic. The drive circuit according to claim 1, wherein the electro-optical element is an organic electroluminescence element. An electro-optical device comprising the drive circuit according to claim 1. An electronic apparatus comprising the electro-optical device according to claim 8. A driving method for driving a plurality of electro-optical elements,
Based on a reference clock, a setting period that is a period for selecting whether to emit or extinguish the electro-optical element, a setting step of sequentially determining the plurality of electro-optical elements,
A storage step of storing light emission information indicating whether the electro-optical element should emit light or should be quenched,
A step of selecting whether to emit or extinguish the electro-optical element based on the emission information, in the selection period,
A driving method comprising: The setting step generates a timing signal indicating the selection period by changing a logical value,
The driving method according to claim 10, wherein the storing step updates the light emission information based on a change in the logical value.

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