JP5008302B2 - Display device - Google Patents

Description

  The present invention relates to a display device having a plurality of pixels arranged in a matrix and an electronic apparatus using the display device. More specifically, the present invention relates to a display device that displays an image by inputting a video signal to a selected pixel and controls each pixel, and an electronic apparatus using the display device.

  Demand for dot matrix display devices such as liquid crystal display devices is rapidly increasing not only for stationary applications such as television receivers and displays for personal computers, but also for portable applications. In recent years, an EL display device having a pixel including an organic electroluminescence (EL) element has been put into practical use as a next-generation display device replacing a liquid crystal display device.

  In general, the dot matrix type display device includes a passive matrix type and an active matrix type. There are an analog gradation method and a digital gradation method as methods for expressing gradation in an active matrix display device. In the analog gradation method, gradation is expressed by controlling the luminance of a pixel. In the digital gradation method, each pixel is controlled by two values of light emission or no light emission. The gradation is expressed by the size of the light emission area or the length of the light emission time in a certain period. The former is called the area gradation method, and the latter is called the time gradation method.

  In the above-described time gray scale method, one frame period is divided into a plurality of subframe periods, and the light emission time is weighted in each subframe period. Then, the luminance per frame period is controlled by the combination of subframe periods to express gradation. As one of methods for realizing multi-gradation by such a method, a method disclosed in Patent Document 1 is disclosed.

In Patent Document 1, for example, in the case of 6-bit (64 gradations) display, one frame period is divided into six subframe periods (SF1 to SF6), and the length of the light emission period in each subframe period is 2 ⁵ : 2. ⁴ : 2 ³ : 2 ² : 2 ¹ : 1 and each gradation is expressed by selecting which sub-frame period to emit light (see FIG. 5A). Specifically, if no light is emitted during any period, the first gradation (black: luminance 0) is represented, and if light is emitted during all periods, the 64th gradation (white: luminance 63) is represented. If the light emission period of 2 ⁴ , 2 ³ , 2 ² , 1 is selected, the 30th gradation is represented. 2 ⁴ +2 ³ +2 ² + 1 = 29, that is, the 30th gradation (luminance 29) among 64 gradations from luminance 0 to luminance 63 is expressed.

Further, in a subframe period with a short bit, that is, a short light emission time, it is necessary to control to stop light emission before the start of the next subframe period. Therefore, the selection period of one row is divided into a plurality of sub-horizontal periods (see FIG. 5B, in FIG. 5B, it is divided into two sub-horizontal periods before and after). Signal writing is performed, and erasing is performed in a certain sub-horizontal period. By performing the writing and erasing at the necessary timing in each necessary row, the light emission period is controlled by each bit. The writing and erasing are performed by corresponding gate drivers (also referred to as gate signal line driving circuits).
JP 2001-324958 A

  In the case of driving a display device using the digital time gray scale method described in Patent Document 1, the driving of the active matrix pixel may be binary display of white display or black display. Therefore, a significant advantage is that variation in characteristics of thin film transistors (hereinafter referred to as TFTs) constituting a pixel hardly affects display quality.

  On the other hand, the number of video signal writings within one frame period is large, and writing and erasing operations for controlling the light emission time are necessary. The operating frequency of the peripheral drive circuit becomes high and the power consumption increases. . In addition, since the writing operation and the erasing operation are performed by the gate drivers corresponding to each, there are two gate drivers. As the number of gray levels increases, the gate driver is required to have a high operating frequency, so that the area of the gate driver usually increases. This is higher for a display device having one gate driver. Further, as the display device becomes high definition, the horizontal period is usually shortened and the load on the gate line is usually increased. Therefore, there is a limit to high definition in the method of inputting a signal from one side of the gate signal line. is there.

  In view of the above-described problems, an object of the present invention is to provide a display device and an electronic device that can reduce power consumption when driven using a digital time gray scale method. It is another object of the present invention to provide a high-definition display device and electronic device. Another object of the present invention is to provide a display device and an electronic device having a narrow frame (slim bezel).

  The present invention is characterized in that both a write operation and an erase operation are performed by a single gate signal line driver circuit. In addition, the present invention is characterized in that high-definition display is performed by using two gate signal line driver circuits. Here, writing refers to inputting an image signal to a selected row, and erasing refers to inputting a non-display signal (for example, a state in which all pixels display black) to the selected row. It shall be said.

  The main structure of the gate signal line driver circuit of the present invention is a shift register for selecting a row and a control circuit for switching between writing and erasing of a video signal. The control circuit is, for example, an RS latch (a latch having a reset / set function). Further, the switching method by the control circuit uses an output signal of the shift register of the row, an output signal of the control circuit of the previous row, and an external signal.

  That is, a pixel portion having a plurality of pixels provided in a region surrounded by gate signal lines constituting a plurality of rows and source signal lines constituting a plurality of columns, and adjacent gate signal lines and adjacent source signal lines A gate signal line driving circuit electrically connected to the source signal line (also referred to as a source driver) and a gate signal line driving circuit electrically connected to the gate signal line. Is a display device having a shift register for selecting a row and a control circuit for performing switching operation of writing or erasing a video signal to a pixel.

  In the switching operation, an output signal of the control circuit corresponding to a row selected by the shift register, a row before the row, and a signal input to the control circuit from the outside are used.

  According to the present invention, the gate signal line driver circuits are arranged on both sides of the pixel portion, for example, on the left and right sides, and the same signal is supplied to the row from both sides of the row.

  The gate signal line driver circuit of the present invention can be formed over the same substrate as the substrate over which the pixel portion is formed. Similarly, the source signal line driver circuit can be formed over the same substrate as the pixel portion.

  In the present invention having the above characteristics, power consumption can be reduced by performing a writing operation and an erasing operation with one gate signal line driver circuit.

  Further, according to the present invention having the above characteristics, a single gate signal line driver circuit can be provided, so that the display device can be easily narrowed.

  In addition, according to the present invention having the above characteristics, the gate signal line driving circuits are arranged on both sides of the pixel portion, and the same signal is supplied from both sides of the row to the row, so that the horizontal period is short and the load on the gate line is reduced. It can correspond to a large high-definition display device.

(Embodiment 1)
Embodiments of the present invention will be described in detail below. An example in which an RS latch is used as a control circuit is shown. It should be noted that the present invention is not limited to the following description, and it is easy for those skilled in the art to variously change the form and scope of the present invention without departing from the spirit and scope of the present invention. To be understood. Therefore, the present invention should not be construed as being limited to the description of the embodiments below.

  A structure of an active matrix display device of the present invention will be described with reference to FIG. The pixel portion 101 has a plurality of pixels 102 surrounded by a dotted frame, and these are arranged in a matrix. A source driver 103 and a gate driver 104 are arranged around the pixel portion 101.

  The source driver 103 includes a shift register 105, a first latch circuit 106, a second latch circuit 107, and a level shifter buffer 108. The gate driver 104 includes a shift register 109, an RS latch 110, and a level shifter buffer 111.

  Next, details of the pixel 102 will be described with reference to FIG. Each pixel includes a source signal line 121 connected to the source driver 103, a gate signal line 122 connected to the gate driver 104, a current supply line 123, a counter electrode 124, a switching TFT 125 connected to the source signal line 121 and the gate signal line 122. And a driving TFT 126 connected to the current supply line 123, a driving TFT 126, and a light emitting element 127 connected to the counter electrode 124.

  The driving of the pixel differs depending on the polarity of the TFT constituting the pixel, the direction of the current flowing through the light emitting element, and the like. In this embodiment mode, as an example, the switching TFT 125 is configured by an N-type TFT and the driving TFT 126 is configured by a P-type TFT, and the light emitting element 127 is maintained at a low potential from the current supply line 123 maintained at a high potential. A configuration in which a current flows toward the counter electrode 124 that has sagged will be described. As for the logic of the subsequent circuit operation, the case where the pixel described here is driven is taken as an example. However, of course, the present invention can be similarly applied to the case of driving a pixel having a configuration other than that shown here by reviewing the relationship between the logic of the signal and the power supply. It is not limited.

  In a row where no pixel is selected, the gate signal line 122 is at a low level, and the switching TFT 125 is OFF. On the other hand, in the row in which the pixel is selected, the gate signal line 122 becomes High level, the switching TFT 125 is turned on, and the potential of the source signal line 121 is written to the gate electrode of the driving TFT 126.

  Here, when the potential of the source signal line 121 is at a high level, the driving TFT 126 is turned off, and no current flows to the light emitting element 127, so that the pixel expresses black. On the other hand, when the potential of the source signal line 121 is at a low level, the driving TFT 126 is turned on, a current flows through the light emitting element 127 and light is emitted, and the pixel expresses white. Note that although not particularly specified in FIG. 1B, it is preferable that a video signal written to the gate electrode of the driving TFT 126 can be held for a certain period using a holding capacitor or the like. Thereby, even after the gate signal line 122 is not selected, the driving TFT 126 can be kept on or off, and the black or white display state can be kept.

  Next, the operation of the display device of the present invention will be described. More specifically, the operation of the display device of the present invention in which both the write operation and the erase operation are performed by one gate driver will be described.

  In the source driver 103, the shift register 105 sequentially outputs sampling pulses from the first stage according to the clock signal (SCK) and the start pulse (SSP). In accordance with the sampling pulse output from the shift register 105, the first latch circuit 106 samples the video signal (Data). In the stage where the sampling of the video signal in the first latch circuit 106 is completed, the video signal captured in the memory portion provided in the first latch circuit 106 is held until the sampling in the final stage is completed. Is done. After a while, the output of the sampling pulse from the final stage of the shift register 105 is finished, and after the sampling is completed in all the stages of the first latch circuit 106, it is held in the first latch circuit 106 according to the latch pulse (SLAT). The one row of data thus transferred is transferred to the second latch circuit 107 all at once.

  Thereafter, amplitude conversion is performed in the level shifter buffer 108 as necessary, and the source signal line is charged / discharged in accordance with the video signal. Further, a mode for charging / discharging the source signal line in accordance with the video signal and a mode for outputting an erasing signal to all the source signal lines are selected by a write / erase selection signal (hereinafter referred to as W / E signal).

  On the other hand, in the gate driver 104, the shift register 109 sequentially outputs row selection pulses from the first stage according to the clock signal (GCK), the start pulse 1 (G1SP), or the start pulse 2 (G2SP). The gate driver 104 also has a pulse width control signal 1 (GPWC1) that is a half cycle of the clock signal (GCK) and a pulse width control signal 2 (GPWC2) that is an inverted signal of the pulse width control signal 1 (GPWC1). Is entered.

  Next, the case where the start pulse 1 (G1SP) is input and the case where the start pulse 2 (G2SP) is input will be described.

  In the first stage of the RS latch 110, when the start pulse 1 (G1SP) is input to the shift register 109, the output of the RS latch does not change and holds the initial state. Since the RS latch holds the initial state, the RS latch selects the pulse width control signal 1 (GPWC1), and the pulse width control signal 1 (GPWC1) and the row selection pulse of the shift register 109 of the row. Is input to the level shifter buffer 111 of the row, the level shifter buffer 111 of the row outputs a write signal to the gate signal line.

  After the second stage of the RS latch 110, the output state (initial state) of the RS latch several stages before the RS latch is received, and the logical product of the pulse width control signal 1 (GPWC1) and the row selection pulse of the shift register 109 is obtained. By inputting the signal obtained from the above to the level shifter buffer 111 of the row, the level shifter buffer 111 of the row outputs a write signal to the gate signal line.

  An example of this series of operations is simply shown in FIG. In FIG. 6A, GSR1, GSR2, and GSR3 are outputs of the shift register 109, and GLine1, GLine2, and GLine3 are gate signal lines, and signals input to them are described.

  In the first stage of the RS latch 110, when the start pulse 2 (G2SP) is input to the shift register 109, the output state of the first stage of the RS latch 110 is inverted (set) from the initial state. The RS latch selects the pulse width control signal 2 (GPWC2), and outputs a signal obtained by ANDing the pulse width control signal 2 (GPWC2) and the row selection pulse of the shift register 109 of the row. The data is input to the buffer 111 and an erase signal is output to the gate signal line.

  Further, after the second stage of the RS latch 110, an output inverted (set) with respect to the initial state of the RS latch several stages before the RS latch is received, and the pulse width control signal 2 (GPWC2) and the shift register 109 are received. A signal obtained by ANDing the row selection pulses is input to the level shifter buffer 111 of the row, and an erase signal is output to the gate signal line. Further, the output of the RS latch from the RS latch onward is input to each RS latch, and when the input is inverted (set) with respect to the initial state, the output of the RS latch is reset, and the RS latch The output returns to the initial state.

  This series of operations is simply shown in FIG. In FIG. 6B, GSR1, GSR2, and GSR3 are outputs of the shift register 109, and GLine1, GLine2, and GLine3 are gate signal lines, and signals input to them are described.

  From the above, the gate driver 104 according to the present invention, after inputting the start pulse 1 (G1SP), delays the start pulse 2 after delaying by an integer (2 or more) times the period of the clock signal (GCK). By inputting (G2SP), writing and erasing can be performed within one horizontal period. In other words, the gate driver 104 according to the present invention combines the functions of the write gate driver and the erase gate driver into one gate driver.

  If one gate driver 104 according to the present invention is arranged on one side of the pixel portion 101, that is, only on one side, the area of the frame can be reduced as compared with the method in which the gate driver for writing and the gate driver for erasing are arranged separately on both sides. Can do.

  If one gate driver 104 according to the present invention is arranged on one side of the pixel portion 101, that is, only on one side, the number of shift registers 109 is such that the write gate driver and the erase gate driver are divided on both sides of the pixel region. Since it is half of the arrangement method, power consumption can be reduced.

(Embodiment 2)
As shown in FIG. 2, a gate driver 104 having a shift register 109, an RS latch 110, and a level shifter buffer 111 is arranged on both sides so as to sandwich the pixel portion 101, and the same signal is sent from both sides to the same gate signal line. In addition, by outputting simultaneously, it becomes faster to transmit a signal to the gate signal line. Accordingly, it is possible to cope with a high-definition display device having a short horizontal period and a large load on the gate line.

  In FIG. 2, the same components as those in FIG. The gate driver of this embodiment has the same structure as the gate driver described in FIG. This embodiment is different from the first embodiment in which one gate driver 104 is arranged on both sides of the pixel portion 101, and one gate driver 104 is arranged only on one side.

(Embodiment 3)
In this embodiment mode, structural examples of a driver circuit of a display device of the present invention, that is, a source driver and a gate driver will be described.

  First, a configuration example of the source driver will be described with reference to FIG. The source driver includes a shift register 301, a first latch circuit 302, a second latch circuit 303, a write / erase selection circuit 304, and a buffer circuit 305.

  The shift register 301 sequentially outputs sampling pulses in accordance with a clock signal (SCK, SCKb: SCKb is an inverted signal of SCK) and a start pulse (SSP). The first latch circuit 302 samples the video signal (Data) in accordance with the sampling pulse output from the shift register 301. After the sampling of the video signal is completed in all stages of the first latch circuit 302, when a latch pulse (SLAT, SLATb: SLATb is an inverted signal) is input, the video signal held in the first latch circuit 302 Are simultaneously transferred to the second latch circuit 303. The write / erase selection circuit 304 inverts and outputs the video signal when the W / E signal is active (here, when it is at a high level). On the other hand, when the W / E signal is at the low level, the high level is output regardless of the video signal. Thereafter, the source signal lines (SLine 1 to SLine n) are charged and discharged through the buffer circuit 305 (n is an integer of 2 or more).

  Next, the configuration of the gate driver will be described with reference to FIG. The gate driver includes a shift register 401, a selector circuit 402, an RS latch circuit 403, an inverter circuit 406, an inverter circuit 407, an AND circuit 404, and a buffer circuit 405. The input of the inverter circuit 406 is connected to the output of the AND circuit 404 two stages before, and the input of the inverter circuit 407 is connected to the output of the AND circuit 404 two stages after. The input of the inverter circuit 406 is a set input of the RS latch circuit 403, and the input of the inverter circuit 407 is a reset input of the RS latch circuit 403. The start pulse 2 (G2SP) is connected to the input of the first-stage and second-stage inverter circuits 406. First, when the start pulse 1 (G1SP) is input, the gate lines (GLine1, GLine2, GLine3, GLine4) are ANDed with the pulse width control signal 1 (GPWC1) and the row selection pulse of the shift register 401. Signal is output. When the start pulse 2 (G2SP) is input, the gate line (GLine1, GLine2, GLine3, GLine4) is ANDed with the pulse width control signal 2 (GPWC2) and the row selection pulse of the shift register 401. Signal is output.

  The selector circuit 402, the RS latch circuit 403, the inverter circuit 406, the inverter circuit 407, and the AND circuit 404 can be collectively expressed as a control circuit.

  Note that the gate driver and source driver configurations of this embodiment are not provided with a level shifter, but may be provided as needed.

  FIG. 7 illustrates an example of a mobile phone on which a display device using the gate driver and the source driver described in this specification, for example, an electroluminescence (EL) display device is mounted.

  The structure of the pixel of the electroluminescence (EL) display device is not limited to the structure illustrated in FIG. For example, a so-called multi-gate structure in which a plurality of TFTs are connected in series to one or both of the switching TFT and the driving TFT can be employed. Further, the present invention is not limited to a configuration using two types of TFTs, a switching TFT and a driving TFT. Further, the sectional structure of each TFT is not limited to a specific one, and the polarity (N channel type, P channel type) of each TFT is not limited.

  Moreover, a well-known material and formation method can be used for each layer, an insulating film, an electrode, and wiring which comprise a light emitting element.

  The display device 701 is detachably incorporated in the housing 702. The shape and dimensions of the housing 702 can be changed as appropriate in accordance with the size of the display device 701. A housing 702 to which the display device 701 is fixed is fitted into a printed wiring board 703 and assembled as a module.

  The display device 701 is connected to the printed wiring board 703 through the FPC 708. A signal processing circuit including a speaker, a microphone, a transmission / reception circuit, a CPU, a controller, and the like is formed on the printed wiring board 703. Such a module is combined with the input means 704 and the battery 705 and stored in the casings 700 and 706. The pixel portion of the display device 701 is arranged so as to be visible from an opening window formed in the housing 700.

  Since the power consumption can be reduced by mounting the display device of the present invention on a cellular phone, the life of the battery 705 can be extended. Further, the opening window can be designed to be large by narrowing the frame.

  The mobile phone according to the present embodiment can be transformed into various modes according to the function and application. For example, the above-described effects can be obtained even when a plurality of display devices are provided or a case is divided into a plurality of cases and opened and closed by a hinge.

  FIG. 8A illustrates a display device in which a display panel 801 and a circuit board 802 are combined, which are mounted on a television receiver. The display device is, for example, an electroluminescence (EL) display device, and the source driver and the gate driver described in this specification are used.

  The structure of the pixel of the electroluminescence (EL) display device is not limited to the structure illustrated in FIG. For example, a so-called multi-gate structure in which a plurality of TFTs are connected in series to one or both of the switching TFT and the driving TFT can be employed. Further, the present invention is not limited to a configuration using two types of TFTs, a switching TFT and a driving TFT. Further, the sectional structure of each TFT is not limited to a specific one, and the polarity (N channel type, P channel type) of each TFT is not limited.

  Moreover, a well-known material and formation method can be used for each layer, an insulating film, an electrode, and wiring which comprise a light emitting element.

  For example, a control circuit 803, a signal dividing circuit 804, and the like are formed on the circuit board 802. FIG. 8A illustrates an example in which the source driver 805 and the gate driver 806 are formed over the same substrate as the pixel portion 807, but only the gate driver 806 is formed over the same substrate as the pixel portion 807. May be. Further, as shown in Embodiment Mode 1, a structure in which one gate driver 806 is provided only on one side of the pixel portion can be employed.

  The television set illustrated in FIG. 8B can be completed by incorporating the display device illustrated in FIG. 8A into the housing 811. Reference numeral 812 denotes a display screen, which is appropriately provided with a speaker 813, an operation switch 814, and the like.

  By applying the present invention to a display device incorporated in a television receiver, the power consumption of the television receiver can be reduced and the display screen 812 can be enlarged by narrowing the frame.

  9A and 9B illustrate an example of a digital camera in which a display device using the gate driver and the source driver described in this specification, for example, an electroluminescence (EL) display device is mounted. .

  The structure of the pixel of the electroluminescence (EL) display device is not limited to the structure illustrated in FIG. For example, a so-called multi-gate structure in which a plurality of TFTs are connected in series to one or both of the switching TFT and the driving TFT can be employed. Further, the present invention is not limited to a configuration using two types of TFTs, a switching TFT and a driving TFT. Further, the sectional structure of each TFT is not limited to a specific one, and the polarity (N channel type, P channel type) of each TFT is not limited.

  Moreover, a well-known material and formation method can be used for each layer, an insulating film, an electrode, and wiring which comprise a light emitting element.

  FIG. 9A is a front view of the digital camera, in which 901 indicates a release button, 902 indicates a main switch, 903 indicates a finder window, 904 indicates a strobe, 905 indicates a lens, and 906 indicates a casing.

  FIG. 9B is a view of the digital camera shown in FIG. 9A viewed from the rear. 907 is a viewfinder eyepiece window, 908 is a monitor, and 909 and 910 are operation buttons.

  By applying the display device of the present invention to the monitor 908 of the digital camera, power consumption can be reduced and the monitor 908 can be enlarged by narrowing the frame.

  The present invention can be applied not only to the mobile phone shown in the first embodiment, the television receiver shown in the second embodiment, and the digital camera shown in the third embodiment, but also to any electronic device equipped with a display device.

FIG. 6 illustrates a display device of the present invention. FIG. 6 illustrates a display device of the present invention. FIG. 14 illustrates an example of a source driver used in a display device of the present invention. FIG. 14 illustrates an example of a gate driver used for a display device of the present invention. The figure explaining a digital time gradation system. 4 is a timing chart for explaining the operation of the display device of the present invention. The figure which shows the example of the cellular phone Diagram showing an example of a television receiver Diagram showing an example of a digital camera

Explanation of symbols

101 Pixel portion 102 Pixel 103 Source driver 104 Gate driver 105 Shift register 106 First latch circuit 107 Second latch circuit 108 Level shifter buffer 109 Shift register 110 RS latch 111 Level shifter buffer 121 Source signal line 122 Gate signal line 123 Current Supply line 124 Counter electrode 125 TFT for switching
126 Driving TFT
127 Light emitting element 301 Shift register 302 First latch circuit 303 Second latch circuit 304 Write / erase selection circuit 305 Buffer circuit 401 Shift register 402 Selector circuit 403 RS latch circuit 404 AND circuit 405 Buffer circuit 406 Inverter circuit 407 Inverter circuit

Claims (1)

A pixel, a gate signal line driver circuit, and a source signal line driver circuit;
The pixel includes a first transistor, a second transistor, and a light emitting element,
A gate of the first transistor is electrically connected to the gate signal line driver circuit via a gate signal line;
One of the source and the drain of the first transistor is electrically connected to the source signal line driver circuit through a source signal line,
The other of the source and the drain of the first transistor is electrically connected to the gate of the second transistor;
One of a source and a drain of the second transistor is electrically connected to the light emitting element,
The other of the source and the drain of the second transistor is electrically connected to a current supply line;
The gate signal line driving circuit includes a shift register, an RS latch, and a level shifter.
When writing a video signal from the source signal line driver circuit to the pixel,
The shift register has a function of outputting a row selection pulse by inputting a clock signal and a first start pulse,
The RS latch has a function of holding an output of an initial state when the first start pulse is input to the shift register, a first pulse width control signal and the function of holding the output of the initial state. A function of outputting a logical product with a row selection pulse to the level shifter ,
The level shifter has a function of controlling the switching of the first transistor by outputting a first signal to the gate signal line,
When inputting an erasing signal from the source signal line driver circuit to the pixel,
The shift register has a function of outputting a row selection pulse by inputting a clock signal and a second start pulse,
The RS latch has a function of inverting an output with respect to the initial state when the second start pulse is input to the shift register and the RS latch, and the first pulse by inverting the output. A function of inputting a logical product of a second pulse width selection signal, which is an inverted signal of the width control signal, and a row selection pulse to the level shifter;
The level shifter has a function of controlling the switching of the first transistor by outputting a second signal to the gate signal line,
The first pulse width control signal and the second pulse width control signal are set to have a half period of the clock signal,
The second start pulse is input after being delayed by an integer (two or more) times the period of the clock signal after the input of the first start pulse,
The set input terminals of the first and second stage RS latches are electrically connected to the wiring for supplying the second start pulse,
The set input terminal of the RS latch after the third stage is electrically connected to the output terminal of the RS latch before the second stage,
The display device, wherein a reset input terminal of the RS latch is electrically connected to an output terminal of the RS latch after two stages.