JPH08274584A - Active inductor - Google Patents

Abstract

PURPOSE: To provide an active inductor with high inductorance value even in a high-frequency range higher than a microwave range and having a low loss by compensating resistance loss generated by drain conductance, etc., being enabled to be miniaturized. CONSTITUTION: Feedback in one direction is applied to a source-grounded FET 31 by connecting gate-grounded/cascade-connected FETs 39, 43 to the FET 31. One terminal of a resistance element 50 is connected to the connection line of the drain electrode 40 of the FET 39 and the source electrode 45 of the FET 43, and two terminals are formed by leader terminals from the other terminal of the resistance element 50 and the source electrode 33 of the FET 31, respectively. Thereby, fixed negative resistance is generated for a frequency in series with inductance, and impedance observed from the two terminals goes to only an inductance component by adjusting the resistance value of the resistance element 50, which generates the active inductor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a small-sized, wideband and low-loss active inductor using a transistor.

[0002]

2. Description of the Related Art In a conventional MMIC (microwave monolithic integrated circuit), a spiral inductor in which a metal conductor is spirally formed on a dielectric substrate is often used for the purpose of reducing the chip size. Although this spiral inductor has a simple structure, there is a problem in that in order to obtain a required inductance, the shape of the spiral inductor becomes large and a substantial occupied area is expanded. On the other hand, by using an FET (field effect transistor) or the like, which is an active element, it can be made smaller than a spiral inductor, and therefore, an active inductor suitable for miniaturization of the MMIC has been considered.

[0003]

By the way, the conventional active inductor using the FET is suitable for miniaturization of the MMIC because the FET circuit itself can be made smaller than the spiral inductor. However, in the conventional active inductor, due to the resistance loss generated due to the drain conductance, etc.,
In particular, 1 / of the cutoff frequency f _T at which the performance of the FET begins to deteriorate
There is a drawback in that good operation at frequencies of 2 or more cannot be realized. Therefore, this point will be described in detail below.

[First Conventional Example] FIG. 46 shows the configuration of a first conventional example in which the size and the frequency are increased (Japanese Patent Publication 5-2).
4685). In this active inductor 700, a source-grounded FET 31 and a gate-grounded FET 35 are cascode-connected, and a resistor 16 having a resistance value R is connected between a gate 34 of the FET 31 and a drain 36 of the FET 35.
A resistor 50 having a resistance value R ₀ is connected between the terminals 17 and 18. Here, the resistor 50 functions to suppress "increase in inductance value in high-frequency characteristics" which is a problem when the resistor does not exist and to approach a constant inductance value in a wide frequency range. In FIG. 46, each P is a point to which a voltage is applied via a coil that cuts off a high frequency, and each C is a capacitor for blocking a DC voltage. The same applies to the following drawings.

Since the impedance Z ₀ when looking at the FET 35 side from the terminals 17 and 18 respectively connected to the drain 36 and the gate 38 of the FET ₃₅ is inductive, the FET circuit of FIG. 46 can be used as an active inductor. . Therefore, assuming that the resistor 50 does not exist in the active inductor 700 of FIG.
From this, the impedance Z ₀ seen from the FET circuit side is obtained.
In order to simplify the circuit analysis, FET31, FET35
Have the same electrical characteristics, and each is expressed only by the depletion layer capacitances Cgs1 and Cgs2 between the gate and the source immediately below the gate and the mutual conductances gm1 and gm2.
The impedance Z ₀ is given by the following equation.

[Equation 1]

Here, the cutoff frequency of the FET f _T = gm1 /
(2πCgs1) = gm2 / (2πCgs2). Within the same wafer, F having the same characteristics of f _T
It is possible to easily configure the ET. FIG. 47 shows a circuit diagram of an equivalent circuit under the above conditions. As shown in the figure, for a series circuit of a resistance 61 having a resistance value (1 / gm1) and an inductance 62 having an inductance value (Cgs1 R / gm1), a capacitor 63 having a capacitance (f / f _T ) ² Cgs1 is used. Corresponds approximately to the circuit connected in parallel.

Now, an FE having a short gate length for the microwave band
When T is used in a frequency band of approximately f _T / 3 or less, (f
/ F _T ) ² = 1/9 << 1. As a result, the imaginary term of the denominator in the equation (1) can be ignored, and the circuit of FIG. 46 operates as an active inductor equivalent to the series circuit of the resistor 61 and the inductance 62. Gate width 100μ
m FET (transconductance gm = 20 ms, depletion layer capacitance Cgs = 0.16 pF, cutoff frequency f _T = gm /
FIG. 48 shows the frequency characteristics of the impedance Z ₀ (= R + jωL, the same applies below) in the equation (1) when (2πCgs) = 20 GHz) is used. Here, it is assumed that the FETs to be used have the same gate width. The resistance value R of the resistor 16 is 50Ω.

As can be seen from FIG. 48, this active inductor has a resistance component in series with the inductance,
Since the transconductance gm is not so large in the microwave band, the loss becomes large and it is difficult to operate the active inductor satisfactorily at a high frequency above the microwave band.

[Second Conventional Example] FIG. 49 shows the configuration of a second conventional example in which the size and the frequency are increased (Japanese Patent Laid-Open No. 2-2).
No. 05107). The active inductor 800 cascode-connects the source-grounded FET 31 and the gate-grounded FET 35, and also connects the drain 36 of the FET 35.
From the gate 34 of the FET 31 to the gate ground F
It is characterized by a one-way return by ET39.

The impedance Z ₀ when the FET 35 is viewed from the terminals 17 and 18 connected to the drain 36 and the gate 38 of the FET ₃₅ is inductive, so that FIG.
Can be used as an active interactor. In the microwave band having a relatively low frequency, the impedance Z ₀ is almost given only by the inductance component and is lossless.
The high frequency characteristics are improved as compared with the active inductor 700 of No. 6 described above.

Next, assuming that the resistor 50 does not exist in the active inductor 800, the terminals 17 and 18 are connected to F.
The impedance Z ₀ viewed from the ET circuit side is obtained. To simplify the circuit analysis, FET31, FET35, FE
T39 has electrically the same characteristics, and each has a depletion layer capacitance Cgs1, Cgs2, Cgs between the gate and the source immediately below the gate.
If it is expressed only by f and transconductance gm1, gm2, gmf, impedance Z ₀ is given by the following equation.

[Equation 2]

Here, the cutoff frequency of the FET f _T = gm1 /
(2πCgs1) = gm2 / (2πCgs2) = gmf / (2π
Cgsf). A circuit diagram of an equivalent circuit under the above conditions is shown in FIG. As shown in the figure, the resistance value [1 /
It is almost the same as the parallel circuit of the resistance 61 of {(f / f _T ) ² gmf}] and the inductance 62 of the inductance value {Cgs1 / (gm1 gmf)}.

Now, an FE having a short gate length for the microwave band
When T is used in a frequency band of approximately f _T / 3 or less, (f
/ F _T ) ² = 1/9 << 1, and the real number term of the denominator in the equation (2) can be ignored, so that the impedance Z ₀ is given only by the inductance component and operates as a lossless active inductor. FET having a gate width of 100 μm (transconductance gm = 20 ms, depletion layer capacitance Cgs = 0.
16 pF, cutoff frequency f _T = gm / (2πCgs) = 20
GHz) impedance Z _{0 of the} equation (2)
The frequency characteristics of are shown in FIG. 51 (a) and FIG. 51 (b).
In this figure, the frequency characteristic of the inductance component (L) of the impedance (the same figure (a)) and the frequency characteristic of the resistance component (R) (the same figure (b)) are shown. Here, it is assumed that the FETs to be used have the same gate width. Further, in this figure, three cases of drain conductance Gd = 0, 1, 2 mS are shown.

As can be seen from this figure, as the drain conductance increases, steady resistance loss occurs even in a relatively low frequency band of about several GHz. Furthermore, in the vicinity of 10 GHz (f = f _T / 2), the real term (f / f _T ) ² gmf / {1+ of the denominator of the equation (2) is no longer present.
The effect of (f / f _T ) ² } cannot be ignored and the loss is increasing. Therefore, it can be said that it is difficult to operate this active inductor without loss at a high frequency above the microwave band.

[Third Conventional Example] As a third conventional example, FIG. 52 shows a configuration of a cascode-connected / gate-grounded cascode-connected feedback-type active inductor.
No. 05107). In this active inductor 900, instead of the feedback circuit using the FET 39 shown in FIG. 49, a feedback circuit including a FET 39 and a FET 43 connected in cascode with the gate grounded is connected.

Next, the impedance Z of the circuit seen from the terminals 17 and 18 when the resistor 50 is not connected.
_Ask for ₀ . In order to simplify the circuit analysis, FET31,
The FET 35, the FET 39, and the FET 43 have the same electrical characteristics, and the depletion layer capacitances Cgs1, Cgs2, Cgsf, Cgsa between the gate and the source immediately below the gate and the mutual conductor gm1,
If expressed only by gm2, gmf, and gma, the impedance Z ₀ is

(Equation 3) Given in. Here, the cutoff frequency f _T of the FET is f _T =
gm1 / (2πCgs1) = gm2 / (2πCgs2) = gmf
/ (2πCgsf) = gma / (2πCgsa).

As shown in FIG. 53, the equivalent circuit of this active inductor 900 has a resistance 50 having a resistance value R ₀ , a negative resistance 61 having a resistance value (−1 / gmf), and an inductance value Cg.
It is almost the same as the parallel circuit of the inductance 62 of s1 / (gm1 gmf). Here, when the resistance value R ₀ = 1 / gmf, the negative resistance component is canceled and only the inductance component is produced, and the device operates as a lossless active inductor.

FET having a gate width of 100 μm (transconductance gm = 20 mS, depletion layer capacitance Cgs = 0.16 p)
F, drain conductance Gd = 0,1,2,4m
S, cutoff frequency f _T = gm / (2πCgs) = 20 GH
54 (a) and 54 (b) show frequency characteristics of L and R with respect to the impedance Z ₀ when z) is used. Here, it is assumed that the FETs to be used have the same gate width. Further, here, the case where the resistance value R ₀ = 200Ω is shown. Since the active inductor 900 generates a negative resistance in parallel with the inductance, the loss can be reduced by adjusting the resistance value R ₀ , but the frequency range in which the loss is compensated is narrow. As.

[Fourth Conventional Example] As a fourth conventional example, FIG. 55 shows a configuration of an active inductor of a gate resistance insertion type (P. Alinikula et al., "Monolithic active resonators").
for wireless applications. "IEEE Microwave and Mi
llimeter-Wave Monolithic Circuits Symposium Dig.,
pp.197-200,1994. or P.Alinikula et al., "Integra
ting Active Resonators for Wireless applications, "
Microwave journal, pp.106-113, Jan, 1995.). This active inductor 1000 is a FET whose gate is grounded from the drain 32 of the source-grounded FET 31 to the gate 34.
39 is used for feedback, and a resistor 50 having a resistance value R ₀ is inserted between the gate 42 of the FET 39 and the DC voltage blocking capacitor C.

Next, the terminal 1 of the active inductor 1000.
The impedance Z ₀ viewed from 7, 18 is obtained. In order to simplify the circuit analysis, the FET 31 and the FET 39 have the same electrical characteristics, and the depletion layer capacitances Cgs1 and Cgsf between the gate and the source immediately below the gate and the transconductance gm1.
If expressed only by gmf, the impedance Z ₀ is

[Equation 4] Given in. Here, the cutoff frequency f _T of the FET is f _T
= Gm1 / (2πCgs1) = gmf / (2πCgsf). In the same wafer, it is possible to easily form an FET having such characteristics that cutoff frequencies f _T are equal.

As shown in FIG. 56, the equivalent circuit of this active inductor 1000 has a resistance value − (f / f _T ) ² {R ₀ −
1 / gmf} resistance 61 and inductance value Cgs1 /
It is almost the same as the series circuit of the inductance 62 of (gm1gmf). FET with a gate width of 100 μm (transconductance gm = 20 mS, depletion layer capacitance Cgs = 0.16 p
F, drain conductance Gd = 0,1,2 mS, cutoff frequency f _T = gm / (2πCgs) = 20 GHz), the frequency characteristics of L and R with respect to the impedance Z ₀ are shown in FIG. b). Here, it is assumed that the FETs to be used have the same gate width. Further, here, the case where the resistance value R ₀ = 100Ω is shown. Since the active inductor 1000 generates a negative resistance that depends on the frequency, it is possible to reduce the loss by adjusting the resistance value R ₀ , but a problem is that the loss compensated frequency range is narrow. To be

[Fifth Conventional Example] As a fifth conventional example, FIG. 58 shows a structure of an active inductor of a gate resistance insertion type (S. Lucyszyn et al., "Monolithic narrow-band fil").
ter using ultrahigh-Q tunable active inductors ", I
EEE Transactions on Microwave Theory and Technique
s, vol.42, pp.2617-2622, Dec. 1994). In the active inductor 1100, similarly to the second conventional example, the source-grounded FET 31 and the gate-grounded FET 35 are cascode-connected, and one-way feedback is applied from the FET 35 to the FET 31 by the gate-grounded FET 39. In addition to this, a resistor 50 having a resistance value R _{0 is connected} between the gate 42 of the FET 39 and the DC voltage blocking capacitor C by the FET 31.
A feedback resistor 16 (resistance value R) for adjusting the inductance is inserted between the gate 34 and the drain 40 of the FET 39.

Next, the terminal 1 of the active inductor 1100.
The impedance Z _{0 of} the circuit viewed from 7, 18 is obtained.
In order to simplify the circuit analysis, as in the first conventional example,
The resistance value of the resistor 16 that functions as a feedback resistor for adjusting the inductance value is set to R = 0Ω, and the FET 31, FET 35,
The FET 39 has electrically the same characteristics, and the depletion layer capacitances Cgs1, Cgs2, Cgsf between the gate and the source immediately below the gate,
If the transconductances gm1, gm2, and gmf are used alone, the impedance Z ₀ is

(Equation 5) Given in. Here, the cutoff frequency f _T of the FET is f _T
= Gm1 / (2πCgs1) = gm2 / (2πCgs2) = gm
f / (2πCgsf). In the same wafer, it is possible to easily form an FET having such characteristics that cutoff frequencies f _T are equal.

As shown in FIG. 59, the active inductor 11
The equivalent circuit of 00 has a resistance value of 1 / {(f / f _T ) ² gmf}
Resistance 61 and inductance value Cgs1 / {gm1 gmf}
Parallel circuit of the inductance 62 of, and the resistance value- (f / f
_T ) ² R ₀ negative resistance 63 and inductance Cgsf R ₀ /
It is almost the same as a series circuit including a parallel circuit of the inductance 64 of {(f / f _T ) ² gmf}.

FET having a gate width of 100 μm (transconductance gm = 20 mS, depletion layer capacitance Cgs = 0.16 p)
F, drain conductance Gd = 0,1,2 mS, cut-off frequency f _T = gm / (2πCgs) = 20 GHz), the frequency characteristics of L and R with respect to the impedance Z ₀ are shown in FIG. Shown in b). Here, it is assumed that the FETs to be used have the same gate width. Also, here, the resistance value R
The case of ₀ = 50Ω is shown. As described above, since the active inductor 1100 generates the negative resistance that depends on the frequency, the loss can be reduced by adjusting the resistance value R ₀ , but the frequency range in which the loss is compensated is narrow. It can be mentioned as a point.

As described above, in the existing active inductor, resistance loss occurs due to the effects of the drain conductance between the drain and source of the FET, the resistance for gate bias, the DC bias circuit, etc. It has a drawback that good operation cannot be realized in the above high frequency band. The present invention has been made in view of such a background, and even in a high frequency band higher than the microwave band, the inductance value is large and the resistance loss generated by the drain conductance or the like is compensated to reduce the loss. It is intended to provide an active inductor that can be realized.

[0027]

In order to solve the above-mentioned problems, the invention according to claim 1 generates a resistance loss that constantly occurs regardless of frequency and generates a negative resistance that is constant with respect to frequency. It is characterized in that it has a first compensating means for canceling it out, and is composed of only active elements. In the invention according to claim 2, in the invention according to claim 1, the resistance loss that increases as the frequency becomes higher is canceled by generating a negative resistance having a frequency characteristic that is contrary to the frequency characteristic of the resistance loss. It is characterized in that it has a second compensating means. The invention of claim 3 is the same as claim 1 or 2.
In the invention described above, the first compensating means is characterized in that the negative resistance is generated in series with respect to an inductance component existing in the active inductor.

According to a fourth aspect of the invention, the first transistor and the first electrode are the second transistor of the first transistor.
A second transistor connected to the electrode, a second electrode connected to the third electrode of the first transistor, and a first electrode connected to the second electrode of the second transistor;
An electrode is connected to the third electrode of the second transistor,
A third electrode having a third electrode connected to the first electrode of the first transistor, and a connection line between the third electrode of the second transistor and the second electrode of the third transistor. It is characterized in that the first terminal drawn out and the second terminal drawn out from the second electrode of the first transistor are two terminals. According to a fifth aspect of the invention, in the invention of the fourth aspect, the connection line between the third electrode of the second transistor and the second electrode of the third transistor and the first terminal are connected. It is characterized in that a first resistance element is inserted between them.

The invention according to claim 6 is the invention according to claim 4 or 5, wherein a second resistor is provided between the second electrode of the second transistor and the first electrode of the third transistor. The feature is that an element is inserted. Also,
The invention according to claim 7 is the invention according to any one of claims 4 to 6, wherein a third resistor is provided between the second electrode of the first transistor and the first electrode of the second transistor. The feature is that an element is inserted.

The invention according to claim 8 is the invention according to claims 4 to 4.
The invention according to any one of items 7 to 7 is characterized in that a fourth resistance element is inserted between the first electrode of the first transistor and the second electrode of the first transistor. The invention according to claim 9 is the invention according to any one of claims 4 to 8, wherein a fifth electrode is provided between the first electrode of the first transistor and the third electrode of the third transistor. It is characterized in that the resistance element of is inserted.

The invention according to claim 10 is the invention according to claim 4
In the invention according to any one of items 1 to 9, a first capacitor is connected between the first electrode and the second electrode of the first transistor, and the first electrode and the second electrode of the second transistor are connected. A second capacitor is connected in between, and a third capacitor is connected between the first electrode and the second electrode of the third transistor.

The invention according to claim 11 is the invention according to claim 4.
In the invention according to any one of 10 to 10, the third electrode of the first transistor and the second electrode of the second transistor are included.
Insert m (m ≧ 1) transistors between the electrodes,
It is characterized in that the m transistors are cascode-connected to the first transistor. The invention of claim 12 is the same as the invention of claim 11,
A capacitor is connected between the first electrode and the second electrode of each of the m transistors.

The invention according to claim 13 is the same as claim 4
In the invention according to any one of 1 to 12, the first electrode of the first transistor and the third electrode of the third transistor
Insert n (n ≧ 1) transistors between the electrodes,
The n transistors are cascode-connected to the third transistor. The invention of claim 14 is the same as the invention of claim 13,
A capacitor is connected between the first electrode and the second electrode of each of the n transistors.

The invention according to claim 15 is the same as claim 4
The invention of any one of claims 1 to 14, wherein the third electrode of the second transistor and the second electrode of the third transistor are provided.
Insert p (p ≧ 1) transistors between the electrodes,
It is characterized in that the p transistors are cascode-connected to the second transistor. The invention of claim 16 is the same as the invention of claim 15,
A capacitor is connected between the first electrode and the second electrode of each of the p transistors.

In the present invention, each transistor is an FET or a HEMT (High Electron Mobility T
In the case of ransistor), the first electrode of these transistors is a gate electrode, the second electrode is a source electrode, and the third electrode is a drain electrode. When each transistor is a bipolar transistor, the first electrode of these transistors is a base electrode, the second electrode is an emitter electrode, and the third electrode is a collector electrode.

[0036]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. [Embodiment 1] FIG. 1 is a circuit diagram of an active inductor 100 according to this embodiment. In this figure, terminals 17,
18 is a terminal when this circuit is regarded as an inductor element, Z ₀ is an impedance when this circuit is viewed from terminals 17 and 18, C is a DC voltage blocking capacitor, and P is a point to which a voltage is applied. Is.

Reference numerals 31, 39 and 43 denote FETs, each of which has a capacitance of Cgs as a depletion layer capacitance between the gate and the source immediately below the gate.
1, Cgsf, Cgsa, and gm1, gmf, gma as transconductance, respectively. Further, G, S, and D shown in the drawing are a gate electrode, a source electrode, and a drain electrode of the FET, respectively. That is, the terminals 32, 40,
44 is the drain electrode of FET31,39,43, respectively, and terminals 33,41,45 are FET31,3 respectively.
Source electrodes 9 and 43 and terminals 34, 42 and 46 are gate electrodes of FETs 31, 39 and 43, respectively. Also,
50 is a resistor having a resistance value R ₀ .

In the active inductor 100, the FET 31 having the source grounded is fed back in one direction by the FET 39 and the FET 43 which are cascode-connected with the gate grounded. A resistor 50 is connected between the terminal 17 and a connection point between the drain 40 of the FET 39 and the source 45 of the FET 43.

Next, the impedance Z ₀ as viewed from the FET 39 side from the terminals 17 and 18 is obtained. In order to simplify the circuit analysis, the FET 31, FET 39, and FET 43 all have the same electrical characteristics, and each has a gate-source depletion layer capacitance Cgs1, Cgsf, Cgsa and transconductance gm1, gmf directly below the gate. If expressed only by gma, the impedance Z ₀ is given by the following equation.

(Equation 6)

Now, the cutoff frequency of the FET f _T = gm1 /
(2πCgs1) = gmf / (2πCgsf) = gma / (2π
Cgsa). The equivalent circuit at this time is shown in FIG. As shown in the figure, the resistor 50 having the resistance value R ₀ and the resistance value (−1
/ Gmf) resistance 61 and inductance value {(1 / gmf
+ / Gma) Cgs1 / gm1} is substantially the same as the series circuit of the inductance 62.

When the resistance value R ₀ of the resistor 50 is set to 1 / gmf which has the same magnitude as the resistance value of the resistor 61, the resistance component in the equation (6) is canceled out, and the impedance Z ₀ is given only by the inductance component. Operates as a lossy inductor. This will be described with reference to FIG. This figure is a frequency characteristic diagram in which the horizontal axis represents frequency and the vertical axis represents resistance value R of the resistance of the active inductor. When the resistor 50 does not exist, the resistance value of the active inductor is the value of “resistance loss that occurs steadily + negative resistance” in the figure, and has a negative resistance value. That is, by generating a “negative resistance” in contrast to the conventional “steadily occurring resistance loss”, the resistance value of these sums becomes a negative resistance value. On the other hand, the resistance value of the resistor 50 is the value of "series resistance" in the figure, and has a positive resistance value. Therefore, by setting the resistance value of the resistor 50 to have the same magnitude as that of the sum of these resistance values with the opposite sign, the resistance values are offset, and the characteristic after “compensation” in FIG. it can.

Next, an FET having a gate width of 100 μm (transconductance gm = 20 ms, depletion layer capacitance Cgs = 0.
16 pF, cutoff frequency f _T = gm / (2πCgs) = 20
The frequency characteristics of L and R with respect to the impedance Z ₀ in the active inductor using (GHz) are shown in FIGS. 4 (a) and 4 (b). Here, it is assumed that the FETs to be used have the same gate width. Further, the resistance value R ₀ of the resistor 50 is set to 0. further,
In this figure, the drain conductance Gd = 0, 1, 2,
Four cases of 4 mS are shown. Note that, as described above, all the FETs have the same drain conductance Gd because all the FETs have the same electrical characteristics.

It can be seen from the frequency characteristic of the resistance component R shown in FIG. 4 (b) that it has a negative resistance. Therefore, as described above, the equivalent resistance value can be set to 0 by adjusting the resistance value of the resistor 50 to this negative resistance value.
As described above, by appropriately setting the resistance value R ₀ of the resistor 50, it is possible to compensate for the resistance loss that occurs steadily and to provide a low-loss frequency characteristic. Therefore, it can be seen that the active inductor of this embodiment operates well even at frequencies in the microwave band and above.

[Second Embodiment] FIG. 5 is a circuit diagram of an active inductor 200 according to this embodiment. In this figure, the same parts, signals and the like as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. As can be seen from the comparison with FIG. 1, the active inductor 200 further includes a resistor 71 having a resistance value Rf1 with respect to the active inductor 100 described above.

That is, the active inductor 200 is
One-way feedback is performed to the source-grounded FET 31 by the FET 39 and the FET 43, which are cascode-connected with the gate grounded. In addition, the drain 40 and F of the FET 39
A resistor 50 having a resistance value R ₀ is connected between the connection point of the source 45 of the ET 43 and the terminal 17, and a resistor 71 is connected between the source 41 of the FET 39 and the gate 46 of the FET 43.

Next, the impedance Z ₀ as viewed from the FET 39 side from the terminals 17 and 18 is obtained. In order to simplify the circuit analysis, the FET 31, FET 39, and FET 43 all have the same electrical characteristics, and each has a gate-source depletion layer capacitance Cgs1, Cgsf, Cgsa and transconductance gm1, gmf directly below the gate. If expressed only by gma, the impedance Z ₀ is given by the following equation.

(Equation 7)

Now, the cutoff frequency of the FET f _T = gm1 /
(2πCgs1) = gmf / (2πCgsf) = gma / (2π
Cgsa). FIG. 6 shows a circuit diagram of an equivalent circuit at this time. As shown in the figure, a resistor 50 having a resistance value R ₀ , a resistor 61 having a resistance value − {1 / gmf + (f / f _T ) ² Rf 1} and an inductance value {(1 / gmf + 1 / gma) Cgs1 / g
It is almost the same as the series circuit of the inductance 62 of (m1). The resistance value R ₀ of the resistor 50 is the same as that of the resistor 61.
When {1 / gmf + (f / f _T ) ² Rf1} is set, the resistance component in the equation (7) is canceled out, and the impedance Z ₀ is given only by the inductance component to operate as a lossless inductor.

Here, a FET having a gate width of 100 μm (transconductance gm = 20 ms, depletion layer capacitance Cgs =
0.16 pF, cutoff frequency f _T = gm / (2πCgs) =
The resistance value Rf1 of the resistor 71 for an active inductor using 20 GHz and drain conductance Gd = 2 mS)
7 (a) and 7 (b) show the frequency characteristics of L and R with respect to the impedance Z ₀ when V is changed.
Shown in In this figure, three cases of resistance values Rf1 = 0, 10, 50Ω are shown. The gate widths of the FETs used are the same. The resistance value R ₀ of the resistor 50 is 0.

From the above-mentioned frequency characteristic diagram of the resistance component R in FIG. 4B, it can be seen that the frequency characteristic of resistance loss changes when the drain conductance value changes. However, as shown in FIG. 7B, since the frequency characteristic of the generated negative resistance changes according to the resistance value Rf1 of the resistance 71,
By appropriately setting the resistance value Rf1, it is possible to compensate for the above change in the frequency characteristic. That is, the resistor 6 in FIG.
The frequency dependence of {-(f / f _T ) ² Rf1} of 1 can cancel the frequency characteristic of the resistance loss generated by the change of the drain conductance value shown in FIG. 4B.

This will be described with reference to FIG. This figure is a frequency characteristic diagram when the horizontal axis represents frequency and the vertical axis represents resistance value R of the resistance of the active inductor. FIG.
The frequency characteristic of the resistance component shown in (b) corresponds to “resistance resistance increasing as frequency becomes higher” in FIG. 8, and has a positive resistance value in the frequency region exceeding about 10 GHz. On the other hand, based on the resistance value Rf1 of the resistor 71 {-
The frequency characteristic of (f / f _T ) ² Rf1} corresponds to “negative resistance generated by insertion resistance” in FIG.
It has a negative resistance value in the frequency region exceeding the vicinity of z. Therefore, the change in the frequency characteristic due to the resistance loss is canceled out, and the characteristic “after compensation” in FIG. 8, that is, the characteristic of the resistance loss “0” is obtained.

As described above, by adjusting the resistance value Rf1 of the resistor 71, it is possible to perform appropriate loss compensation for a given drain conductance value. Also, the resistance 50
By appropriately setting the resistance value R ₀ of R, the resistance loss that occurs steadily (see FIG. 3) can be compensated, and low loss frequency characteristics can be provided. Therefore, it can be seen that the active inductor of this embodiment operates well even at frequencies in the microwave band and above.

[Third Embodiment] FIG. 9 is a circuit diagram of an active inductor 300 according to this embodiment. In this figure, the same parts, signals and the like as those in FIG. 5 are designated by the same reference numerals, and the description thereof will be omitted.

In the active inductor 300, the FET 31 having the source grounded is fed back in one direction by the FET 39 and the FET 43 connected in cascode with the gate grounded. Further, a resistor 50 having a resistance value R ₀ is connected between the connection point between the drain 40 of the FET 39 and the source 45 of the FET 43 and the terminal 17, and a resistor 72 having a resistance value Rf 2 is connected between the gate 42 of the FET 39 and the source 33 of the FET 31. Are connected.

Next, the impedance Z ₀ as viewed from the FET 39 side from the terminals 17 and 18 is obtained. In order to simplify the circuit analysis, the FET 31, FET 39, and FET 43 all have the same electrical characteristics, and each has a gate-source depletion layer capacitance Cgs1, Cgsf, Cgsa and transconductance gm1, gmf directly below the gate. If expressed only by gma, the impedance Z ₀ is given by the following equation.

(Equation 8)

Now, the cutoff frequency of the FET f _T = gm1 /
(2πCgs1) = gmf / (2πCgsf) = gma / (2πCgs
a). FIG. 10 shows a circuit diagram of an equivalent circuit at this time. As shown in the figure, the resistance 50 with the resistance value R ₀ and the resistance value
- {1 / gmf + (f / f T) 2 Rf2} resistor 61 and the inductance value of {(1 / gmf + 1 / gma-Rf2) Cgs1
/ Gm1} is almost the same as the series circuit of the inductance 62. If the resistance value R ₀ of the resistor 50 is {1 / gmf + (f / f _T ) ² Rf2} having the same magnitude as that of the resistor 61, the resistance component in the equation (8) is canceled out, and the impedance Z ₀ is only an inductance component. Given, it operates as a lossless inductor.

Here, a FET having a gate width of 100 μm (transconductance gm = 20 ms, depletion layer capacitance Cgs =
0.16 pF, cutoff frequency f _T = (gm / 2πCgs) =
The resistance value of the resistor 72 is Rf2 with respect to the active inductor using 20 GHz and drain conductance Gd = 2 mS.
11 (a) and 11 (b) show the frequency characteristics of L and R with respect to the impedance Z ₀ when V is changed. In this figure, three cases of resistance values Rf2 = 0, 10, 50Ω are shown. The gate widths of the FETs used are the same.
The resistance value R ₀ of the resistor 50 is 0.

From the above-mentioned frequency characteristic diagram of the resistance component R in FIG. 4B, it can be seen that the frequency characteristic of the resistance loss changes when the drain conductance value changes. However, as shown in FIG. 11B, since the frequency characteristic of the generated negative resistance changes according to the resistance value Rf2 of the resistor 72, by appropriately setting the resistance value Rf2 of the resistor 72, As in the case of 2, it is possible to compensate for the change in the frequency characteristic.

As described above, by adjusting the resistance value Rf2 of the resistor 72, it is possible to perform appropriate loss compensation for a given drain conductance value. Also, the resistance 50
By appropriately setting the resistance value R ₀ of R, the resistance loss that occurs steadily (see FIG. 3) can be compensated, and low loss frequency characteristics can be provided. Therefore, it can be seen that the active inductor of this embodiment operates well even at frequencies in the microwave band and above.

[Fourth Embodiment] FIG. 12 is a circuit diagram of an active inductor 400 according to this embodiment. In this figure, the same parts, signals and the like as those in FIG. 5 are designated by the same reference numerals, and the description thereof will be omitted.

In the active inductor 400, the FET 31 having the source grounded is fed back in one direction by the FET 39 and the FET 43 connected in cascode with the gate grounded. A resistor 50 having a resistance value R ₀ is connected between the connection point between the drain 40 of the FET 39 and the source 45 of the FET 43 and the terminal 17, and a resistor 73 having a resistance value Rf3 is connected between the gate 34 and the source 33 of the FET 31. are doing.

Next, the impedance Z ₀ seen from the FET 39 side from the terminals 17 and 18 is obtained. In order to simplify the circuit analysis, the FET 31, FET 39, and FET 43 all have the same electrical characteristics, and each has a gate-source depletion layer capacitance Cgs1, Cgsf, Cgsa and transconductance gm1, gmf directly below the gate. It is assumed that each is expressed only by gma. The circuit diagram of the equivalent circuit at this time is as shown in FIG. 13 in a low frequency band of about several GHz. The resistance value Rf3 of the resistor 73 is {gmf / (gm1
gma)}, the resistance value of the resistor 61 becomes zero. Therefore, by setting the resistance value R ₀ of the resistor 50 to 0, the resistance component can be ignored, and the impedance Z ₀ is given only by the inductance component.

Here, a FET having a gate width of 100 μm (transconductance gm = 20 ms, depletion layer capacitance Cgs =
0.16 pF, cutoff frequency f _T = gm / (2πCgs) =
The resistance value of the resistor 73 is Rf3 for an active inductor using 20 GHz and drain conductance Gd = 2 mS).
14 (a) and 14 (b) show the frequency characteristics of L and R with respect to the impedance Z ₀ when V is changed. In this figure, three cases of resistance values Rf3 = 50, 100, 1 GΩ are shown. The gate widths of the FETs used are the same. The resistance value R ₀ of the resistor 50 is 0.

From the frequency characteristic diagram of the resistance component R shown in FIG. 4B, it can be seen that the frequency characteristic of resistance loss changes when the drain conductance value changes. However, as shown in FIG. 14B, since the frequency characteristic of the generated negative resistance changes according to the resistance value Rf3 of the resistor 73, by appropriately setting the resistance value Rf3 of the resistor 73, As in the case of 2, it is possible to compensate for the change in the frequency characteristic.

As described above, by adjusting the resistance value Rf3 of the resistor 73, it is possible to perform appropriate loss compensation for a given drain conductance value. Also, the resistance 50
By appropriately setting the resistance value R ₀ of R, the resistance loss that occurs steadily (see FIG. 3) can be compensated, and low loss frequency characteristics can be provided. Therefore, it can be seen that the active inductor of this embodiment operates well even at frequencies in the microwave band and above.

[Fifth Embodiment] FIG. 15 is a circuit diagram of an active inductor 500 according to this embodiment. In this figure, the same parts, signals and the like as those in FIG. 5 are designated by the same reference numerals, and the description thereof will be omitted.

In this active inductor 500, the FET 31 having the source grounded is fed back in one direction by the FET 39 and the FET 43 connected in cascode with the gate grounded. Further, a resistor 50 having a resistance value R ₀ is connected between the connection point between the drain 40 of the FET 39 and the source 45 of the FET 43 and the terminal 17, and the drain 44 of the FET 43 is connected.
A resistor 74 having a resistance value Rf4 is connected between the gate of the FET 31 and the gate 34 of the FET 31.

Next, an FET having a gate width of 100 μm (transconductance gm = 20 ms, depletion layer capacitance Cgs = 0.
16 pF, cutoff frequency f _T = gm / (2πCgs) = 20
16 (a) and FIG. 16 (a) and FIG. 16 (a) and FIG. 16 (a) and FIG. 16 (a) and FIG. 16 (b) show the frequency characteristics of the impedance Z ₀ when the resistance value Rf4 of the resistor 74 is changed for an active inductor using GHz and drain conductance Gd = 2 mS). Shown in b). In this figure, three cases of resistance values Rf4 = 0, 200, 400Ω are shown. The gate widths of the FETs used are the same. The resistance value R ₀ of the resistor 50 is 0.

From the frequency characteristic diagram of the resistance component R shown in FIG. 4B, it can be seen that the frequency characteristic of resistance loss changes when the drain conductance value changes. However, as shown in FIG. 16B, since the frequency characteristic of the generated negative resistance changes according to the resistance value Rf4 of the resistor 74, by appropriately setting the resistance value Rf4 of the resistor 74, In the same manner as in 2, it is possible to compensate for the above change in the frequency characteristic.

As described above, by adjusting the resistance value Rf4 of the resistor 74, it is possible to perform appropriate loss compensation for a given drain conductance value. Also, the resistance 50
By appropriately setting the resistance value R ₀ of R, the resistance loss that occurs steadily (see FIG. 3) can be compensated, and low loss frequency characteristics can be provided. Therefore, it can be seen that the active inductor of this embodiment operates well even at frequencies in the microwave band and above.

In the active inductors of the above-described embodiments, the resistance element and the capacitor are not essential, and the active inductors can be configured by only the active elements. Therefore, the circuit size can be reduced by reducing the number of elements. In addition, the self-resonant frequency can be made higher than that of an inductor that requires a passive element such as a capacitor. Also, by changing the voltage at the voltage application point P to the gate of the FET,
Since the transconductance gm of the FET changes and the inductance value of the active inductor can be changed, a voltage adjustment type active inductor can be realized.

[Modification 1] In the above-described first to fifth embodiments, if the equivalent circuit at low frequency is the same as that of each of these embodiments, a circuit configuration other than the above may be adopted. As a first example of such a circuit configuration, a configuration in which the source-grounded FET 31 in each of the active inductors described above is replaced with a cascode connection circuit including a source-grounded FET and a gate-grounded FET can be considered. Circuit diagrams of the active inductor thus configured are shown in FIGS. 17 to 21 corresponding to the first to fifth embodiments, respectively.

For example, to explain the circuit configuration corresponding to the first embodiment, in the circuit of FIG. 17, the FET 35 is added to the circuit of FIG. 1, and the source-grounded FET 31 of FIG. It is replaced by a source grounded cascode FET. It should be noted that it is also possible to add another FET to the stage subsequent to the FET 35 to increase the number of source-grounded cascode FETs. And even if comprised as mentioned above, Embodiment 1
The same action and effect as those described in 5 are obtained.

[Modification 2] As a second example in which the equivalent circuit at low frequencies is the same as in the first to fifth embodiments, a configuration in which the FET 39 forming the gate-grounded cascode FET is cascode-connected can be considered. As an example thereof, FIG. 22 shows a circuit configuration when such a modification is applied to the circuit of the first embodiment (see FIG. 1). As shown in this figure, a new FET 81 is inserted between the drain 40 of the FET 39 and the source 45 of the FET 43.
Source 83 of T81 and drain 40 of FET 39 and FE
Connected to the gate 46 of T43 and the gate 8 of FET 81
4, the drain 82 is the source 41 of the FET 39,
It is connected to the source 45 of the FET 43.

Now, in order to simplify the circuit analysis, FE
T81 has a FET 31, FET 39, FET 43 is electrically the same characteristics, and is expressed only in the depletion layer capacitance Cgsb and transconductance gmb between the gate and source of the gate immediately below, cut-off of the FET frequency f _T = gm1 / ( Two
πCgs1) = gmf / (2πCgsf) = gma / (2πCgs
a) = gmb / (2πCgsb). Then, Figure 2
The equivalent circuit at low frequency of the active inductor shown in 2 is a resistance of resistance R ₀ and a negative resistance of resistance − (1 / gmf + 1 / gmb) and an inductance value {(1 / gmb + 1 / gma)
It is almost the same as the series circuit of the inductance of Cgs1 / gm1}. Therefore, the transconductances gmb and gmf
Are equal to each other, the circuit becomes the same as the equivalent circuit of the active inductor shown in FIG. 1 (see FIG. 2) except that the negative resistance value is doubled. And, such a large negative resistance value
It is convenient to consider the case where an active inductor is used for the oscillator.

Needless to say, the same modifications can be made to the second to fifth embodiments. In addition, FET8
It is also possible to add a FET to the subsequent stage of 1 to increase the number of stages of cascode connection. And even if comprised as mentioned above, the same effect | action and effect as what was demonstrated in Embodiment 1-5 can be acquired.

[Modification 3] Furthermore, as a third example in which the equivalent circuit at low frequencies is the same as that of the first to fifth embodiments, a configuration in which the FET 43 forming the cascode FET with the grounded gate is connected in cascode is conceivable. As an example thereof, FIG. 23 shows a circuit configuration when such a modification is applied to the circuit of the first embodiment (see FIG. 1). As shown in this figure, a new FET 85 is inserted between the drain 44 of the FET 43 and the gate 34 of the FET 31.
The source 87 and the gate 88 of 85 are connected to the drain 44 and the source 45 of the FET 43, respectively, and the drain 86 of the FET 85 is connected to the gate 34 of the FET 31.

Needless to say, similar modifications can be made to the second to fifth embodiments. In addition, FET8
It is also possible to add a FET to the subsequent stage of 5 and increase the number of stages of cascode connection. Even with the above configuration, the same operation and effect as those described in the first to fifth embodiments can be obtained. Furthermore, as long as the equivalent circuit at the low frequency is the same, circuit configurations other than the modified examples 1 to 3 may be used.

[Modification 4] In Embodiments 2 to 5 described above, in order to generate the negative resistance depending on the frequency, only one resistor 71 to 74 having resistance values Rf1 to Rf4 is inserted at different positions. ing. However, the present invention is not limited to this, and by combining these embodiments, a resistance element for generating a negative resistance depending on the frequency may be inserted in two or more places.

Therefore, first, FIGS. 24 to 29 show circuit configurations when the resistance element is inserted at two places. FIG.
Corresponds to the combination of the second and third embodiments, and FET 39
Between the source 41 and the gate 46 of the FET 43
The resistor 71 of is inserted, and the gate 42 of the FET 39 and the FET
A resistor 72 having a resistance value Rf2 is inserted between the source 33 of 31 and the resistor 33.

FIG. 25 shows a combination of the second and fourth embodiments, in which a resistor 71 having a resistance value Rf1 is inserted between the source 41 of the FET 39 and the gate 46 of the FET 43, and the FET 3 is connected.
A resistor 73 having a resistance value Rf3 between the source 33 and the gate 34 of 1
Is inserted. Further, FIG. 26 shows the second embodiment.
5 is a combination of 5 and the source 41 of FET 39 and F
A resistor 71 having a resistance value Rf1 is inserted between the gate 46 of the ET43, the gate 34 of the FET 31 and the drain 4 of the FET 43.
The resistor 74 having the resistance value Rf4 is inserted between the four resistors.

Similarly, FIG. 27 is a combination of the third and fourth embodiments, FIG. 28 is a combination of the third and fifth embodiments, and FIG.
9 is a combination of the fourth and fifth embodiments. Next, the circuit configuration in the case where the resistance element is inserted at three places is shown in FIG.
It shows in FIG. FIG. 30 shows a combination of the second, third and fourth embodiments, FIG. 31 shows a combination of the second, third and fifth embodiments, FIG. 32 shows a combination of the second, fourth and fifth embodiments, and FIG. This is a case where 3, 4, 5 are combined. Furthermore, when the resistance elements are inserted at all four positions, the circuit configuration is as shown in FIG. Even in the case of the above configuration, by adjusting the resistance values Rf1 to Rf4 of the inserted resistors 71 to 74, the same loss compensation as in the second to fifth embodiments can be realized.

[Fifth Modification] In the first to fifth embodiments described above, the resistor 50 is omitted, that is, the resistance value R ₀ =
The circuit configuration may be 0Ω. FIG. 35 shows the circuit configuration of the active inductor configured as described above in the case of the first embodiment. In addition, regarding Embodiments 2 to 5, it suffices to remove the resistor 50 from FIGS. 5, 9, 12, and 15, and those skilled in the art can easily recall the circuit configuration. Omit it.

[Modification 6] For the purpose of obtaining a large inductance value, as shown in FIG. 36, each FET may be connected with a capacitor. The active inductor 600 shown in this figure is the active inductor 1 of the first embodiment.
00 (see FIG. 1), source 3 of FET 31
3, between gate 34, source 41 of FET 39, gate 4
2 and between the source 45 and the gate 46 of the FET 43, capacitors 51 and 5 having capacitances C1, C2 and C3, respectively.
2, 53 are connected.

Here, the impedance Z ₀ of the active inductor 600 viewed from the terminals 17 and 18 is obtained by replacing the capacitance Cgs1 in the equation (6) with (C1 + Cgs1). Therefore, although the cutoff frequency f _T is smaller than that in the first embodiment, the capacitance Cgs1 in the equation (6) is reduced.
Becomes equivalently large, and an inductance value larger than that of the active inductor 100 of the first embodiment can be obtained.

Also in the active inductors of Embodiments 2 to 5, the same effect of increasing the inductance value can be obtained by connecting a capacitor to each FET. Even with such a configuration, since the active inductor can be essentially configured with only the transistor and the capacitor,
It is possible to reduce the size of the circuit as in each of the above embodiments.

[Modification 7] In each of the above embodiments, the case where the FET is used as the active element of three terminals is shown, but the invention is not limited to this, and for example, a bipolar transistor or a HEMT.
Can be similarly configured by using. In addition, the modification 1 mentioned above
It goes without saying that the modified example 7 may be arbitrarily combined.

<Experimental Example 1> The following is a result of trial production of an active inductor having the circuit configuration shown in FIG. 17 (a configuration obtained by modifying the first embodiment by a modification 1). In the experiment,
FETs 31, 35, 39, 43 and D in FIG.
HEM with a gate width of 25 μm as a C bias FET
T (mutual conductance gm = 11 mS) was used, and the resistance value of the resistor 50 was set to R ₀ = 36Ω. The gate bias resistance was 2 kΩ and each was connected to the source electrode of the FET. The bias conditions were a drain voltage of 10 V and a drain current of 15 mA. The chip size is 0.43
It was × 0.40 mm ² .

FIG. 37 shows the simulation result of the S parameter, and the series resistance value at 1 GHz is 0.3Ω. On the other hand, FIG. 38 shows the result of the measured S parameter. The measured resistance value and inductance value are larger than the simulation results shown in FIG. 37, but this is due to the parasitic capacitance due to the pattern layout,
It is considered that this is due to the influence of the impedance of the FET for DC bias, and furthermore, since the gate bias resistors of the FET are connected to the source electrodes of the FETs respectively, the bias is fixed and the negative resistance value is finely adjusted. It is thought that it is not possible to do. The series resistance value at 1 GHz was 0.8Ω, which was 28 in terms of Q value conversion.

<Experimental Example 2> The details of the results of another experiment using the circuit configuration of the first embodiment will be described below. FIG. 39 shows a detailed circuit diagram of the active inductor used in this experiment. The FETs 31, 39, 43 and the FET 51 for DC bias shown in the figure are all InAlAs / InG with a gate length of 0.1 μm.
HEAs of aAs / InP was used. These HEMTs are 25
μm width, average f _T = 140 GHz, f _max = 180 GH
z, and the source and drain electrodes are made of non-alloy ohmic contact, and n ⁺ -InGaAs / n ⁺ -In is used to reduce the contact resistance.
An AlAS cap layer was used. The bias condition is Vg
1 = 0.0V, Vg2 = 1.2V, Vg3 = 2.4V,
Vg4 = 3.5V, Vd = 4.9V, drain current Id
= 11 mA. The resistance value R ₀ was 29Ω, and the chip size was 0.78 × 0.40 mm ² .

FIG. 40 shows S-parameters measured for 2 GHz to 26 GHz. As a result, 0.045G
The series resistance is maintained at 0Ω or more in the frequency range of Hz to 26.5 GHz, and the loss compensation is performed up to the range exceeding 20 GHz. The S parameter at 2 GHz is capacitive due to the DC cut capacitor.

Further, FIG. 41 shows the measurement result of the frequency characteristic of the impedance when the impedance of the active inductor is represented by the series connection of the resistance and the inductance. The inductance values at 6 GHz and 20 GHz are 0.41 nH and 0.82, respectively.
nH and the Q value in the frequency range between them is 1
It is over 00. The inductance values at 7 GHz and 15 GHz are 0.44 nH and 0.
It is 59 nH, and the Q value in the frequency range between them is over 1000.

By the way, considering the application to active filters, phase shifters, oscillators, etc., it can be said that the stability against bias and temperature changes is important. FIG. 42 shows 1
It is a measurement result of the characteristic change when changing the bias voltage Vg3 at 8 GHz. The inductance values at 2.5V and 1.5V are 0.73nH and 0.8, respectively.
3 nH, and the Q value at these bias values is 35
It was 0 and 420. Also, at 18 GHz, -5
As a result of measurement with a temperature change of up to 55 ° C., changes in the inductance value and the resistance value were within 0.1 nH and within 2Ω, respectively.

Further, in order to investigate the dynamic range, changes in the inductance value and the resistance value when the incident power was changed at 2.6 GHz were examined. The apparatus configuration at this time is shown in FIG. As shown in the figure, the 2.6 GHz signal generated by the signal generator 81 was injected into the active inductor 83 via the circulator 82, and the reflected signal was observed by the spectrum analyzer 84. Figure 44
As shown in, the incident power is 1-dB gain compression point.
It is -1 dBm, and the power of the fundamental wave with respect to the power of the second harmonic exceeds 20 dB in the reflected signal. The phase deviation was less than 1 degree in the illustrated incident power range. Thus, the change in the inductance value and the resistance value can be ignored until the incident power is -1 dBm.

Furthermore, FIG. 45 shows 5 of the latest reports.
The results of comparing the bandwidths in these reports with the measured values of the present invention are shown for the measured Q values of more than 0. According to the conventional example, the maximum value of the measured frequency range is about 1 GHz to 2 GHz, whereas the present invention has a wider band and lower loss than this.

[0095]

As described above, according to the first, fourth, and fifth aspects.
According to the described invention, the resistance loss that constantly occurs regardless of the frequency is canceled by generating a constant negative resistance with respect to the frequency, and furthermore, the inductor can be configured by only the active element. As a result, the circuit size can be reduced by reducing the number of elements, and the self-resonant frequency can be increased as compared with an inductor that requires passive elements such as capacitors. Further, even in the frequency range above the microwave band, the impedance of the active inductor becomes only the inductance component and an arbitrary inductance value can be obtained, and an active inductor with low loss can be realized over a wide band from DC to high frequency band. Can also be obtained.

According to the second and sixth aspects of the invention, the resistance loss increasing as the frequency becomes higher is generated by the negative resistance having the frequency characteristic opposite to the frequency characteristic of the resistance loss. Since they cancel each other, the frequency characteristic of the resistance loss caused by the change of the drain conductance value can be canceled, and an effect that an appropriate loss compensation can be performed for a given drain conductance value can be obtained.

According to the third aspect of the invention, since the negative resistance is generated in series with respect to the inductance component existing in the active inductor, the frequency range in which the loss is compensated can be widened. can get. Further, according to the inventions of claims 10, 12, 14, and 16, since the capacitor is connected between the first electrode and the second electrode of each transistor, the capacitance value of the depletion layer capacitance of each transistor is It can be increased equivalently, and the effect that the inductance value of the active inductor can be increased is obtained.

According to the eleventh, thirteenth, and fifteenth aspects of the present invention, one or more transistors are connected to the cascode for each of the first to third transistors. The effect that an active inductor having the same equivalent circuit at low frequency as the inductor can be realized by different circuit configurations is obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an active inductor according to Embodiment 1 of the present invention.

FIG. 2 is a circuit diagram of an equivalent circuit of the active inductor according to the same embodiment.

FIG. 3 is a diagram for explaining the principle of “loss compensation by series resistance” adopted by the present invention.

FIG. 4 is a diagram showing frequency characteristics of an inductance L (FIG. 4A) and a resistance R (FIG. 4B) of the active inductor according to the same embodiment.

FIG. 5 is a circuit diagram of an active inductor according to Embodiment 2 of the present invention.

FIG. 6 is a circuit diagram of an equivalent circuit of the active inductor according to the same embodiment.

FIG. 7 is a diagram showing frequency characteristics of an inductance L (FIG. 7A) and a resistance R (FIG. 7B) of the active inductor according to the same embodiment.

FIG. 8 is a diagram for explaining the principle of “loss compensation by insertion resistance” adopted by the present invention.

FIG. 9 is a circuit diagram of an active inductor according to Embodiment 3 of the present invention.

FIG. 10 is a circuit diagram of an equivalent circuit of the active inductor according to the same embodiment.

FIG. 11 is an inductance L (FIG. 11A) and a resistance R (FIG. 11B) of the active inductor according to the embodiment.
It is a figure which shows the frequency characteristic of.

FIG. 12 is a circuit diagram of an active inductor according to Embodiment 4 of the present invention.

FIG. 13 is a circuit diagram of an equivalent circuit of the active inductor according to the same embodiment.

FIG. 14 is an inductance L (FIG. 14A) and a resistance R (FIG. 14B) of the active inductor according to the same embodiment.
It is a figure which shows the frequency characteristic of.

FIG. 15 is a circuit diagram of an active inductor according to Embodiment 5 of the present invention.

FIG. 16 is an inductance L (FIG. 16A) and a resistance R (FIG. 16B) of the active inductor according to the same embodiment.
It is a figure which shows the frequency characteristic of.

FIG. 17 is a circuit diagram when a first modification of the present invention is applied to the first embodiment.

FIG. 18 is a circuit diagram when a first modification of the present invention is applied to the second embodiment.

FIG. 19 is a circuit diagram when a first modification of the present invention is applied to the third embodiment.

FIG. 20 is a circuit diagram when a first modification of the present invention is applied to the fourth embodiment.

FIG. 21 is a circuit diagram when the first modification of the present invention is applied to the fifth embodiment.

FIG. 22 is a circuit diagram when a second modification of the present invention is applied to the first embodiment.

FIG. 23 is a circuit diagram when a third modification of the present invention is applied to the first embodiment.

FIG. 24 is a circuit diagram when the second and third embodiments of the present invention are combined.

FIG. 25 is a circuit diagram when the second and fourth embodiments of the present invention are combined.

FIG. 26 is a circuit diagram when the second and fifth embodiments of the present invention are combined.

FIG. 27 is a circuit diagram when the third and fourth embodiments of the present invention are combined.

FIG. 28 is a circuit diagram when the third and fifth embodiments of the present invention are combined.

FIG. 29 is a circuit diagram in the case where the embodiments 4 and 5 of the present invention are combined.

FIG. 30 is a circuit diagram when the second, third and fourth embodiments of the present invention are combined.

FIG. 31 is a circuit diagram when the second, third and fifth embodiments of the present invention are combined.

FIG. 32 is a circuit diagram in the case where the embodiments 2, 4, and 5 of the present invention are combined.

FIG. 33 is a circuit diagram when the third, fourth and fifth embodiments of the present invention are combined.

FIG. 34 is a circuit diagram in the case of combining Embodiments 2 to 5 of the present invention.

FIG. 35 is a circuit diagram when a modified example 5 of the invention is applied to the first embodiment.

FIG. 36 is a circuit diagram when a modification 6 of the invention is applied to the first embodiment.

FIG. 37 is a diagram showing calculated values of S parameters regarding the active inductor to which the first modification of the present invention is applied to the first embodiment.

FIG. 38 is a diagram showing measured values of S parameters regarding an active inductor of Experimental Example 1 in which Modification 1 of the present invention is applied to Embodiment 1.

FIG. 39 is a detailed circuit diagram of an active inductor according to Experimental Example 2.

FIG. 40 is a diagram showing measurement results of S parameters of the active inductor according to the experimental example.

FIG. 41 is a frequency characteristic diagram of impedance of the active inductor according to the experimental example.

FIG. 42 is a diagram showing changes in the characteristics of the inductance and the Q value when the bias voltage of the FET forming the active inductor is changed in the experimental example.

FIG. 43 is a diagram showing a configuration of an apparatus for examining a dynamic range of an active inductor in the experimental example.

FIG. 44 is a diagram showing the relationship between the power of a signal incident on an active inductor and the power of a reflected signal in the same experimental example.

FIG. 45 is a diagram showing results of comparison of dynamic range between third and fifth conventional examples and the present invention in the same experimental example.

FIG. 46 is a circuit diagram of an active inductor according to a first conventional example.

FIG. 47 is a circuit diagram of an equivalent circuit of an active inductor according to the conventional example.

FIG. 48 is a diagram showing frequency characteristics of an active inductor according to the conventional example.

FIG. 49 is a circuit diagram of an active inductor according to a second conventional example.

FIG. 50 is a circuit diagram of an equivalent circuit of an active inductor according to the conventional example.

FIG. 51 is a diagram showing frequency characteristics of an inductance L ((a) in the figure) and a resistance R ((b) in the figure) of the active inductor according to the conventional example.

FIG. 52 is a circuit diagram of an active inductor according to a third conventional example.

FIG. 53 is a circuit diagram of an equivalent circuit of an active inductor according to the conventional example.

FIG. 54 is a diagram showing frequency characteristics of an inductance L ((a) in the figure) and a resistance R ((b) in the figure) of an active inductor according to the conventional example.

FIG. 55 is a circuit diagram of an active inductor according to a fourth conventional example.

FIG. 56 is a circuit diagram of an equivalent circuit of an active inductor according to the conventional example.

FIG. 57 is a diagram showing frequency characteristics of the inductance L ((a) in the figure) and the resistance R ((b) in the figure) of the active inductor according to the conventional example.

FIG. 58 is a circuit diagram of an active inductor according to a fifth conventional example.

FIG. 59 is a circuit diagram of an equivalent circuit of an active inductor according to the conventional example.

FIG. 60 is a diagram showing frequency characteristics of an inductance L ((a) in the figure) and a resistance R ((b) in the figure) of the active inductor according to the conventional example.

[Explanation of symbols]

C DC voltage blocking capacitor P Point at which voltage is applied via a coil that blocks high frequencies 16, 50, 61, 71-74 Resistors 17, 18 Terminals 31, 35, 39, 43, 81, 85 FET 32, 36, 40, 44, 82, 86 Drain 33, 37, 41, 45, 83, 87 Source 34, 38, 42, 46, 84, 88 Gate 51, 52, 53 Capacitor 62, 64 Inductance

Claims (16)

[Claims] 1. A first compensating means for canceling resistance loss that constantly occurs regardless of frequency by generating a constant negative resistance with respect to frequency, and is composed of only active elements. Active inductor characterized by. 2. A second compensating means for canceling the resistance loss which increases as the frequency increases by generating a negative resistance having a frequency characteristic that is contrary to the frequency characteristic of the resistance loss. The active inductor according to claim 1. 3. The first compensating means generates the negative resistance in series with respect to an inductance component existing in the active inductor.
Active inductor as described. 4. A first transistor, and a second transistor having a first electrode connected to a second electrode of the first transistor and a second electrode connected to a third electrode of the first transistor. A first electrode connected to the second electrode of the second transistor, a second electrode connected to the third electrode of the second transistor, and a third electrode connected to the first electrode of the first transistor A third transistor that is connected to the second electrode of the second transistor and a second terminal of the second transistor, and a third terminal of the first transistor, An active inductor comprising a second terminal drawn from two electrodes and two terminals. 5. A first resistance element is inserted between the connection line between the third electrode of the second transistor and the second electrode of the third transistor and the first terminal. The active inductor according to claim 4. 6. The active inductor according to claim 4, wherein a second resistance element is inserted between the second electrode of the second transistor and the first electrode of the third transistor. . 7. The third resistance element is inserted between the second electrode of the first transistor and the first electrode of the second transistor, according to any one of claims 4 to 6. The active inductor according to the item. 8. The fourth resistance element is inserted between the first electrode of the first transistor and the second electrode of the first transistor. The active inductor according to the item. 9. The fifth resistance element is inserted between the first electrode of the first transistor and the third electrode of the third transistor. The active inductor according to the item. 10. A first capacitor is connected between a first electrode and a second electrode of the first transistor, the second capacitor
A second capacitor is connected between the first electrode and the second electrode of the transistor, and a third capacitor is connected between the first electrode and the second electrode of the third transistor. Item 10. The active inductor according to any one of items 4 to 9. 11. m (m ≧ m) between the third electrode of the first transistor and the second electrode of the second transistor.
11. The active inductor according to claim 4, wherein 1) transistors are inserted, and the m transistors are cascode-connected to the first transistor. 12. The first of each of the m transistors
The active inductor according to claim 11, further comprising a capacitor connected between the electrode and the second electrode. 13. Between the first electrode of the first transistor and the third electrode of the third transistor, n (n ≧
13. The active inductor according to claim 4, wherein 1) transistors are inserted, and the n transistors are cascode-connected to the third transistor. 14. The first of each of the n transistors
14. The active inductor according to claim 13, further comprising a capacitor connected between the electrode and the second electrode. 15. Between the third electrode of the second transistor and the second electrode of the third transistor, p (p ≧
15. The active inductor according to claim 4, wherein 1) transistors are inserted, and the p transistors are cascode-connected to the second transistor. 16. The first of each of the p transistors
16. The active inductor according to claim 15, further comprising a capacitor connected between the electrode and the second electrode.