CN111988016B - Active inductor with large inductance value and high Q value at high frequency and with independently adjustable Q peak value at same frequency - Google Patents
Active inductor with large inductance value and high Q value at high frequency and with independently adjustable Q peak value at same frequency Download PDFInfo
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Abstract
Active inductance that big inductance value high Q value under high frequency and Q peak value can independently be adjusted under same frequency relates to the radio frequency integrated circuit field, includes: the circuit comprises a first transconductance unit (1), a second transconductance unit (2) with resistance and resistance-capacitance dual feedback, a resistance loss cancellation unit (3) with a bias voltage adjustable end and a bias unit (4) with two bias voltage adjustable ends. The first transconductance unit (1) and the second transconductance unit form a first impedance conversion loop on one hand, and form a second impedance conversion loop on the other hand, and the first impedance conversion loop and the second impedance conversion loop are connected in parallel, so that the inductance value is increased; the resistance loss counteraction unit improves the Q value; by jointly and cooperatively tuning the bias voltage of the two bias voltage adjustable ends in the bias unit and the bias voltage of one bias voltage adjustable end in the resistance loss counteracting unit, the independent tuning of the Q peak value of the active inductor under the same high frequency can be realized.
Description
Technical Field
The present invention relates to the field of radio frequency integrated circuits, and more particularly, to an inductor device having a high inductance and a high Q factor at high frequencies, and having an independently tunable Q peak at the same frequency in the high frequency range.
Background
As Radio Frequency Integrated Circuits (RFICs) such as filters, oscillators, and amplifiers have been developed to be small in size, reconfigurable in performance, and high in performance, there is a demand for high-frequency, high-Q, inductance, and tunable Q performance indexes as inductors that are basic components of RFICs.
However, the on-chip passive spiral inductor widely used in RFICs today is constructed of multiple turns of metal wire, the total length of which is linear with the desired inductance value. To obtain large inductance values, the metal lines need to be very long, which means large area, high chip cost and large loss resistance. At the same time, the large area also means large parasitic capacitance, resulting in low operating frequency and low Q-value at the chip passive spiral inductor. In addition, the sheet passive spiral inductor has the disadvantage that the inductance and Q value are not tunable because the geometric dimension of the metal wire is fixed. Therefore, although the on-chip passive spiral inductor has the advantages of good linearity and low power consumption, the above disadvantages make it difficult to adapt to the requirements of RFIC to small size, reconfigurable performance and high performance.
In order to overcome the disadvantages of on-chip passive spiral inductors, researchers have generated a great interest in inductors (active inductors, AI) synthesized using active devices. Since the active inductor is based on transistor synthesis, the performance of the active inductor is closely related to the used circuit topology, and therefore, optimizing the circuit topology is the key to improve the performance of the active inductor. At present, the topology of an active inductance circuit is not ideal enough, effective coordination is not available among all the components, and large inductance value, high Q value and excellent tuning characteristic are difficult to obtain at the same time under high frequency.
Disclosure of Invention
The invention aims to provide a novel tunable active inductor with large inductance value and high Q peak value, which can work at high frequency. The invention adopts two novel transconductance units, a tunable resistance loss offset unit and a tunable bias unit to form an inductance circuit topology, and through mutual cooperation and effective coordination among the units, the active inductor has a large inductance value and a high Q value under high frequency, and the Q peak value can be independently tuned under the same frequency of a high-frequency area.
The invention adopts the following technical scheme:
an active inductor which can simultaneously obtain a high Q value and a large inductance value at a high frequency and can independently tune a Q peak value at the same frequency of a high-frequency region, is characterized in that: the circuit comprises a first transconductance unit (1), a second transconductance unit (2) with resistance and resistance-capacitance dual feedback, a resistance loss cancellation unit (3) with one bias voltage adjustable end and a bias unit (4) with two bias voltage adjustable ends, and is shown in figure 1.
The first transconductance unit (1) in the active inductance circuit comprises a first N-type MOS transistor (M) n1 ) (ii) a The second transconductance unit (2) with resistance and resistance-capacitance dual feedback comprises a second N-type MOS transistor (M) n2 ) A third N-type MOS transistor (M) n3 ) The first passive sourceResistance (R) 1 ) A second passive resistor (R) 2 ) A first passive capacitor (C) 1 ) A second passive capacitor (C) 2 ) (ii) a The resistive loss cancellation unit (3) with a bias adjustable terminal comprises a voltage source with a second adjustable voltage source (V) tune2 ) Ninth N type MOS transistor (M) n9 ) (ii) a The bias unit (4) with two adjustable bias terminals comprises a fourth P-type MOS transistor (M) p4 ) And a fifth P type MOS transistor (M) p5 ) And a sixth N type MOS transistor (M) n6 ) And seventh N type MOS transistor (M) n7 ) With a first adjustable voltage source (V) tune1 ) Of the eighth N-type MOS transistor (M) n8 ) With a third adjustable voltage source (V) tune3 ) Of the tenth P-type MOS transistor (M) p10 )。
Wherein: input terminal (V) of the active inductor in ) Simultaneously connecting a first N-type MOS transistor (M) n1 ) Source electrode of (1), third N-type MOS transistor (M) n3 ) Gate of (b), sixth N type MOS transistor (M) n6 ) And a seventh N-type MOS transistor (M) n7 ) A gate and a drain of (1); third N-type MOS transistor (M) n3 ) With the tenth P-type MOS transistor (M) at the same time p10 ) Drain electrode of (1), second N-type MOS transistor (M) n2 ) Source electrode of (1), second passive capacitor (C) 2 ) Are connected with each other; second N-type MOS transistor (M) n2 ) Is simultaneously connected with a second passive capacitor (C) 2 ) First terminal, second passive resistor (R) 2 ) Is connected with the second end of the first end; second N-type MOS transistor (M) n2 ) With the drain of the fifth P-type MOS transistor (M) at the same time p5 ) Drain electrode of (1), ninth N-type MOS transistor (M) n9 ) The source electrodes of the two-way transistor are connected; ninth N type MOS transistor (M) n9 ) Is connected to a second adjustable voltage source (V) tune2 ) (ii) a Ninth N type MOS transistor (M) n9 ) Is simultaneously connected with the first N-type MOS transistor (M) n1 ) Gate of (3), eighth N-type MOS transistor (M) n8 ) Drain electrode of (1), fourth P-type MOS transistor (M) p4 ) And a fifth P-type MOS transistor (M) p5 ) The grid electrodes are connected; eighth N type MOS transistor (M) n8 ) Is connected to a first adjustable voltage source (V) tune1 ) (ii) a Eighth N type MOS transistor (M) n8 ) Source and secondSix N type MOS transistor (M) n6 ) The drain electrodes of the two electrodes are connected; second passive resistor (R) 2 ) Simultaneously with the first passive resistor (R) 1 ) Second terminal, first passive capacitor (C) 1 ) Are connected with each other; tenth P type MOS transistor (M) p10 ) Is connected to a third adjustable voltage source (V) tune3 ) (ii) a Power supply (V) DD ) Simultaneously connecting a fourth P type MOS transistor (M) p4 ) Source of (1), fifth P-type MOS transistor (M) p5 ) Source electrode of (1), first N-type MOS transistor (M) n1 ) Drain, tenth P-type MOS transistor (M) p10 ) Source electrode of (1), first passive resistor (R) 1 ) And a first passive capacitor (C) 1 ) A first end of (a); third N-type MOS transistor (M) n3 ) Source electrode of (1), sixth N type MOS transistor (M) n6 ) Source electrode of (1), seventh N type MOS transistor (M) n7 ) Are all connected with the ground terminal (GND).
The first transconductance unit (1) in the active inductance circuit is a first N-type MOS transistor (M) n1 ) Forming a negative transconductor; with a resistance (R) 1 ) And resistance (R) 2 ) -a capacitance (C) 2 ) A second N-type MOS transistor (M) of a second transconductance unit (2) with dual feedback n2 ) And a third N-type MOS transistor (M) n3 ) Are connected in series to form a positive transconductor; the positive transconductor and the negative transconductor form a first impedance conversion loop, and the impedance characteristic of the input end of the active inductor is presented as an inductive reactance characteristic. Further, a resistor (R) having a large resistance value 1 ) And resistance (R) 2 ) -a capacitance (C) 2 ) The dual feedback structure reduces the series resistance of the inductor and increases the Q value of the active inductor; on the other hand, the transistor M n2 The output impedance of the loop is increased, the impedance conversion effect of the circuit is enhanced, and the Q value of the active inductor is also improved.
Further, the first transconductance unit (1) and an eighth N-type MOS transistor (M) in the bias unit (4) are connected n8 ) Sixth N type MOS transistor (M) n6 ) And multiplexing to form a second impedance conversion loop, and connecting the first impedance conversion loop and the second impedance conversion loop in parallel, so that the impedance conversion times are increased, and the equivalent inductance value of the active inductor is increased.
Further, a second adjustable voltage source (V) is arranged between the first transconductance unit (1) and the second transconductance unit (2) with resistance and resistance-capacitance dual feedback tune2 ) A resistive loss cancellation unit (3), i.e. M n9 Operating in the linear region, equivalent to a resistance R F The real part loss of the active inductor is effectively reduced, and the Q value of the active inductor is increased. And can pass through transistor M n9 Is applied with different control voltages (V) tune2 ) Changing the equivalent resistance R F Thereby realizing the adjustment of the Q value and the inductance value.
Further, the bias unit (4) comprises a complex current mirror network (M) p4 、M p5 、M n6 、M n7 、M n8 ) From an eighth N-type MOS transistor (M) operating in saturation mode n8 ) Generating a required bias current; transistor M p4 、M p5 、M n6 、M n7 Is a current mirror, replicating an eighth N-type MOS transistor (M) n8 ) The resulting current. The main advantage of this composite current mirror structure to provide bias to the inductive circuit is the generation of multiple current branches with different amplitudes for different parts of the circuit and the elimination of the use of multiple external power supplies.
On the other hand, a tenth P-type MOS transistor (M) in the bias unit (4) p10 ) As an independent current source, is disposed in the second N-type MOS transistor (M) n2 ) And a third N-type MOS transistor (M) n3 ) In between, a third N-type MOS transistor (M) is added n3 ) Will significantly increase the total current of the transistor M n3 Transconductance g of m3 Thereby increasing the Q value; on the other hand, the Q value of the active inductor and the transistor M n2 Transconductance g of m2 Transistor M n3 Transconductance g of m3 Proportional, zero frequency (ω) 0 ) And the inductance (L) and the transistor M n3 Transconductance g of m3 Is proportional, therefore, by adjusting the first adjustable voltage source V tune1 The fifth P type MOS transistor (M) can be changed p5 ) The current supplied thereby changing the transistor M n2 Transconductance g of m2 Transistor M n3 Transconductance g of m3 (ii) a By adjusting a third adjustable voltage source V tune3 The tenth P type MOS transistor (M) can be changed p10 ) Thereby changing the bias current of the transistor M n3 Transconductance g of m3 . Co-regulating a first adjustable voltage source V tune1 And a third adjustable voltage source V tune3 Can counteract the pair g m2 、g m3 The coupling is adjusted so as to achieve independent tuning of the Q value at the same frequency and the same inductance value.
Compared with the prior art, the invention has the following advantages:
the active inductor of the invention consists of a first transconductance unit (1) with a resistor (R) 1 ) And resistance (R) 2 ) -a capacitance (C) 2 ) A second transconductance unit (2) with dual feedback and a second adjustable voltage source V tune2 And with a first adjustable voltage source V tune1 A third adjustable voltage source V tune3 The bias unit (4). The first transconductance unit (1) and the second transconductance unit (2) form a first impedance conversion loop; an eighth N-type MOS transistor (M) in the first transconductance unit (1) and the bias unit (4) n8 ) And a sixth N type MOS transistor (M) n6 ) A second impedance conversion loop is formed, and the first impedance conversion loop is connected with the second impedance conversion loop in parallel, so that the impedance conversion times of the circuit are increased, and the equivalent inductance value is increased; the resistance loss counteracting unit (3) reduces the series resistance loss of the inductor, thereby increasing the Q value of the active inductor; five transistors in the biasing unit (4) [ i.e., fourth P-type MOS transistor (M) p4 ) A fifth P type MOS transistor (M) p5 ) And a sixth N type MOS transistor (M) n6 ) Seventh N type MOS transistor (M) n7 ) And an eighth N type MOS transistor (M) n8 ) Form a composite current mirror network with an eighth N-type MOS transistor (M) n8 ) The generated current is transmitted to the transistor M p4 、M p5 、M n6 、M n7 The power supply is copied and utilized, and the use of a plurality of external power supplies is reduced; tenth P type MOS transistor (M) p10 ) Is a third N-type MOS transistor (M) n3 ) Providing additional current through a first adjustable voltage source V in the bias unit (4) tune1 The first stepThree adjustable voltage source V tune3 With a second adjustable voltage source V in the resistive loss counteracting unit (3) tune2 The mutual matching and effective coordination of the active inductors can realize the independent tuning of the Q peak value of the active inductor in the same frequency of a high-frequency area.
Drawings
Fig. 1 is a circuit topology diagram of an embodiment of an active inductor of the present invention, wherein: 1-a first transconductance unit; 2-a second transconductance unit with resistance and resistance-capacitance dual feedback; 3-resistive loss cancellation unit with one bias adjustable terminal; 4-a biasing unit with two biased adjustable ends.
FIG. 2 shows the active inductor biased at a combination (i.e., first adjustable voltage source V) tune1 =1.39V, second adjustable voltage source V tune2 =0.58V, third adjustable voltage source V tune3 = 1.75V), the variation curve of Q value and inductance L with frequency.
FIG. 3 shows the active inductors in cooperation with the first adjustable voltage source (V) tune1 ) A second adjustable voltage source (V) tune2 ) And a third adjustable voltage source (V) tune3 ) Three combined biases (i.e. V) bias1 、V bias2 、V bias3 ) A graph of Q versus frequency, wherein the first combination bias V bias1 Comprises the following steps: v tune1 ＝1.30V，V tune2 ＝0.54V，V tune3 =1.98V; second combined offset V bias2 Comprises the following steps: v tune1 ＝1.30V，V tune2 ＝0.55V，V tune3 =1.91V; third combined bias V bias3 Comprises the following steps: v tune1 ＝1.39V，V tune2 ＝0.58V，V tune3 ＝1.75V。
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described with reference to the accompanying drawings.
The active inductance circuit comprises a first transconductance unit (1), a second transconductance unit (2) with resistance and resistance-capacitance dual feedback, a resistance loss cancellation unit (3) with one bias voltage adjustable end and a bias unit (4) with two bias voltage adjustable ends.
In this embodiment of the active inductor, the first transconductance unit (1) comprises a first N-type MOS transistor (M) n1 ) (ii) a The second transconductance unit (2) with resistance and resistance-capacitance dual feedback comprises a second N-type MOS transistor (M) n2 ) A third N-type MOS transistor (M) n3 ) A first passive resistor (R) 1 ) A second passive resistor (R) 2 ) A first passive capacitor (C) 1 ) A second passive capacitor (C) 2 ) (ii) a The resistive loss cancellation unit (3) with an adjustable end for biasing comprises a voltage source with a second adjustable voltage source (V) tune2 ) Ninth N type MOS transistor (M) n9 ) (ii) a The bias unit (4) with two adjustable bias terminals comprises a fourth P-type MOS transistor (M) p4 ) And a fifth P type MOS transistor (M) p5 ) And a sixth N type MOS transistor (M) n6 ) Seventh N type MOS transistor (M) n7 ) With a first adjustable voltage source (V) tune1 ) Of the eighth N-type MOS transistor (M) n8 ) With a third adjustable voltage source (V) tune3 ) Of the tenth P type MOS transistor (M) p10 )。
The specific implementation of the circuit in this embodiment is:
input terminal (V) of the active inductor in ) Simultaneously connecting a first N-type MOS transistor (M) n1 ) Source electrode of (1), third N-type MOS transistor (M) n3 ) Gate of (d), sixth N-type MOS transistor (M) n6 ) And a seventh N-type MOS transistor (M) n7 ) A gate and a drain of (1); third N type MOS transistor (M) n3 ) With the tenth P-type MOS transistor (M) at the same time p10 ) Drain electrode of (1), second N-type MOS transistor (M) n2 ) Source electrode, second passive capacitor (C) 2 ) Are connected with each other; second N-type MOS transistor (M) n2 ) Is simultaneously connected with a second passive capacitor (C) 2 ) First terminal, second passive resistor (R) 2 ) Is connected with the second end of the first end; second N-type MOS transistor (M) n2 ) With the drain of the fifth P-type MOS transistor (M) at the same time p5 ) Drain electrode of (1), ninth N-type MOS transistor (M) n9 ) The source electrodes of the two-way transistor are connected; ninth N type MOS transistor (M) n9 ) Is connected to a second adjustable voltage source (V) tune2 ) (ii) a Ninth N-type MOS transistor(M n9 ) Is simultaneously connected with the first N-type MOS transistor (M) n1 ) Gate of (3), eighth N-type MOS transistor (M) n8 ) Drain electrode of (1), fourth P-type MOS transistor (M) p4 ) And a fifth P type MOS transistor (M) p5 ) The grid electrodes are connected; eighth N type MOS transistor (M) n8 ) Is connected to a first adjustable voltage source (V) tune1 ) (ii) a Eighth N type MOS transistor (M) n8 ) And a sixth N-type MOS transistor (M) n6 ) The drain electrodes of the two electrodes are connected; second passive resistor (R) 2 ) Simultaneously with the first passive resistor (R) 1 ) Second terminal, first passive capacitor (C) 1 ) Are connected with each other; tenth P type MOS transistor (M) p10 ) Is connected to a third adjustable voltage source (V) tune3 ) (ii) a Power supply (V) DD ) Simultaneously connecting a fourth P type MOS transistor (M) p4 ) Source of (1), fifth P-type MOS transistor (M) p5 ) Source electrode of (1), first N-type MOS transistor (M) n1 ) Of the drain, tenth P-type MOS transistor (M) p10 ) And a first passive resistor (R) 1 ) A first passive capacitor (C) 1 ) A first end of (a); third N-type MOS transistor (M) n3 ) Source electrode of (1), sixth N type MOS transistor (M) n6 ) Source electrode of (1), seventh N-type MOS transistor (M) n7 ) Are all connected with the ground terminal (GND). Finally, a high Q value and a large inductance value are obtained simultaneously by the mutual cooperation of the first transconductance unit (1), the second transconductance unit (2) with resistance and resistance-capacitance dual feedback, the resistive loss cancellation unit (3) with one bias voltage adjustable end, and the bias unit (4) with two bias voltage adjustable ends, and an external adjustable voltage source (i.e. V) by the adjustable bias unit (4) with two bias voltage adjustable ends and the resistive loss cancellation unit (3) with one bias voltage adjustable end tune1 、V tune2 And V tune3 ) The combined cooperative tuning of the active inductor can independently adjust the Q peak value of the active inductor under the same frequency in a high-frequency region.
Fig. 2 shows the active inductor biased at a combination (i.e. first adjustable voltage source V) tune1 =1.39V, second adjustable voltage source V tune2 =0.58V, third adjustable voltage source V tune3 = 1.75V), Q value versus inductance value L versus frequency. It can be seen that at high frequencies (6.68 GHz to 9.56 GHz), the inductance ranged from 15 to 29nH and the Q ranged from 39 to 6408, while large inductance and Q values were obtained. Wherein the active inductor has both an inductance value of 15nH and a Q value of 6408 at a high frequency point of 6.68GHz, these results show that the active inductor can have both a large inductance value and a high Q value at a wide frequency band range of a high frequency region.
FIG. 3 shows the active inductors in combination with a co-tuned first adjustable voltage source (V) tune1 ) A second adjustable voltage source (V) tune2 ) And a third adjustable voltage source (V) tune3 ) Three combined biases (i.e. V) bias1 、V bias2 、V bias3 ) A graph of Q versus frequency, wherein the first combination bias V bias1 Comprises the following steps: v tune1 ＝1.30V，V tune2 ＝0.54V，V tune3 =1.98V; second combined offset V bias2 Comprises the following steps: v tune1 ＝1.30V，V tune2 ＝0.55V，V tune3 =1.91V; third combined bias V bias3 Comprises the following steps: v tune1 ＝1.39V，V tune2 ＝0.58V，V tune3 =1.75V. It can be seen that the Q value reaches a maximum at a high frequency of 6.68GHz under all three combined biases, and the Q peak can be adjusted from 2021 to 6408, indicating that the active inductor can tune the Q peak at the same frequency.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (1)
1. Active inductance that big inductance value high Q value and Q peak value can independently be adjusted under same frequency under high frequency, its characterized in that includes: the circuit comprises a first transconductance unit (1), a second transconductance unit (2) with resistance and resistance-capacitance dual feedback, a resistance loss cancellation unit (3) with a bias voltage adjustable end and a bias unit (4) with two bias voltage adjustable ends;
wherein: the first transconductance unit (1) in the active inductance circuit comprises a first N-type MOS transistor (M) n1 ) (ii) a The second transconductance unit (2) with resistance and resistance-capacitance dual feedback comprises a second N-type MOS transistor (M) n2 ) A third N-type MOS transistor (M) n3 ) A first passive resistor (R) 1 ) A second passive resistor (R) 2 ) A first passive capacitor (C) 1 ) A second passive capacitor (C) 2 ) (ii) a The resistive loss cancellation unit (3) with an adjustable end for biasing comprises a voltage source with a second adjustable voltage source (V) tune2 ) Ninth N type MOS transistor (M) n9 ) (ii) a The bias unit (4) with two adjustable bias terminals comprises a fourth P-type MOS transistor (M) p4 ) A fifth P type MOS transistor (M) p5 ) And a sixth N type MOS transistor (M) n6 ) And seventh N type MOS transistor (M) n7 ) With a first adjustable voltage source (V) tune1 ) Of the eighth N-type MOS transistor (M) n8 ) With a third adjustable voltage source (V) tune3 ) Of the tenth P-type MOS transistor (M) p10 )；
Wherein: input terminal (V) of the active inductor in ) Simultaneously connecting a first N-type MOS transistor (M) n1 ) Source electrode of (1), third N-type MOS transistor (M) n3 ) Gate of (d), sixth N-type MOS transistor (M) n6 ) And a seventh N-type MOS transistor (M) n7 ) A gate and a drain of (1); third N-type MOS transistor (M) n3 ) With the tenth P-type MOS transistor (M) at the same time p10 ) Drain electrode of (1), second N-type MOS transistor (M) n2 ) Source electrode, second passive capacitor (C) 2 ) Are connected with each other; second N-type MOS transistor (M) n2 ) Is simultaneously connected with a second passive capacitor (C) 2 ) First terminal, second passive resistor (R) 2 ) Is connected with the second end of the first end; second N-type MOS transistor (M) n2 ) With the drain of the fifth P-type MOS transistor (M) at the same time p5 ) A ninth N-type MOS transistor (M) n9 ) Source phase ofConnecting; ninth N type MOS transistor (M) n9 ) Is connected to a second adjustable voltage source (V) tune2 ) (ii) a Ninth N type MOS transistor (M) n9 ) Is simultaneously connected with the first N-type MOS transistor (M) n1 ) Gate of (3), eighth N-type MOS transistor (M) n8 ) Drain of (1), fourth P-type MOS transistor (M) p4 ) And a gate and a drain of the fifth P-type MOS transistor (M) p5 ) The grid electrodes of the grid electrodes are connected; eighth N type MOS transistor (M) n8 ) Is connected to a first adjustable voltage source (V) tune1 ) (ii) a Eighth N type MOS transistor (M) n8 ) And a sixth N-type MOS transistor (M) n6 ) The drain electrodes of the two electrodes are connected; second passive resistor (R) 2 ) Simultaneously with the first passive resistor (R) 1 ) Second terminal, first passive capacitor (C) 1 ) Is connected with the second end of the first end; tenth P type MOS transistor (M) p10 ) Is connected to a third adjustable voltage source (V) tune3 ) (ii) a Power supply (V) DD ) Simultaneously connecting a fourth P-type MOS transistor (M) p4 ) Source of (1), fifth P-type MOS transistor (M) p5 ) Source electrode of (1), first N-type MOS transistor (M) n1 ) Drain of (1), tenth P-type MOS transistor (M) p10 ) Source electrode, first passive resistor (R) 1 ) And a first passive capacitor (C) 1 ) A first end of (a); third N type MOS transistor (M) n3 ) Source electrode of (1), sixth N type MOS transistor (M) n6 ) Source electrode of (1), seventh N-type MOS transistor (M) n7 ) Are all connected with the ground terminal (GND).
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| US7042317B2 (en) * | 2003-09-08 | 2006-05-09 | State Of Oregon, Acting By And Through The Board Of Higher Education On Behalf Of Portland State University | High-frequency active inductor |
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| CN103475357A (en) * | 2013-08-31 | 2013-12-25 | 西安电子科技大学 | Semi-active on-chip inductor based on active inductor |
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