JPH08273385A - Program memory - Google Patents

Abstract

PURPOSE: To provide a program memory in which the memory cell can serve both as a memory for reading/writing the data and as a read only memory by connecting/disconnecting the output side end of a first MOS transistor and a third MOS transistor selectively. CONSTITUTION: At first, a joint A is connected through a conductor with a mask and a joint B is disconnected. In this regard, a memory cell 8 functions as a nonvolatile memory which can read/write a data. When the joint A is disconnected and the joint B is connected through a conductor with the mask, the program memory functions as the memory cell in a mask ROM which outputs 0 upon accessing an address.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to program memories.

[0002]

2. Description of the Related Art A one-chip microcomputer for mass production has a mask ROM in which program data is stored inside the chip. When manufacturing a mass-produced one-chip microcomputer, it is necessary to burn a MOS transistor to that effect with a mask so that desired program data can be read into the ROM area on the chip. At this time, however, there is an error in the program data. The prerequisite is that there is not even one.

Therefore, at present, as a means for judging the correctness of the program data before the ROM is burned on the chip with a mask, a nonvolatile memory such as an EPROM capable of writing and reading the program data as many times as necessary is incorporated. The chip microcomputer is being developed as a model having the same function as the mass-production 1-chip microcomputer. Then, the program developer writes the considered program into the EPROM of the above-described EPROM-embedded 1-chip microcomputer, checks the normal operation by operating the 1-chip microcomputer in this state, and confirms normal operation. After the confirmation, the program is burned into the mask ROM of the mass-production 1-chip microcomputer to prevent the program from being erroneously masked.

[0004]

[Problems to be Solved by the Invention] However, EPR
Since the structures of the OM and the mask ROM are different, the peripheral circuits inevitably also differ within one chip. That is, before manufacturing a mass-produced one-chip microcomputer, EPs having the same function but different structures are manufactured.
A one-chip microcomputer with a built-in ROM must also be developed, and there is a problem that the development period becomes long.

In view of this, the present invention provides a program memory having the same structure and capable of freely selecting a non-volatile memory capable of writing and reading and a non-volatile memory dedicated to reading in the same chip by mask wiring. To aim.

[0006]

The present invention has been made to solve the above-mentioned problems, and is characterized in that a first MOS transistor having a floating gate and the first MOS transistor are provided. A memory cell composed of a second MOS transistor connected in series with one output side of the MOS transistor and an output side of the first MOS transistor connected in series with the other output side of the first MOS transistor. A third MOS transistor that precharges the other end to a predetermined potential; and a short-circuit line that short-circuits the first MOS transistor. The other end on the output side of the first MOS transistor and the third transistor A nonvolatile memory capable of writing / reading data to / from the memory cell by selectively connecting or disconnecting the connection line and the short-circuit line. It is that it also serves as a memory cell of the memory or read-only non-volatile memory.

[0007]

According to the present invention, it is possible to write / read data to / from a memory cell by connecting the connection line between the other output side of the first MOS transistor and the third MOS transistor and cutting off the short-circuit line. Can be used as a memory cell of a non-volatile memory, in which the connection line between the other output side of the first MOS transistor and the third MOS transistor is cut off and the short-circuit line is cut off, or the first MOS transistor
By disconnecting the connection line between the other end on the output side of the transistor and the third MOS transistor and connecting the short-circuit line, the memory cell can be used as a memory cell of a read-only nonvolatile memory.

[0008]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a diagram showing a program memory of the present invention.
In FIG. 1, (1) is a first MOS transistor having a floating gate, which functions as a 1-bit memory cell of a nonvolatile memory in which writing and reading can be repeated depending on whether or not electric charge is stored in the floating gate. It is a thing. Specifically, the first MOS
Storage of charges in the floating gate of the transistor (1) is performed as shown in FIG. That is, the first MOS
When the charge is stored in the floating gate (2) of the transistor (1), the voltage V1 (for example, 12
Voltage), a voltage V2 (for example, 0.7 V) is applied to the drain (4), and a voltage V3 is applied to the gate (5).
(For example, 2 volts) is applied. Then, the gate (5)
Is positively charged and a large potential difference of 11.3 V is generated between the source (3) and the drain (4), a negative charge is generated between the source and the drain, and the source (3) is drained (4). An electric current flows. At this time, a charge called hot electron is generated between the source and drain according to a large potential difference, and this charge is generated in the insulating film (6).
That is, the negative charge is stored in the floating gate (2) via the above, that is, the floating gate (2) stores negative charges. In this way, even if a constant potential difference is applied between the gate (5) and the source (3) in order to make the first MOS transistor (1) storing negative charges in the floating gate (2) conductive, the floating gate (2) ) Is negatively charged, only the current path near the floating gate (2) between the source and drain is positively charged, and no current flows between the source and drain. On the other hand, when no charge is stored in the floating gate (2) of the first MOS transistor (1), the voltage V2 applied to the drain (4) is set to 0.7.
Increase from bolt to 4 volts. As a result, the potential difference between the drain and the source becomes 8 V, the hot electrons are not generated, and the floating gate (2) is not negatively charged. Therefore, the first MO in which the floating gate (2) is not negatively charged
Gate (5) and source (3) of S-transistor (1)
When a constant potential for conduction is applied between the gate (5) and the floating gate (2), a negative charge is charged between the source and drain,
As a result, conduction is established between the source and drain. First mentioned above
The characteristics of the MOS transistor (1) are used for the memory cell. A first MOS transistor (1) with or without electric charges stored in the floating gate is provided as a part of the memory cell (8) in FIG. (7) is an N-channel type second M
The OS transistor is connected in series with the first MOS transistor (1) and the source is grounded. A memory cell (8) for one bit of the non-volatile memory is constituted by these first and second MOS transistors (1) and (7). That is, the memory cells (8) are provided by the number of bits required for the non-volatile memory. When accessing an address in which a predetermined memory cell (8) is arranged, a voltage for reading is applied to the gates of the first and second MOS transistors (1) and (7) based on the result of decoding the address data. Should be applied.

(9) is a first MOS transistor (1)
Is a P-channel type third MOS transistor for precharging the drain side of the transistor to the voltage Vdd, and is connected in series with the first MOS transistor (1) via the connection point A. (10) is a P-channel type MOS transistor, which is connected in parallel with the third MOS transistor (9). (11) is an inverter, a MOS
It is connected between the gate and drain of the transistor (10). The precharge voltage is held by the closed loop of the MOS transistor (10) and the inverter (11). The third MOS transistor (9) becomes conductive before the voltage based on the address data is applied to the gates of the first and second MOS transistors (1) and (7), and the third MOS transistor (9) is turned on. The drain side is precharged to the voltage Vdd. Reference numeral (12) is a short-circuit line that short-circuits the drain-source path of the first MOS transistor (1) and is provided with a connection point B. Here, the connection points A and B are initially in a state where the wirings are separated on the semiconductor integrated circuit, and are connected or not connected depending on whether or not a conductor such as aluminum is masked here. As described above, the mask can be switched.

The case where the connection points A and B are selectively connected or disconnected will be described below. First, the connection point A is connected with a mask using a conductor such as aluminum, and the connection point B is left in a separated state. In this case, the memory cell (8) functions as a non-volatile memory (for example, EPROM, EEPROM, etc.) capable of writing and reading data. For example, when charges are stored in the floating gate of the first MOS transistor (1), in order to read the data of the memory cell (8), the first and second MOS transistors (1 ) When a voltage is applied to the gates of (7) to make both the transistors (1) and (7) conductive, the first MOS transistor (1) cannot be turned on, so that a high level (logic “1” is output as output data). Output, on the contrary, the first M
When electric charges are not stored in the floating gate of the OS transistor (1), when a voltage for conduction is applied to the gates of the first and second MOS transistors (1) and (7), both transistors (1) (7) is turned on, and a low level (logic “0”) is output as output data. That is, data corresponding to the state of the floating gate of the first MOS transistor (1) is output.

When the connection point A is kept in a separated state and the connection point B is connected by a mask using a conductor such as aluminum, a mask ROM of "0" is output when an address is accessed. Functions as a memory cell. Specifically, according to the result of decoding the address data, the second MOS
When a voltage for reading is applied to the gate of the transistor (7), the transistor (7) is turned on and the output data becomes "0". On the other hand, if the connection points A and B are left in the separated state, they function as the memory cells of the mask ROM that outputs "1" when the address is accessed. Specifically, according to the result of decoding the address data, the second M
When a voltage for reading is applied to the gate of the OS transistor (7), the transistor (7) turns on,
Since the connection point B is in the non-connection state, the output data is "1".

From the above, it is possible to write and read the memory cell (8) by selectively connecting or disconnecting the connection points A and B even though they have the same structure in the same chip. It can be used as a memory cell of a non-volatile memory or a read-only non-volatile memory. Incidentally, recently, the diameter of the wiring on the chip (micron rule) also tends to be miniaturized, and even if both the first and second MOS transistors (1) and (7) are provided, the area occupied by the program memory is small. There is no special increase in size.

[0013]

According to the present invention, a memory cell can be formed by selectively connecting or disconnecting a connection line between the other output side of the first MOS transistor and the third transistor and a short-circuit line. Since it can also be used as a memory cell of a non-volatile memory that can write and read data or a read-only non-volatile memory, when manufacturing a one-chip microcomputer with a built-in mask ROM for mass production, it has an EPROM for evaluation. There is no need to individually develop each one-chip microcomputer, which has the advantage of shortening the development period.

[Brief description of drawings]

FIG. 1 is a diagram showing a program memory of the present invention.

FIG. 2 is a diagram showing a fault of a first MOS transistor.

[Explanation of symbols]

 (1) First MOS transistor (7) Second MOS transistor (9) Third MOS transistor (12) Short-circuit line

Claims (5)

[Claims] 1. A first M having a floating gate.
A memory cell including an OS transistor and a second MOS transistor connected in series with one output side end of the first MOS transistor; and a memory cell connected in series with the other output side end of the first MOS transistor, A third MOS transistor that precharges the other output side of the first MOS transistor to a predetermined potential; and a short-circuit line that short-circuits the first MOS transistor, and the other output side of the first MOS transistor Edge and the third
By selectively connecting or disconnecting a connection line with a transistor and the short-circuit line, the memory cell is also used as a memory cell of a nonvolatile memory capable of writing / reading data or a read-only nonvolatile memory. Program memory characterized by being able to do. 2. The memory cell is written and read with data by connecting a connection line between the other output side of the first MOS transistor and the third MOS transistor and cutting off the short-circuit line. 2. The program memory according to claim 1, wherein the program memory can be used as a memory cell of a non-volatile memory capable of performing the above. 3. A state in which a connection line between the other output side of the first MOS transistor and the third MOS transistor is cut off and the short-circuit line is cut off, or the first short circuit is cut off.
The other end of the output side of the MOS transistor and the third MOS
The program according to claim 1, wherein the memory cell can be used as a memory cell of a read-only nonvolatile memory by disconnecting a connection line with a transistor and connecting the short-circuit line. memory. 4. The output line other end of the first MOS transistor, the connection line of the third MOS transistor, and the short-circuit line are disconnected on an integrated circuit,
2. The program memory according to claim 1, wherein the connection line and the short-circuit line are brought into a connected state by providing a conductor with a mask in the disconnection portion. 5. The program memory according to claim 1, wherein the writable and readable nonvolatile memory is an EPROM or an EEPROM, and the read-only nonvolatile memory is a mask ROM.