JP2007172814A - Semiconductor device and its operating method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing an area of the semiconductor device, reading data reliably, and simplifying replacement of data. <P>SOLUTION: In the semiconductor device, a memory cell and a data line are controlled with a reset signal so that data can be reliably outputted. Also, an element of data holding unit is included, and the data holding unit includes a plurality of memory cells. The area can be reduced by using such a memory cell. A transistor is not connected to GND, thereby simplifying the replacement of data in the memory cell. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a semiconductor device having a storage area and a method for operating the device.

With the development of computer technology, a large amount of memory is required. In order to increase the capacity of the memory, the number of memory cells may be increased. However, when the number of memory cells is increased, the area increases, and there is a limit to downsizing the memory and the computer having the memory.

Such memories include RAM (Random Access Memory) and ROM (Read Only Memory). The RAM is a rewritable memory, and the ROM is a readable only memory.

RAMs and ROMs have word lines and data lines, and memory cells are formed at intersections thereof. Predetermined information can be created according to the binary state (0 and 1) of the memory cell.

Regarding the ROM, a configuration of a multi-value mask ROM has been proposed in which the number of revision masks is small and the degree of integration is improved, so that the potential control of the word line at the time of reading is simplified (see Patent Document 1).

In order to reduce current consumption when selecting a word line, a data holding means and a power supply control means are provided, and the data holding means has a ROM structure having a plurality of memory cells (see Patent Document 2). .
JP 2000-299394 A JP 2005-203079 A

In the ROM configurations described in Patent Documents 1 and 2, a plurality of wirings are provided for one memory cell. Such wiring greatly affects the integration density of the ROM. The degree of wiring integration depends on the exposure technique, and there is a limit to narrowing the wiring width and the wiring interval (line and space). Accordingly, an object of the present invention is to reduce the number of wirings in the memory cell portion and realize space saving.

Further, precharge is required for the operation of the ROM. Therefore, an object of the present invention is to enable reliable data reading by inputting a reset signal to a precharge circuit and a word line.

The ROM data is diverse and can be changed frequently. In order to change the data, it is necessary to change the mask from the exposure mask for the wiring, which is expensive. Therefore, an object of the present invention is to change data with a minimum mask change when changing data.

In view of the above problems, the present invention includes a memory cell, a precharge circuit connected through a data line, and a sense amplifier circuit, and the word line and the data line are controlled by a reset signal. It is a semiconductor device.

Further, the transistor of the memory cell may be disconnected without being connected to GND. As a result, at the time of data rewriting, either the contact mask or the wiring mask can be easily changed. Such a memory cell includes a word line, a data line, a GND line, and one transistor.

Specific examples of the present invention will be described below.

One embodiment of the present invention is a semiconductor device including a memory cell, a precharge circuit, and a sense amplifier circuit that are electrically connected to each other through a data line. The memory cell includes a first transistor in which one electrode is electrically connected to the data line. The precharge circuit includes a second transistor in which one electrode is electrically connected to the data line. The sense amplifier circuit includes a third transistor having one electrode connected to the data line, an input terminal electrically connected to the data line, and an output terminal electrically connected to the gate of the third transistor. And a connected inverter.

Another embodiment of the present invention is a semiconductor device including a memory cell, a precharge circuit, and a sense amplifier circuit that are electrically connected to each other through a data line. The memory cell includes a first transistor having one electrode electrically connected to the data line and a word line. The precharge circuit includes a second transistor in which one electrode is electrically connected to the data line. The sense amplifier circuit includes a third transistor having one electrode electrically connected to the data line, an input terminal electrically connected to the data line, and an output terminal to the gate of the third transistor. The word line is electrically connected to the gate of the first transistor.

Another embodiment of the present invention is a semiconductor device including a memory cell, a precharge circuit, a sense amplifier circuit, a first inverter, and a NAND that are electrically connected to each other through a data line. The memory cell includes a first transistor having one electrode electrically connected to the data line and a word line. The precharge circuit includes a second transistor in which one electrode is electrically connected to the data line. The sense amplifier circuit includes a third transistor having one electrode electrically connected to the data line, an input terminal electrically connected to the data line, and an output terminal to the gate of the third transistor. A second inverter electrically connected, the word line is electrically connected to the gate of the first transistor, and the first inverter and the NAND are electrically connected to the word line.

Another embodiment of the present invention is a semiconductor device including a memory cell, a precharge circuit, a sense amplifier circuit, a first inverter, and a NAND that are electrically connected to each other through a data line. The memory cell includes a first transistor having one electrode electrically connected to the data line and a word line. The precharge circuit includes a second transistor in which one electrode is electrically connected to the data line. The sense amplifier circuit includes a third transistor having one electrode electrically connected to the data line, an input terminal electrically connected to the data line, and an output terminal to the gate of the third transistor. A second inverter electrically connected, the word line is electrically connected to the gate of the first transistor, and the first inverter and the NAND are electrically connected to the word line. An address signal and a reset signal are input to the NAND.

In the present invention, the potential of the other electrode of the first transistor is a ground potential. Specifically, the other electrode of the first transistor is electrically connected to the wiring and has a ground potential. Alternatively, the other electrode of the first transistor is not connected.

In the present invention, the potential of the other electrode of the second transistor is a high potential side potential. The potential of the other electrode of the third transistor is a high potential side potential.

In the present invention, the first transistor is N-type, the second transistor is P-type, and the third transistor is P-type.

One embodiment of a method for operating a semiconductor device according to the present invention includes a memory cell electrically connected via a data line, a precharge circuit, a sense amplifier circuit, an inverter electrically connected to the memory cell, and It has a NAND, a low signal is input to the precharge circuit and the NAND as a reset signal, a high signal is input to the NAND as an address signal, and a high signal is input to the data line The transistor included in the precharge circuit is turned on, the transistor included in the memory cell is turned off, and a high signal is output from the data line.

Another embodiment of the semiconductor device operating method of the present invention includes a memory cell electrically connected via a data line, a precharge circuit, a sense amplifier circuit, an inverter electrically connected to the memory cell, and If a NAND has a precharge circuit as a reset signal, a low signal is input to the NAND, a low signal is input to the NAND as an address signal, and a high signal is input to the data line, the precharge circuit The transistor included in the memory cell is turned on, the transistor included in the memory cell is turned off, and a high signal is output from the data line.

Another embodiment of the semiconductor device operating method of the present invention includes a memory cell electrically connected via a data line, a precharge circuit, a sense amplifier circuit, an inverter electrically connected to the memory cell, and If a NAND has a precharge circuit as a reset signal, a high signal is input to the NAND, a high signal is input to the NAND as an address signal, and a low signal is input to the data line, the precharge circuit The transistor included in the memory cell is turned off, the transistor included in the memory cell is turned on, and a low signal is output from the data line.

Another embodiment of the semiconductor device operating method of the present invention includes a memory cell electrically connected via a data line, a precharge circuit, a sense amplifier circuit, an inverter electrically connected to the memory cell, and If a NAND has a precharge circuit as a reset signal, a high signal is input to the NAND, a low signal is input to the NAND as an address signal, and a low signal is input to the data line, the precharge circuit The transistor included in the memory cell is turned off, the transistor included in the memory cell is turned off, and a low signal is output from the data line.

By controlling the word line and data line with the reset signal, reliable data output is possible.

In addition, the memory cell includes a single transistor connected to the word line, the data line, and the GND line, so that space saving can be realized. With the memory cell that realizes space saving, it is possible to increase the number of acquisitions and to realize a low price.

In the memory cell, when the transistor is not connected to GND, the data mask can be easily changed by either the contact mask or the wiring mask.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in all the drawings for describing the embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

(Embodiment 1)
In this embodiment, a structure and operation of a semiconductor device including memory cells and the like are described.

FIG. 1 shows a memory cell 10, a precharge circuit 11 and a sense amplifier circuit 12 connected to the memory cell 10 via a data line 15. The memory cell 10 has an N-type transistor (Tr1), and the gate electrode of the transistor (Tr1) is connected to the word line 16. An inverter (INV1) and a NAND are connected in series to the word line 16, and an address signal (address) and a reset signal (reset) are input to the input terminals of the NAND, respectively. A signal based on the address signal and the reset signal is output from the output terminal of the NAND, and this signal is inverted by INV1. The inverted signal, that is, the inverted signal is input to the gate of the transistor (Tr1). The present invention is not limited to the combination of NAND and INV1, as long as the signal based on the address signal and the reset signal can be inverted and input to the gate of the transistor (Tr1). For example, a circuit in which two INVs and one NOR are combined can be used. One electrode of the transistor (Tr1) is connected to the data line 15, and the other electrode is grounded (GND connection). That is, the other electrode is at ground potential. The wiring grounded in this way is referred to as a GND line 20.

The precharge circuit 11 connected to the memory cell 10 via the data line 15 has a P-type transistor (Tr2). One electrode of the transistor (Tr2) is connected to the data line 15, and the other electrode is set to VDD (high potential side potential). A reset signal is input to the gate of the transistor (Tr2).

The sense amplifier circuit 12 connected to the memory cell 10 via the data line 15 includes a P-type transistor (Tr3) and an inverter (INV2). One electrode of the transistor (Tr3) is connected to the data line 15, and the other electrode has a VDD potential. The gate of the transistor (Tr3) is connected to the output terminal of the inverter (INV2), and the input terminal is connected to the data line 15.

The operation in such a circuit will be described. First, an operation in which a low state (0) signal is output to the data line 15 will be described. In FIG. 1, in order to output low (0) to the data line, the transistor (Tr1) of the memory cell 10 is connected to GND.

FIG. 3 shows a timing chart. A series of operations will be described separately for period 1, period 2, period 3, and period 4.

In period 1, the low state (0) is input to the input terminal B of the NAND as a reset signal. Further, a high state (1) is input to the input terminal A of the NAND as an address signal. Therefore, the NAND outputs a high state (1). The output in the high state (1) goes to the low state (0) via INV1 (this is referred to as a NANDb signal). The NANDb signal is input to the gate of the transistor (Tr1) of the memory cell 10, and the transistor (Tr1) is turned off. At the same time, the low state (0) of the reset signal is input to the gate of the transistor (Tr2) of the precharge circuit 11, and the transistor (Tr2) of the precharge circuit 11 is turned on to output high (1). . Thus, the data line is in a high state (1), and the output of data (data) is in a high state (1).

In period 2, a low state (0) is input to the input terminal B of the NAND as a reset signal. Further, the low state (0) is input to the input terminal A of the NAND as an address signal. Therefore, the NAND outputs a high state (1). The output in the high state (1) goes to the low state (0) via the INV1 (NANDb signal). The NANDb signal is input to the gate of the transistor (Tr1) of the memory cell 10, and the transistor (Tr1) is turned off. At the same time, the low state (0) of the reset signal is input to the gate of the transistor (Tr2) of the precharging circuit 11, the transistor (Tr2) of the precharging circuit 11 is turned on, and the high state (1) is output. To do. As a result, the data line 15 is in the high state (1), and the output of the data (data) is in the high state (1).

In the period 3, the high state (1) is input to the input terminal B of the NAND as a reset signal. Further, a high state (1) is input to the input terminal A of the NAND as an address signal. Therefore, the NAND outputs a low state (0). The output in the low state (0) goes to the high state (1) via the INV1 (NANDb signal). The NANDb signal is input to the gate of the transistor (Tr1) of the memory cell 10, and the transistor (Tr1) is turned on. Then, the data line 15 is in a low state (0). At the same time, the high state (1) of the reset signal is input to the gate of the transistor (Tr2) of the precharge circuit 11, and the transistor (Tr2) of the precharge circuit 11 is turned off. As a result, the data line 15 becomes the low state (0), and the output of the data (data) becomes the low state (0).

In the period 4, the high state (1) is input to the input terminal B of the NAND as a reset signal. Further, the low state (0) is input to the input terminal A of the NAND as an address signal. Therefore, the NAND outputs a high state (1). The output in the high state (1) goes to the low state (0) via the INV1 (NANDb signal). The NANDb signal is input to the gate of the transistor (Tr1) of the memory cell 10, and the transistor (Tr1) is turned off. At the same time, the high state (1) of the reset signal is input to the gate of the transistor (Tr2) of the precharge circuit 11, and the transistor (Tr2) of the precharge circuit 11 is turned off. Since the data line 15 was in the low (0) state in the period 3 that is the state before the period 4, the data line 15 is in the low state (0) even in the period 4, and the output of the data (data) is in the low state (0 )

The memory cell of this embodiment can reliably output data by controlling the word line and the data line with a reset signal.

In addition, the memory cell includes a single transistor connected to the word line, the data line, and the GND line, so that space saving can be realized. As a result, the low cost of the memory cell and the device having the memory cell can be realized.

(Embodiment 2)
In this embodiment, a structure and operation of a semiconductor device having memory cells and the like which are different from those in the above embodiment will be described.

FIG. 2 shows a memory cell 10, a precharge circuit 11 and a sense amplifier circuit 12 connected via a data line 15. The difference between the structures of FIGS. 1 and 2 is that the transistor (Tr1) of the memory cell 10 is not GND-connected and is not connected. In this manner, by disconnecting the transistor (Tr1) in the memory cell, data can be changed by either the contact mask or the wiring mask at the time of data rewriting of the memory cell. In this way, the data in the memory cell can be rewritten by a simple process. Since other configurations are the same, description thereof is omitted.

FIG. 4 shows a timing chart. A series of operations will be described separately for period 5, period 6, period 7, and period 8.

In the period 5, the low state (0) is input to the input terminal B of the NAND as the reset signal. Further, a high state (1) is input to the input terminal A of the NAND as an address signal. Therefore, the NAND outputs a high state (1). The output in the high state (1) goes to the low state (0) via the INV1 (NANDb signal). The NANDb signal is input to the gate of the transistor (Tr1) of the memory cell 10, and the transistor (Tr1) is only connected to the word line 16 and the data line 15, and is turned off. At the same time, the low state (0) of the reset signal is input to the gate of the transistor (Tr2) of the precharging circuit 11, the transistor (Tr2) of the precharging circuit 11 is turned on, and the high state (1) is output. To do. As a result, the data line is in the high state (1), and the output of the data (data) is in the high state (1).

In period 6, a low state (0) is input to the input terminal B of the NAND as a reset signal. Further, the low state (0) is input to the input terminal A of the NAND as an address signal. Therefore, the NAND outputs a high state (1). The output in the high state (1) goes to the low state (0) via the INV1 (NANDb signal). The NANDb signal is input to the gate of the transistor (Tr1) of the memory cell 10, and the transistor (Tr1) is only connected to the word line and the data line, and is turned off. At the same time, the low state (0) of the reset signal is input to the gate of the transistor (Tr2) of the precharging circuit 11, the transistor (Tr2) of the precharging circuit 11 is turned on, and the high state (1) is output. To do. As a result, the data line 15 is in the high state (1), and the output of the data (data) is in the high state (1).

In the period 7, the high state (1) is also input to the input terminal B of the NAND as a reset signal. Further, a high state (1) is input to the input terminal A of the NAND as an address signal. Therefore, the NAND outputs a low state (0). The output in the low state (0) goes to the high state (1) via the INV1 (NANDb signal). The NANDb signal is input to the gate of the transistor (Tr1) of the memory cell 10, and the transistor (Tr1) is only connected to the word line and the data line, and is turned off. At the same time, the high state (1) of the reset signal is input to the gate of the transistor (Tr2) of the precharge circuit 11, and the transistor (Tr2) of the precharge circuit 11 is turned off. In the period 6 which is the state before the period 7, the data line 15 is in the high state (1) and the high state (1) is held by the sense amplifier circuit 12, so the data line 15 is also in the period 7. In the state (1), the output of the data (data) is in the high state (1).

In the period 8, the high state (1) is input to the input terminal B of the NAND as a reset signal. Further, the low state (0) is input to the input terminal A of the NAND as an address signal. Therefore, the NAND outputs a high state (1). The output in the high state (1) goes to the low state (0) via the INV1 (NANDb signal). The NANDb signal is input to the gate of the transistor (Tr1) of the memory cell 10, and the transistor (Tr1) is only connected to the word line and the data line, and is turned off. At the same time, the high state (1) of the reset signal is input to the gate of the transistor (Tr2) of the precharge circuit 11, and the transistor (Tr2) of the precharge circuit 11 is turned off. Since the data line 15 is in the high state (1) in the period 7 which is the state before the period 8 and the high state (1) is held by the sense amplifier circuit 12, the data line 15 is in the high state even in the period 8. (1), and the output of data (data) is in a high state (1).

The memory cell of this embodiment can reliably output data by controlling the word line and the data line with a reset signal.

In addition, the memory cell includes a single transistor connected to the word line, the data line, and the GND line, so that space saving can be realized. As a result, the low cost of the memory cell and the device having the memory cell can be realized.

Furthermore, ROM data is diverse and can be changed frequently. To change the data, it is necessary to change the mask from the exposure mask of the wiring, which is expensive. However, as in the present embodiment, the data is determined depending on whether or not the transistor of the memory cell is connected to GND. For recognition, data can be changed by changing one contact mask or one wiring mask.

(Embodiment 3)
In this embodiment mode, a wireless chip including a semiconductor device having memory cells is described as a structural example of the semiconductor device of the present invention. A method for manufacturing a wireless chip is described below.

5A, a peeling layer 601, an insulating layer 602, and a semiconductor film 603 are formed in this order over a substrate 600 having an insulating surface (hereinafter referred to as an insulating substrate). As the insulating substrate 600, a glass substrate, a quartz substrate, a substrate made of silicon, a metal substrate, a plastic substrate, or the like can be used. The insulating substrate 600 may be thinned by polishing. By using a thin insulating substrate, the finished product can be reduced in weight and thickness.

The peeling layer 601 is mainly composed of an element selected from W, Ti, Ta, Mo, Nb, Nd, Ni, Co, Zr, Zn, Ru, Rh, Pd, Os, Ir, and Si. It can be formed from an alloy material or a compound material. For the separation layer, a single-layer structure of the above elements or a stacked structure of the above elements can be used. Such a release layer can be formed by a CVD method, a sputtering method, an electron beam, or the like. In this embodiment mode, W is used, and it is formed by a CVD method. At this time, the treatment may be performed with plasma using O ₂ , N _2, or N ₂ O. Then, the peeling process which is a subsequent process can be easily performed. The separation layer 601 can have a single-layer structure or a stacked structure. The peeling layer 601 is not necessarily formed over the entire insulating substrate, and may be selectively formed. That is, the peeling layer 601 only needs to be able to peel off the insulating substrate 600 later, and the region where the peeling layer is formed is not limited.

For the insulating layer 602, an inorganic material such as silicon oxide or silicon nitride can be used. The insulating layer 602 can have a single-layer structure or a stacked structure. By using silicon nitride, entry of an impurity element from the insulating substrate can be prevented. When such a silicon nitride has a laminated structure, it has an effect by being in any one.

For the semiconductor film 603, a material containing silicon can be used. The semiconductor film can be formed by a CVD method or a sputtering method. The crystal structure of the semiconductor film 603 may be amorphous, crystalline, or microcrystalline. Higher crystallinity is preferable because the mobility of the thin film transistor can be increased. In addition, microcrystalline or amorphous is preferable because there is no variation in crystal state between adjacent semiconductor films.

In order to form a crystalline semiconductor film, it may be formed directly on the insulating layer 602, but it is manufactured by heating an amorphous semiconductor film formed on the insulating layer 602. For example, the amorphous semiconductor film is heated by a heating furnace and laser irradiation. As a result, a highly crystalline semiconductor film can be formed. At this time, a metal element that promotes crystallization may be used to lower the heating temperature. For example, the temperature can be lowered by adding nickel (Ni) to the surface of the amorphous semiconductor film and performing heat treatment. As a result, a crystalline semiconductor film can be formed over an insulating substrate with low heat resistance. Note that when laser irradiation is used, the heat resistance of the insulating substrate to be used is not limited because the semiconductor film can be selectively heated.

As shown in FIG. 5B, the semiconductor film 603 is processed to have a predetermined shape. For the processing, etching using a mask formed by a photolithography method can be used. For the etching, a dry etching method or a wet etching method can be used.

An insulating layer functioning as the gate insulating film 604 is formed so as to cover the processed semiconductor film. The gate insulating film 604 can be formed using an inorganic material, for example, silicon nitride or silicon oxide. Plasma treatment may be performed before or after the gate insulating film 604 is formed. For the plasma treatment, oxygen plasma or hydrogen plasma can be used. By such plasma treatment, impurities on the gate insulating film formation surface or the gate insulating film surface can be removed.

After that, a conductive layer functioning as the gate electrode 605 is formed over the semiconductor film with the gate insulating film 604 interposed therebetween. The gate electrode 605 can have a single-layer structure or a stacked structure. The gate electrode 605 includes titanium (Ti), tungsten (W), tantalum (Ta), molybdenum (Mo), neodymium (Nd), cobalt (Co), zirconium (Zr), zinc (Zn), ruthenium (Ru). , Rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), aluminum (Al), gold (Au), silver (Ag), copper (Cu), indium (In) Or an alloy material or a compound material containing the element as a main component can be used.

As shown in FIG. 5C, an insulator functioning as a sidewall 607 is formed on the side surface of the gate electrode 605. The sidewall 607 can be formed using an inorganic material or an organic material. Examples of the inorganic material include silicon oxide and silicon nitride. For example, when silicon oxide is formed so as to cover the gate electrode 605 and isotropic etching is performed, it remains only on the side surface of the gate electrode 605 and can be used as a sidewall. A dry etching method or a wet etching method can be used for the isotropic etching. When the sidewall 607 is processed, part of the gate insulating film 604 is also removed by etching. As a result, a part of the semiconductor film is exposed.

An impurity element is added to the semiconductor film in a self-aligning manner using the sidewall 607 and the gate electrode 605. As a result, impurity regions having different concentrations are formed in the semiconductor film. The impurity region 609 provided below the sidewall 607 has a lower concentration than the impurity region 608 formed in the exposed semiconductor film. Thus, the short channel effect can be prevented by varying the concentration of the impurity region.

As shown in FIG. 5D, insulating layers 611 and 612 are formed so as to cover the semiconductor film, the gate electrode, and the like. The insulating layer covering the semiconductor film, the gate electrode, or the like may have a single layer structure, but preferably has a stacked structure as in this embodiment mode. This is because impurities can be prevented from entering by forming the insulating layer 611 using an inorganic material, and by using an inorganic material using a CVD method, dang in a semiconductor film can be formed using hydrogen in the insulating layer 611. This is because the ring bond can be terminated. After that, the insulating layer 612 is formed using an organic material, whereby planarity can be improved. As the organic material, polyimide, acrylic, polyamide, polyimide amide, benzocyclobutene, siloxane, or polysilazane can be used. Note that siloxane has a skeleton structure of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Polysilazane is formed using a polymer material having a bond of silicon (Si) and nitrogen (N) as a starting material.

After that, a wiring 613 that penetrates the insulating layer 611, the insulating layer 612, and the gate insulating film 604 and is connected to the impurity region 608 is formed. The wiring 613 can have a single-layer structure or a stacked structure. Titanium (Ti), tungsten (W), tantalum (Ta), molybdenum (Mo), neodymium (Nd), cobalt (Co), zirconium (Zr) ), Zinc (Zn), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), aluminum (Al), gold (Au), silver (Ag) ), Copper (Cu), indium (In), or an alloy material containing the element as a main component. At the same time as the wiring 613, another wiring can be formed over the insulating layer 612. The other wiring corresponds to a routing wiring or the like.

In this manner, a thin film transistor (TFT) 615 and a TFT group 616 can be formed. A TFT group refers to a collection of TFTs that constitute a circuit having a certain function. By using the TFT group 616, a ROM can be formed.

As illustrated in FIG. 6A, the insulating layer 620 is formed over the insulating layer 612. The insulating layer 620 can be formed using an inorganic material or an organic material similarly to the insulating layers 611 and 612. A wiring 621 is formed so as to penetrate the insulating layer 620. The wiring 621 can be formed in a manner similar to that of the wiring 613. The wiring 621 is electrically connected to the wiring 613 in the region 622 through an opening provided in the insulating layer 620. In the region 622, a common electrode of a memory cell to be formed later can be grounded. A pad 623 is formed from the same layer as the wiring 621. The pad 623 is electrically connected to the wiring 619 in the region 624 through an opening provided in the insulating layer 620.

As illustrated in FIG. 6B, the insulating layer 630 is formed over the insulating layer 620. The insulating layer 630 can be formed using an inorganic material or an organic material similarly to the insulating layers 611 and 612. The side surface of the insulating layer 630 is processed to be tapered.

An organic compound layer 631 is formed in an opening provided on the TFT 615. The organic compound layer 631 can be formed by an evaporation method or a sputtering method. Such an organic compound layer can be formed from an electroluminescent material. After that, a wiring 632 is formed so as to cover part of the organic compound layer 631 and the insulating layer 630. The wiring 632 can be formed in a manner similar to that of the wiring 621. A region where the wiring 632 is formed becomes a memory region and a contact region. The wiring 632 serves as a common electrode of the memory cell. A ROM can be formed using a memory cell having such an organic compound layer.

As shown in FIG. 6C, an antenna 640 is formed. At this time, the antenna 640 is electrically connected to the pad 623 by thermocompression bonding. In this manner, a wiring region 644 where a lead-out wiring or the like is formed, a memory region 642 where a memory cell is formed, an integrated circuit region 643 where a circuit having a specific function is formed, and a pad region 645. A wireless chip having a contact region 646 is formed. The pad area and the memory area are provided apart from each other to some extent. As a result, data can be written without being affected by stress during antenna crimping.

The antenna crimping is preferably performed in a state where the flexibility of the insulating substrate is low. Therefore, in this embodiment mode, a mode of transposing to a film substrate after antenna crimping is shown.

As shown in FIG. 7A, the insulating substrate 600 is peeled by removing the peeling layer 601. The release layer 601 can be removed physically or chemically. For example, the crystal structure of the separation layer 601 can be changed by heat treatment or the like for the semiconductor film. After that, an opening is provided so that a part of the peeling layer 601 is exposed, and the exposed peeling layer 601 is irradiated with laser. By irradiating the peeling layer 601 with a laser, a trigger for peeling can be given. Then, the insulating substrate and the thin film transistor or the like can be physically peeled off, and the thin film transistor or the like may be naturally peeled off from the insulating substrate without applying any external force due to the stress of the film. Alternatively, an opening reaching the peeling layer 601 can be formed, an etching agent can be introduced through the opening, and the peeling layer 601 can be removed using a chemical reaction.

Thereafter, as shown in FIG. 7B, a film substrate 650 is attached. When the surface of the film substrate 650 has adhesiveness, it can be bonded as it is. When there is no adhesiveness, the film substrate 650 can be bonded through an adhesive.

Then, a wireless chip in which a thin film transistor or the like is transferred to the film substrate can be formed.

As described above, the wireless chip of this embodiment can be manufactured using a TFT group or a memory cell including an organic compound layer. Operating characteristics can be improved by using a TFT group, and cost reduction can be realized by using a memory cell having an organic compound layer.

(Embodiment 4)
In this embodiment mode, a wireless chip having memory cells is described as a structural example of the present invention. In addition, the shape of the antenna formed on the antenna substrate, which is applied to the wireless chip, will be described.

As a signal transmission method in the wireless chip, an electromagnetic coupling method or an electromagnetic induction method (for example, 13.56 MHz band) can be applied. In the case of using an electromagnetic induction method, a conductive layer functioning as an antenna is formed in a ring shape (for example, a loop antenna) or a spiral shape (for example, a spiral antenna) in order to use electromagnetic induction due to a change in magnetic field density.

In addition, when a microwave method (for example, UHF band (860 to 960 MHz band), 2.45 GHz band, or the like) is applied as a signal transmission method in the wireless chip, the wavelength of the electromagnetic wave used for signal transmission is considered. The shape of the conductive layer functioning as an antenna is determined. For example, the conductive layer functioning as an antenna can be formed into a linear shape (for example, a dipole antenna), a flat shape (for example, a patch antenna), a ribbon shape, or the like. Further, the shape of the conductive layer functioning as an antenna is not limited to a linear shape, and may be provided in a curved shape, a meandering shape, or a combination thereof in consideration of the wavelength of electromagnetic waves.

FIG. 8A shows an example in which a conductive layer functioning as an antenna has a narrow line shape and is formed to have a rectangular shape. In FIG. 8A, an integrated circuit 503 including a memory region having a ROM to which the present invention is applied is attached to an antenna substrate 501 on which a conductive layer (dipole antenna) 502 that functions as an antenna is formed. Yes.

FIG. 8B illustrates an example in which a conductive layer functioning as an antenna is formed to have a wide line shape. In FIG. 8B, an integrated circuit 503 including a memory region having a ROM to which the present invention is applied is attached to an antenna substrate 501 on which a conductive layer (patch antenna) 504 functioning as an antenna is formed. Yes.

FIG. 8C illustrates an example in which a conductive layer functioning as an antenna is formed in a ribbon shape (also referred to as a fan shape). In FIG. 8C, an integrated circuit 503 including a memory region having a ROM to which the present invention is applied is attached to an antenna substrate 501 on which a conductive layer 505 functioning as an antenna is formed.

The conductive layer functioning as an antenna is formed using a conductive material on the antenna substrate by a CVD method, a sputtering method, a printing method such as screen printing or gravure printing, a droplet discharge method, a dispenser method, or a plating method. Conductive materials are aluminum (Al), titanium (Ti), silver (Ag), copper (Cu), gold (Au), platinum (Pt) nickel (Ni), palladium (Pd), tantalum (Ta), molybdenum An element selected from (Mo) and indium (In), or an alloy material or a compound material containing these elements as a main component is formed in a single layer structure or a stacked structure.

For example, when a conductive layer that functions as an antenna is formed using a screen printing method, a conductive paste in which conductive particles having a particle size of several nanometers to several tens of micrometers are dissolved or dispersed in an organic resin is selectively used. Can be provided by printing. The conductive particles include silver (Ag), gold (Au), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), tantalum (Ta), molybdenum (Mo) and titanium (Ti). Any one or more metal particles, silver halide fine particles, or dispersible nanoparticles can be used. In addition, as the organic resin contained in the conductive paste, one or more selected from organic resins that function as a binder of metal particles, a solvent, a dispersant, and a coating material can be used. Typically, an organic resin such as an epoxy resin or a silicon resin can be given. In forming the conductive layer, it is preferable to fire after extruding the conductive paste. For example, in the case where fine particles containing silver as a main component (for example, a particle size of 1 nm or more and 100 nm or less) is used as the material of the conductive paste, the conductive layer is obtained by being cured by baking in a temperature range of 150 to 300 ° C. Can do. Further, fine particles mainly composed of solder or lead-free solder may be used. In this case, it is preferable to use fine particles having a particle diameter of 20 μm or less. Solder and lead-free solder have the advantage of low cost.

In addition to the materials described above, ceramic, ferrite, or the like may be applied to the antenna.

In the case of applying an electromagnetic coupling method or an electromagnetic induction method and a wireless chip including an antenna is provided in contact with a metal, a magnetic material having a magnetic permeability between the semiconductor device and the metal is used. It is preferable to provide it. This is because an eddy current flows through the metal as the magnetic field changes, and the change in the magnetic field is weakened by the demagnetizing field generated by the eddy current, and the communication distance is reduced. Therefore, by providing a material having magnetic permeability between the wireless chip and the metal, it is possible to suppress the eddy current of the metal and suppress the decrease in the communication distance. As the magnetic material, ferrite or metal thin film having high magnetic permeability and low high-frequency loss can be used.

In this manner, a wireless chip to which an antenna formed on an antenna substrate is bonded can be provided.

In this embodiment, as a structural example of a semiconductor device of the present invention, a mode in which a wireless chip having a memory cell is formed over a plastic substrate is shown. Note that the wireless chip of this embodiment includes an RF circuit for wireless communication and a CPU in the arithmetic circuit.

Table 1 shows the communication specifications of the wireless chip of this example.

A 13.56 MHz band radio signal is used for communication, and the communication standard and protocol are partially compliant with ISO / IEC 15693. The wireless chip of this embodiment supplies a power supply voltage from the wireless signal via an antenna. Although the wireless chip of this embodiment has an external antenna, it may be a built-in antenna integrated with a circuit. The data transfer rate is 26.48 kbit / s, the data encoding from the reader / writer to the wireless chip is pulse position modulation, and the data encoding from the wireless chip to the reader / writer is the Manchester system.

Table 2 shows an outline of the wireless chip of this example.

Since the wireless chip of this embodiment can be formed using a thin film transistor on a flexible substrate as described above, a very lightweight wireless chip of 103 mg can be provided.

Next, FIG. 9 shows a block configuration of the wireless chip of this embodiment. The wireless chip 550 of this embodiment includes a wireless circuit 551 and a logic circuit 570. The wireless circuit 551 includes a resonance capacitor 552, a power supply circuit 553, a system reset circuit 554, a clock generator 555, a demodulation circuit 556, a modulation circuit 557, and the like. The resonance capacitor 552 can form a resonance circuit together with an external antenna. The power supply circuit 553 includes a rectifier circuit and a storage capacitor, and can generate a power supply voltage. The system reset circuit 554 can generate a system reset signal, and the clock generator 555 can generate a system clock signal. The demodulation circuit 556 has an LPF (Low Pass Filter) and can extract data from a radio signal. The modulation circuit 557 can superimpose data on a radio signal by the Manchester method. These circuits can be formed from thin film transistors.

The logic circuit 570 includes a controller 560, a CPU 571, a ROM 572, a RAM 573, and the like. The controller 560 includes a clock control circuit 561, a control register 562, a reception data register 563, a transmission data register 564, a wireless interface 567, and a CPU interface 568. Have These circuits and the like can be formed from thin film transistors. The demodulation circuit 556 and the modulation circuit 557 can exchange signals with the control register 562, the reception data register 563, and the transmission data register 564 through the wireless interface 567. The clock generator 555 is controlled by the clock control circuit 561, and the clock control circuit 561 operates based on the control register 562. The control register 562, the reception data register 563, and the transmission data register 564 can exchange signals with the CPU 571, the ROM 572, and the RAM 573 via the CPU interface 568.

The CPU included in the wireless chip is an 8-bit CISC (Complex Instruction Set Computer) and can be configured by a flip-flop that operates in a two-phase non-overlapping clock. By using a flip-flop with a two-phase non-overlapping clock operation, it is possible to prevent malfunction caused by variations in clock skew and TFT characteristics and improve reliability. The ROM 572 can be the ROM of the present invention, and is a 2 KB mask ROM. The mask ROM can store programs, secret keys, and the like. A 64B SRAM can be applied to the RAM 573, and the SRAM can be used as a work area of the CPU. Thus, the circuit configuration of the memory cell can be devised to improve the reliability of writing / reading. The controller 560 has a function as a state machine of the wireless chip of this embodiment.

In the wireless chip of the present embodiment, SAFER (Secure And Fast Encryption Route) can be adopted as an algorithm for encryption processing. SAFER is mainly composed of 8-bit arithmetic and is an algorithm suitable for an 8-bit CPU. The wireless chip having the wireless chip of this embodiment can be equipped with a function of receiving a ciphertext, decrypting it using a secret key, and transmitting a plaintext. Of course, other cryptographic processing algorithms such as DES and AES may be employed for the wireless chip of this embodiment.

A photograph of the wireless chip (A) formed on the glass and the wireless chip (B) formed on the flexible substrate is shown in FIG. The wireless chip of this embodiment can be made very thin as described above. FIG. 11 shows a block diagram of an enlarged photograph of a wireless chip. In FIG. 11, the structure of the semiconductor device having the memory cell of the present invention can be applied to the ROM area.

It is the whole figure which showed the state by which the transistor was connected to GND in the memory cell of the semiconductor device of this invention. FIG. 5 is an overall view showing a state where a transistor is not connected to GND in a memory cell of a semiconductor device of the present invention. 3 is a timing chart illustrating the operation of FIG. 1. 3 is a timing chart illustrating the operation of FIG. 2. It is sectional drawing which showed the transistor formation process of this invention. It is sectional drawing which showed the formation process at the time of using an organic compound for a wireless chip. It is sectional drawing which showed the peeling and the adhesion process of the semiconductor device of this invention. It is sectional drawing which showed the antenna shape. It is a figure showing a block configuration of a wireless chip to which the present invention is applied. It is a photograph of the wireless chip formed on the glass and the wireless chip formed on the flexible substrate. A block diagram is described in an enlarged photograph of a wireless chip.

Explanation of symbols

10 memory cell 11 precharge circuit 12 sense amplifier circuit 15 data line 16 word line 20 GND line 501 antenna substrate 502 conductive layer (dipole antenna)
503 Integrated circuit 504 Conductive layer (patch antenna)
505 Conductive layer 550 Wireless chip 551 Wireless circuit 552 Resonance capacitor 553 Power supply circuit 554 System reset circuit 555 Clock generator 556 Demodulation circuit 557 Modulation circuit 560 Controller 561 Clock control circuit 562 Control register 563 Reception data register 564 Transmission data register 567 Wireless interface 568 CPU interface 570 Logic circuit 571 CPU
572 ROM
573 RAM
600 Insulating substrate 601 Release layer 602 Insulating layer 603 Semiconductor film 604 Gate insulating film 605 Gate electrode 607 Side wall 608 Impurity region 609 Impurity region 611 Insulating layer 612 Insulating layer 613 Wiring 615 Thin film transistor (TFT)
616 TFT group 619 wiring 620 insulating layer 621 wiring 622 region 623 pad 624 region 630 insulating layer 631 organic compound layer 632 wiring 640 antenna 642 memory region 643 integrated circuit region 644 wiring region 645 pad region 646 contact region 650 film substrate

Claims (16)

A memory cell electrically connected via a data line, a precharge circuit, and a sense amplifier circuit;
The memory cell includes a first transistor having one electrode electrically connected to the data line,
The precharge circuit includes a second transistor having one electrode electrically connected to the data line,
The sense amplifier circuit includes a third transistor having one electrode electrically connected to the data line, an input terminal electrically connected to the data line, and an output to the gate of the third transistor. A semiconductor device comprising: an inverter whose terminals are electrically connected. A memory cell electrically connected via a data line, a precharge circuit, and a sense amplifier circuit;
The memory cell includes a first transistor having one electrode electrically connected to the data line and a word line,
The precharge circuit includes a second transistor having one electrode electrically connected to the data line,
The sense amplifier circuit includes a third transistor having one electrode electrically connected to the data line, an input terminal electrically connected to the data line, and an output to the gate of the third transistor. An inverter having a terminal electrically connected;
The semiconductor device according to claim 1, wherein the word line is electrically connected to a gate of the first transistor. A memory cell electrically connected via a data line, a precharge circuit, a sense amplifier circuit, a first inverter, and a NAND;
The memory cell includes a first transistor having one electrode electrically connected to the data line and a word line,
The precharge circuit includes a second transistor having one electrode electrically connected to the data line,
The sense amplifier circuit includes a third transistor having one electrode electrically connected to the data line, an input terminal electrically connected to the data line, and an output to the gate of the third transistor. A second inverter having a terminal electrically connected thereto;
The semiconductor device, wherein the word line is electrically connected to a gate of the first transistor, and the first inverter and the NAND are electrically connected to the word line. A memory cell electrically connected via a data line, a precharge circuit, a sense amplifier circuit, a first inverter, and a NAND;
The memory cell includes a first transistor having one electrode electrically connected to the data line and a word line,
The precharge circuit includes a second transistor having one electrode electrically connected to the data line,
The sense amplifier circuit includes a third transistor having one electrode electrically connected to the data line, an input terminal electrically connected to the data line, and an output to the gate of the third transistor. A second inverter having a terminal electrically connected thereto;
The word line is electrically connected to a gate of the first transistor; the first inverter and the NAND are electrically connected to the word line;
The NAND device receives an address signal and a reset signal. In any one of Claims 1 thru | or 4,
The semiconductor device is characterized in that the potential of the other electrode of the first transistor is a ground potential. In any one of Claims 1 thru | or 4,
The semiconductor device is characterized in that the other electrode of the first transistor is electrically connected to a wiring and has a ground potential. In any one of Claims 1 thru | or 4,
The semiconductor device is characterized in that the other electrode of the first transistor is in a disconnected state. In any one of Claims 1 thru | or 7,
2. The semiconductor device according to claim 1, wherein the other electrode of the second transistor has a high potential side potential. In any one of Claims 1 thru | or 8,
2. The semiconductor device according to claim 1, wherein the other electrode of the third transistor has a high potential side potential. In any one of Claims 1 thru | or 9,
The semiconductor device is characterized in that the first transistor is an N-type. In any one of Claims 1 thru | or 10,
The semiconductor device, wherein the second transistor is a P-type. In any one of Claims 1 thru | or 11,
The semiconductor device is characterized in that the third transistor is a P-type. A memory cell electrically connected via a data line, a precharge circuit, a sense amplifier circuit, an inverter electrically connected to the memory cell, and a semiconductor device operation method including a NAND,
When a low signal is input to the precharge circuit and the NAND as a reset signal, a high signal is input to the NAND as an address signal, and a high signal is input to the data line,
The transistor of the precharge circuit is turned on,
The transistor of the memory cell is turned off,
A method of operating a semiconductor device, wherein a high signal is output from the data line. A memory cell electrically connected via a data line, a precharge circuit, a sense amplifier circuit, an inverter electrically connected to the memory cell, and a semiconductor device operation method including a NAND,
When a low signal is input to the precharge circuit and the NAND as a reset signal, a low signal is input to the NAND as an address signal, and a high signal is input to the data line,
The transistor of the precharge circuit is turned on,
The transistor of the memory cell is turned off,
A method of operating a semiconductor device, wherein a high signal is output from the data line. A memory cell electrically connected via a data line, a precharge circuit, a sense amplifier circuit, an inverter electrically connected to the memory cell, and a semiconductor device operation method including a NAND,
When a high signal is input to the precharge circuit and the NAND as a reset signal, a high signal is input to the NAND as an address signal, and a low signal is input to the data line,
The transistor of the precharge circuit is turned off,
The transistor of the memory cell is turned on,
A method of operating a semiconductor device, wherein a low signal is output from the data line. A memory cell electrically connected via a data line, a precharge circuit, a sense amplifier circuit, an inverter electrically connected to the memory cell, and a semiconductor device operation method including a NAND,
When a high signal is input to the precharge circuit and the NAND as a reset signal, a low signal is input to the NAND as an address signal, and a low signal is input to the data line,
The transistor of the precharge circuit is turned off,
The transistor of the memory cell is turned off,
A method of operating a semiconductor device, wherein a low signal is output from the data line.