JPH08272730A - Facsimile equipment - Google Patents

Abstract

PURPOSE: To surely perform command control within a certain time after a trigger by employing queue constitution for DMA operation, and using an interrupt from a timer as a trigger and executing a command data set by DMA. CONSTITUTION: When a CPU 51 sets an address in a DMA controller 52 at the time of write access to perform I/O control over mechanism control, a DMA controller 52 is actuated with the interrupt (character synchronism) from a hardware timer 52 as the trigger. And, a destination address and destination data are read out of the contents of a queue memory storing a DMA action queue, and the command data set such as a MOVE instruction, is executed by DMA. Consequently, command control can surely be performed within a certain time after the trigger and the restriction that a response (control) needs to be sent back within a certain time after the synchronizing signal is eliminated to easily expand the operation of the DMA system.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a facsimile machine I
/ O control unit (system control unit).

[0002]

2. Description of the Related Art In a conventional apparatus, for example, Japanese Patent Application Laid-Open No. 1-07
As described in Japanese Patent No. 0857, the DMA circuit simultaneously fetches the next task ordered while the processor is executing one task, so that the task is performed without interruption and the task processing speed of the processor element is increased. Is improving overall.

[0003]

In the above prior art, C is used.
When the PU tries to perform I / O control of mechanical control, synchronization with the mechanical is often performed by an interrupt from a hardware timer. In that case, there is a constraint that a response (control) must be returned within a fixed time from the synchronization signal. Therefore, the more complicated a system becomes, the more complicated the processing becomes due to an increase in interrupts, and the error in the response time from the hardware timer becomes large due to fluctuations in the processing time due to the increase or decrease in system jobs. there were.
An object of the present invention is to provide a facsimile apparatus (facsimile control system) which can solve such problems and can eliminate the restriction due to the time limitation. It is another object of the present invention to provide a queue configuration for the DMA operation so that the operation of the DMA system can be easily expanded.

[0004]

In order to achieve the above object, the invention according to a first aspect has a DMA operation in a facsimile apparatus as a queue structure, and a MOVE instruction is DMAed by an interrupt (SYNC) from a hardware timer as a trigger. It is characterized in that it is configured to do in. That is, the control means for reading the destination address and the destination data from the contents of the queue memory using the tragger from the timer as the start pulse (52 in FIG. 3).
And the command data set is executed by the DMA.
According to the invention of claim 2, in the invention of claim 1, the queue operation is performed by reading the address in which the data of the next destination is stored.
When the queue address and the start address coincide with each other, a control means for stopping the DMA operation is provided. The invention according to claim 3 is the same as claim 1
In the invention described above, in order to obtain the destination address, a control means for reading the source address and setting the command data by storing the source address is provided. The invention according to claim 4 is the invention according to claim 2, further comprising a control means for setting the command data by reading at a source address and storing the source address to obtain the destination address. It is characterized by this. In the invention described in claim 5, the contents of the read queue address are matched with a preset arbitrary value in place of the control means for stopping the DMA operation by the match with the start address in the invention described in claim 2. In this case, a control means for stopping the DMA operation is provided. Further, the invention according to claim 6 is the invention according to claim 5, further comprising a control means for setting the command data by reading at a source address and storing the source address to obtain the destination address. It is characterized by this. Also,
The invention according to claim 7 is characterized in that, in the invention according to claims 2 and 4, a control means is provided for switching the read / write operation according to the value read from the queue memory.

[0005]

In the invention described in claim 1, the DMAC (D
MA CONTROLLER) is activated by an interrupt (SYNC) from the timer as a trigger, reads the destination address / data from the contents of the queue memory, and sets the command data set such as the MOVE instruction to D.
Run on MA. This ensures command control within a fixed time from the trigger. According to the second aspect of the invention, the DMA operation is stopped when the read queue address and the read start address match. This facilitates control and sets many queue-enabled commands. In the invention of claims 3, 4, and 6, the destination address is obtained from the source address, and the command data is set by storing the source data. In the invention described in claim 5, the DMA operation is stopped when the content of the read queue address matches a preset arbitrary value (for example, "0"). This allows
Easily control and set many queue-enabled commands. According to the seventh aspect of the present invention, the read / write is performed using the control data set in the queue memory in advance to flexibly cope with complicated control.

[0006]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram of a facsimile apparatus according to an embodiment of the present invention. In FIG. 2, reference numeral 1 denotes a display unit (O.P.U.) for displaying various operating states of the apparatus by means of display keys and operation keys provided and allowing the operator to perform various operations such as input of subscriber number. Is. A reading unit (SCANNER) 2 is composed of a CCD or the like and reads an original image to be transmitted or copied at a predetermined resolution. A writing unit (PLOT) 3 records received data or read image information on a recording sheet and outputs various reports on the recording sheet.
TER). Reference numeral 4 is a buffer memory for temporarily storing image information. Reference numeral 6 denotes a compression / decoding unit (D.C.
R).

Reference numeral 7 is a system control unit (SCU) for executing control processing of the entire facsimile apparatus,
A memory (program memory including CPU, system RAM, etc.) for storing the control processing program, various data necessary for the control processing, and various device-specific information (for example, calling number / called number, modem information, etc.) Composed. An image information storage unit (SAF) 8 stores the image information read by the reading unit 2 and the image information received by communication in a coded and compressed state. 9 is a network controller 10
And a communication control unit (CCU) that controls communication with other devices via the modem unit 11. Reference numeral 10 is a network control unit (NCU) connected to a telephone line or the like and performing a predetermined line control at the time of making and receiving a call, and having an automatic calling and receiving function. 11
Is a modem unit (MD) for modulating and demodulating image information and transmitting it, and also transmitting various procedure signals for transmission control.
M). Reference numeral 12 is an IC CARD slot for accommodating an IC CARD used for application function expansion / capacity increase and the like. These are connected by the system bus 13.

FIG. 3 is a block diagram of the system controller shown in FIG. In FIG. 3, reference numeral 51 is a CPU that executes a control processing program, 52 is a DMAC (DMA CONTROLLER) that is activated by a character synchronization (SYNC) from a timer 53 as a trigger, and executes DMA.
Is a timing generator (TIMING GENER)
ATER), 54 is an input / output decoder (I / O DECODE) that performs analog signal / digital signal conversion processing.
R) and 55 are interrupt controllers (INTERRUPT)
CONTROLLER, 56 is a CPU address bus (CPU ADDRESS BUS), 57 is a data bus (DATA BUS), and 58 is an address bus (ADRE).
SS BUS).

FIG. 4 is a block diagram of the DMAC shown in FIG. In FIG. 4, 31 is a register for storing a queue address, 32 is a register for storing an I / O address, 33 is a register for storing I / O data, and 34 is a bank address register. Is.
Reference numeral 21 is a multiplexer (MPX) for selecting the data bus 57 at the time of setting the CPU command data and reading the queue address, and selecting the internal data bus 46 at the time of loading the address counted up in the DMA. Reference numeral 43 is an adder (ADDER) used when incrementing the address. 41 is a register (R
EG) 31 is a latch (LATCH) for preventing the output address from changing during the DMA when the increment address is loaded. A multiplexer (MPX) 22 selects an address of the latch 41 when data is loaded from a RAM (not shown) or stored in the RAM, and is stored in the register (REG) 32 when a MOVE instruction is performed. Select the content. 44 is
A buffer memory (3 that outputs data to the data bus 47
STATE). 42 is a control processor (CM
P) and 49 are command buses.

Next, the I / O control method for DMA with the above configuration will be described with reference to FIGS. 1, 3, and 4. FIG. 1 is a conceptual diagram showing the memory contents during a DMA operation in the first embodiment of the present invention, and shows one embodiment of the invention described in claims 1 to 4. The queue-structured memory is not shown in FIGS. In this embodiment, at the time of write access, the address "a" is DM
When set in the AC 52, the DMAC 52 is activated by the SYNC from the hardware timer 53 as a trigger. First, the data content of the address "a""AD_
1 ”is stored in the register 32. In the next DMA cycle, the data of the address “a + 2” “DA_
1 ”is stored in the register 33. In the next DMA cycle, DAMC outputs the value of “AD_1” to the address bus 58 and the value of “DA_1” to the data bus 57. At the same time, a write signal is output to the external strobe to write the data "DA_1" to the address "AD_1". The above is one embodiment of the invention described in claim 1.

In the next DMA cycle, the queue address "b" in which the next operation content is written is read from the address "a + 4" (not shown). The content "A
D_2 ”is stored in the register 31. In the next cycle, the data of "DA_2" is read from the address "b + 2", and the same operation as described above is repeated. Then, when the content of the read queue address becomes the start queue address “a” again, the DMA write operation is completed.
The above is one embodiment of the invention described in claim 2.

On the other hand, at the time of read access, if the address "a" is set in the DMAC 52, the DMAC
52 is activated by using SYNC from the hardware timer as a trigger. Then, “AD — 1” which is the data content of the address “a” is stored in the register 32. In the next DMA cycle, the DMAC 52 outputs the value of "AD_1" to the address bus 58. At the same time, a read signal is output to the external strobe and "D" is output to the data bus.
The data value of “A_1” is written in the register 33. Next D
In the MA cycle, the data in the register 33 is stored in the address (a + 4) (not shown). The above is one embodiment of the invention described in claim 3.

In the next DMA cycle, the queue address "b" in which the next operation content is written is read from the address "a + 4". The content is stored in the register 31. In the next DMA cycle, “b + 2” to “D
The data "A_2" is read out and the same operation as the embodiment of the invention described in claim 1 is repeated. Then, the operation of the DMA is completed when the content of the read queue address becomes the start queue address. The above is one embodiment of the invention described in claim 4.

FIG. 5 shows D in the second embodiment of the present invention.
It is a conceptual diagram which shows the memory content at the time of MA operation | movement, and shows one Example of invention of Claim 5 and 6. In addition,
This queued memory is not shown in FIGS. In this embodiment, the same DMA operation as in the first embodiment is performed, but the DMA operation is controlled to be completed when the content of the read queue address becomes "0" shown in FIG. . Note that this "0" may be any value.

FIG. 6 shows D in the third embodiment of the present invention.
It is a conceptual diagram which shows the memory content at the time of MA operation, Comprising:
1 illustrates one embodiment of the described invention. The queue-structured memory is not shown in FIGS.
In this embodiment, the address "a" is the same as in the first embodiment.
Is set in the DMAC 52, the DMAC 52 is activated by the SYNC from the hardware timer 53 as a trigger. First, "A" which is the data content of the address "a"
D_1 ”is stored in the register 32. Next DMA
In the cycle (address “a + 2”), the data content for discriminating between the read mode and the write mode is read and the next operation (R / W operation) is determined. Instead of reading the setting mode in the next DMA cycle, the setting mode may be assigned to a specific bit of the data in which the queue address “a + 2” is stored.

[0016]

According to the first aspect of the present invention, command control can be reliably performed within a fixed time from the trigger. According to the invention described in claims 2, 4, 5, and 6, the control means capable of queue operation can set more commands. Further, since the setting of DMA end coincides with the start address or an arbitrary set value, control can be easily performed. According to the third aspect of the present invention, it is possible to surely read the control data within a certain time after the trigger. According to the invention as set forth in claim 7, since the control data can be read and written by the data read from the memory, various controls can be performed.

[Brief description of drawings]

FIG. 1 is a conceptual diagram showing memory contents during a DMA operation in a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a facsimile apparatus according to an embodiment of the present invention.

FIG. 3 is a configuration diagram of a system control unit according to an embodiment of the present invention.

FIG. 4 is a configuration diagram of a DMAC according to an embodiment of the present invention.

FIG. 5 is a conceptual diagram showing memory contents during a DMA operation in the second embodiment of the present invention.

FIG. 6 is a conceptual diagram showing memory contents during a DMA operation in the third embodiment of the present invention.

[Description of Codes] 1: Display unit, 2: Reading unit, 3: Writing unit, 4, 44: Buffer memory, 6: Compression decoding unit, 7: System control unit,
8: image information storage unit, 9: communication control unit, 10: network control unit,
11: modem, 12: IC CARD slot, 13:
System bus, 21, 22: multiplexer, 31-3
4: register, 41: latch, 42: control processor,
43: adder, 46: internal data bus, 49:
Command bus, 51: CPU, 52: DMAC, 53:
Timing generator, 54: input / output decoder, 5
5: interrupt controller, 56: CPU address bus,
57: data bus, 58: address bus.

Claims (7)

[Claims] 1. A timer, a DMA controller, and a DM.
A memory for storing an A operation queue, the DMA controller operates by using a trigger from a timer as an activation pulse, reads a destination address and destination data from the contents of the memory,
A facsimile apparatus characterized by being configured to execute a command data set by DMA. 2. The facsimile apparatus according to claim 1, wherein a queue operation is performed by reading an address where the next destination data is stored, and when the read address and the start address match. , A facsimile apparatus characterized by being configured to stop the DMA operation. 3. The facsimile apparatus according to claim 1, wherein the destination address is read at the source address of the memory content, and the command data is set by storing the source address. Facsimile machine. 4. The facsimile apparatus according to claim 2, wherein the destination address is read at the source address of the memory content and the command data is set by storing the source address. Facsimile machine. 5. The facsimile apparatus according to claim 1, wherein a queue operation is performed by reading an address in which data of a next destination is stored, and the content of the read address is a preset arbitrary value. A facsimile apparatus characterized in that it is configured to stop the DMA operation if they match. 6. The facsimile apparatus according to claim 5, wherein the destination address is read at the source address of the memory content, and the command data is set by storing the source address. Facsimile machine. 7. The facsimile apparatus according to claim 2, wherein the read / write operation is switched according to a value read from the memory.