JP2950725B2 - Image communication device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image communication apparatus, and more particularly to an image communication apparatus having a memory for storing transmitted or received image data. 2. Description of the Related Art As a facsimile apparatus, there is known an apparatus provided with an image memory for storing image data to be transmitted and received. The image memory stores the received image and stores the received image in a predetermined I / O mode.
It is used for various purposes, such as permitting recording and output only when D information is input, ensuring the confidentiality of communication, and temporarily storing images reserved for transmission. However, due to problems such as cost, such an image memory is not used for multitask processing as performed in a computer system or the like. For example, while a received document is being recorded, a process of reading a transmission reservation document or a document image to be copied into an image memory using an unused image reading unit is not performed. In the conventional apparatus, only a simple multiplexing process that accepts a transmission reservation during reception and conveys a document to a reading unit is possible. Even if such processing is performed for the transmission reservation, the operator is uneasy when the reserved document is to be removed, and the usability of the apparatus is the same as in the case of the single task. Although it is not inconceivable that a plurality of image processes such as reception and recording and image reading and storage are performed in parallel, a high-speed processor and a large-capacity memory are required. There is a problem that the manufacturing cost is significantly increased. Since it is difficult for a single processor to execute image processing for handling a large amount of data, a plurality of processors operating at the same time may be required, and the cost of the apparatus is further increased. This is because, in a facsimile machine, the transmitting side can adjust the processing time by adding fill data and the like, but the receiving side must adhere to the minimum transmission time declared in the pre-communication procedure, and as described above, This is because if the transmission is performed in parallel, the reception process cannot be delayed. An object of the present invention is to provide an image communication apparatus which solves the above-mentioned problems and which can execute image reception and image data input processing in parallel with a simple and inexpensive configuration. [0009] In order to solve the above problems, a communication means for transmitting or receiving image data;
A first storing image data received by the communication means;
Memory, output means for outputting the received image data stored in the first memory, input means for inputting image data different from the received image data, and reception of the first memory by the output means A second memory storing a received image program for outputting image data, and a control program for executing a plurality of processes including an image data input processing program by the input means, the received image output processing program, and a control processor for executing the time division input processing program, the control-flop
A processor for controlling the output processing based on a state of the first memory;
A configuration is adopted in which the control program is switched between the control program and the input processing program . According to the above arrangement, the state of the first memory for storing the received image data is controlled by one control processor.
Output processing program and input processing program
By switching the input and output of received image data and input processing of images for transmission, etc. can be performed in parallel, there is no need for a complicated control configuration such as a multiprocessor, and other images for transmission etc. are received during reception. Multiple processing such as inputting can be performed. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the embodiments shown in the drawings. FIG. 1 shows the configuration of a facsimile apparatus employing the present invention. In the figure, reference numeral 11 denotes a CPU for controlling the operation of the entire apparatus, which is constituted by a microprocessor element or the like. The CPU 11 is connected with various storage means necessary for control via a data and address bus, and with various units to be controlled later. Hereinafter, these components will be described. The ROM 12 is used to store programs and constants necessary for control described later. The image memory 13 includes a RAM, a hard disk device, and the like.
Used for temporary storage of transmission / reception image data. In this embodiment, a receiving memory 14 dedicated to storing received images is provided. This reception memory 14
Is used to perform image reception and other processing in parallel, for example, reading processing of a transmission reservation original. The reading of the original image data is performed by a reading unit 15 configured using a CCD sensor or the like. The received image data or the image data read by the reading unit 15 during the copying operation is recorded by the recording unit 16 including a thermal printer, an ink jet printer, or the like. Transmission and reception of image data to and from the line 19 are performed via the communication unit 17. The communication unit 17 includes a modem for modulating and demodulating image signals and procedure signals, an NCU for controlling line connection with a telephone for line control, or holding a loop. The operation unit 20 is provided for inputting an operation for performing a desired operation of the apparatus. Operation unit 20
Is composed of a keyboard such as a numeric keypad and a display such as a liquid crystal display. The above configuration is the same as that of the conventional apparatus except that the reception memory 14 dedicated to the reception image is provided. Next, the operation of the above configuration will be described. The receiving memory 14 has a structure as shown in the memory map of FIG. The reception memory 14 is used for storing received image data sequentially from a lower (upper side in the figure) address (or upper address). The received image data is encoded by an encoding method such as MH (Modified Huffman) and MR (Modified Read), and is sequentially stored in the reception memory 14 before decoding. The decoding is performed by a decoding unit (not shown) or C
The processing is performed by the PU 11 in parallel with the reception. That is, the reception data to be decoded is read out from the reception memory 14 in the order in which they are sequentially stored, and sent to the decoding process. The current position of the leading end of the received data storage area is indicated by the receiving pointer RP, and the leading end of the already read area of the decoded data is indicated by the decoding pointer DP.
These pointers are set in some registers, memories, and the like. Each pointer moves downward in the figure under the control of software as the receiving and decoding (and further recording and outputting) processes proceed. Although the shaded area in FIG. 2 was received,
This is the area that has not been decoded yet. The only memory area whose contents must be guaranteed is the hatched part, and the other part can be used for storage of the next received image or other uses by using a known memory management technique. When the decoding pointer DP and the receiving pointer RP reach the end of the memory, they return to the head of the automatically secured area. Such a memory process is called a FIFO (fast-in, first-out) process. When the speed of the decoding process is lower than the speed of the receiving process, this area always occurs, and the decoding pointer D
P and the reception pointer RP move with a certain address offset. However, as described later, in consideration of a case where the speed of the decoding process is faster than the speed of the receiving process,
Prohibition processing is required to prevent the decryption pointer DP from overtaking the reception pointer RP. FIG. 3 shows a control procedure performed by the CPU 11 of FIG. 1. The illustrated procedure is stored in the ROM 12. As shown in the upper part of FIG. 3, the decoding and output processing of the received data and the storage processing of the transmission original can be performed in parallel. This parallel processing is controlled by a task control routine shown at the bottom of the figure, as is well known in the field of computer technology. Therefore, C
As described above, a processor capable of sufficiently executing a plurality of processes in parallel must be used for the PU 11. At present, microprocessor chips of this kind are available at relatively low cost. First, decoding and output processing of received data will be described. The decoding and output processing of the received data is started based on detection of a call signal transmitted from the line 19 and the like. The received image data is demodulated by the communication control unit 17,
The encoded data is sequentially stored in the reception memory 14 in accordance with a known procedure (not shown). The decryption process is step S1
ＳS3 is performed in a loop. In step S1, decoded data received in a predetermined byte unit is read from the reception memory 14. In step S2, the read data is decrypted. Further, the decoding pointer DP is advanced by a predetermined offset. In step S3, it is determined whether one line of data has been completed, that is, whether the EOL code has been read in the G3 procedure or the like. If the result of step S3 is affirmative, the process proceeds to step S4. If step S4 is denied, the process loops to step S1. In step S4, the recording unit 16 records one line of data decoded by the above loop. The decoding and output processing of the received data is performed by repeatedly executing the processing task of one line by the task control software shown in the lower part of the figure. On the other hand, in the process of accumulating the original image at the upper right of the figure, the original image loaded in the reading unit 15 is read in step S11, and the output data is stored in step S11.
And coded in step S12. In step S13, the encoded data is stored in the image memory 13. The above processing is performed at step S14 by the reading unit 15
Is continued until it is confirmed that one line of data has been read. As described above, the image storage processing is also constituted by the task for one line. When the task control software operates the above two processes in parallel, it follows the procedure shown at the bottom of the figure. First, in step S22, the decryption pointer D
The current value of P and the reception pointer RP is taken in, and the remaining amount of memory (the area other than the broken line in FIG. 2) is calculated. In step S23, it is determined whether the remaining amount is larger than a predetermined value V. The predetermined value V varies depending on the system, but is roughly determined by the processing time and transmission speed of one line for document storage, and the processing time for decoding and outputting one line. If step S23 is denied,
The process proceeds to step S24, and if affirmative, the process proceeds to step S25. In step S24, the received data decoding and output tasks of steps S1 to S4 are executed. In step S25, the accumulation task of steps S11 to S14 is executed. In step S26, the received data decoding similar to step S24 is executed. , Execute the output task, and return to step S22. That is, when the remaining amount of the reception memory 14 is not sufficient, the processing of accumulating the document in the image memory 13 in steps S11 to S14 is temporarily stopped, and the processing in steps S1 to S4
The received data is decoded and output (step S24). If the remaining amount of the reception memory 14 is sufficient, the data reception and accumulation processing in the reception memory 14 are automatically performed, and the reception pointer RP is updated without decoding and the decoding pointer DP is stopped. In the meantime, the document storage process is performed, and thereafter, the received data is decoded and output (steps S25 and S26). As described above, the reception-only memory is provided,
By performing the document accumulation processing according to the remaining amount, the image accumulation processing for reception and transmission can be performed using the CPU 11 by one processor. According to this configuration, parallel processing of transmission and reception can be realized simply and inexpensively only by adding software and memory without increasing hardware such as a processor. In the above configuration, the process of reading the transmission image in parallel with the reception is illustrated, but the process performed in parallel with the reception is not limited to this. For example, it is conceivable that the recording unit 16 reads an image to be copied in parallel with the reception. In addition, a plurality of lines can be accommodated in the communication control unit 17 so that one line can receive the image data and the other line can transmit the read image data. In the above-described embodiment, if only one of the reception and the storage processing of the original image is performed, the processing shown in FIG.
Needless to say, only one of the processes at the top of is performed. In the above-described embodiment, as shown in FIG. 3, the task control program controls each decryption output and each line of the original storage processing program. An embodiment will be described. In another embodiment, the programmable timer 21 shown in FIG. 4 is provided, and when this output signal is used as an interrupt signal to execute the task interrupt processing program shown in FIG.
Processing can be alternately performed in parallel without terminating the decoding output and the document storage processing in units of pages. This programmable timer is currently
Many have a built-in CPU, which does not complicate the hardware. 4 is the same as FIG.
Is the same as The processing flowchart of FIG. 5 will be described. The processes of decryption output and document storage are the same as those in FIG. 3, but each task is automatically switched by an interrupt, so that it is not necessary to terminate each task. That is, when data interruption is performed in step S102 of the decryption output and a task interrupt occurs, the process proceeds from step S121 to step S122, where the next start task is the document storage side, and step S1 is executed.
At 27, if the remaining amount of the receiving memory is smaller than the predetermined amount, it is determined that there is no room, the process proceeds to step S129, the setting of the programmable timer 21 is set to 3 ms, and the process proceeds to step S126.
To set a task start for document storage (processing of a stack area, which is a conventional well-known technique, and returning to the designated task side by a return instruction in step S130). By setting this timer value to 3 ms, if a task interrupt occurs at step S112, the process on the document storage side is executed for 3 ms from step S113, and a task interrupt occurs again and the process is forcibly jumped to step S121. . Since the next activation task is the decoding output side, the process proceeds to step S123, and if the remaining memory is smaller than the predetermined amount, it is determined that there is no allowance, the timer value is set to 10 ms in step S125, and the following steps S126 and S130
Proceed to and perform the decoding output process for 10 ms from step S103.
Run for a while. Next, when a task interrupt occurs, the next task to be started is the document storage side. In step S127, if the remaining memory is larger than a predetermined amount, it is determined that there is a margin, and the standard execution time of 5 ms is set in the programmable timer. The same applies when executing step S124. As described above, by extracting the remaining amount of memory, it is determined whether the amount of reception is larger or smaller than a predetermined amount, and the value of the programmable timer is switched to control the execution time. Control and design are easy and smooth operation is obtained. In each of the above embodiments, two reception memories and two image memories are provided. However, it is of course possible to allocate a memory space for reception and an image to one memory element and use them. The above configuration is not limited to a facsimile machine but can be applied to various image communication devices. As is clear from the above, according to the present invention, the image data received by one control processor
Output processing program based on the state of the first memory for storing the
By switching between the RAM and the input processing program , output of received image data and input processing of images for transmission can be performed in parallel, and a complicated control configuration such as a multiprocessor is not required. This makes it possible to perform multiplexing processing such as inputting an image for transmission and the like, and has an excellent effect that transmission / reception processing can be executed in parallel easily and inexpensively.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a structure of an image communication device employing the present invention. FIG. 2 is an explanatory diagram showing a memory area of a receiving memory of FIG. 1; FIG. 3 is a flowchart illustrating a process of a CPU in FIG. 1; FIG. 4 is a block diagram showing another embodiment of the image communication apparatus. FIG. 5 is a flowchart showing the processing of the CPU in FIG. 4; [Description of Signs] 11 CPU 12 ROM 13 Image memory 14 Reception memory 15 Reading unit 16 Recording unit 17 Communication control unit 20 Operation unit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04N 1/00-1/00 108 H04N 1/21

Claims (1)

(57) [Claims] Communication means for transmitting or receiving image data; and a first means for storing the image data received by the communication means.
Memory, output means for outputting received image data stored in the first memory, input means for inputting image data different from the received image data, and reception of the first memory by the output means A second memory storing a received image program for outputting image data, and a control program for executing a plurality of processes including an image data input processing program by the input unit; the received image output processing program; A control processor that executes an input processing program in a time-sharing manner , wherein the control processor is configured to execute the input processing program based on a state of the first memory.
The output processing program and the input processing program
An image communication device characterized by switching .