JPH08272409A - Sequence controller - Google Patents

Abstract

PURPOSE: To perform simulation even when no real input/output equipment is provided. CONSTITUTION: A real I/O address representing a position on a real I/O space, a virtual I/O address representing the position on a virtual space, memory addresses in accordance with them, and an effective flag representing whether or not the virtual I/O address is effective are set on a mapping table 6. As a virtual I/O, a simulator module loaded on, for example, a connector 5 is set. When the information of the flag is validated, input/output information is transferred between the simulator module and memory 3a based on the correspondent relation of the virtual I/O address and the memory address. In such a way, the simulation is performed even when no real inpu/output equipment is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sequence controller for exchanging input / output information between an I / O space and an internal memory, and particularly to a virtual I / O space as well as a virtual I / O space.
The present invention relates to a sequence controller that can also access O space.

[0002]

2. Description of the Related Art Conventionally, in the field of FA (Factory Automation), a sequence controller (programmable controller) for automatically controlling a production system according to a created program has been widely used. This sequence controller has a method of directly exchanging input / output information with an actual input / output device (hereinafter referred to as an actual I / O) such as a switch, a relay contact, a motor, or a valve, and an actual I / O. There is a method in which input / output information is exchanged with the internal memory for each scan and the actual calculation is performed on the internal memory. Generally, the latter method (this is called a batch refresh method) is the mainstream. ing.

In such a batch refresh system, it is necessary to set the correspondence between the internal memory and the real I / O. As a method for setting this correspondence, the actual I /
According to the method of fixedly determining the correspondence depending on where the I / O card having the interface function with O is mounted in the I / O connector which is the input / output terminal of the controller, and the mounting order of the I / O card There are a method of making a decision and a method of making a decision based on a mapping table which stores the correspondence between the internal memory and the actual I / O. In the method in which the correspondence is fixedly determined depending on the mounting position of the I / O card, if the I / O cards are mounted disjointly, the positions of the corresponding internal memory become disjointed and the handling becomes difficult. . In addition, the method of deciding according to the mounting order of I / O cards allows the internal memory to be used efficiently, but if the card is removed during the process or added later, the correspondence needs to be changed. turn into.

Therefore, in order to facilitate the setting of the correspondence relationship between the internal memory and the actual I / O, there has been considered a method of providing a mapping table for storing the correspondence relationship inside the sequence controller. However, in any of the above-mentioned methods, since the input / output information is exchanged between the internal memory and the real I / O based on the above correspondence, the I / O card is not installed, that is, the real memory. I / O
If was not connected, it could not operate as a controller.

[0005]

As described above, the conventional sequence controller has a problem that it cannot operate unless the actual input / output device is connected, and the simulation cannot be performed. . The present invention has been made to solve the above problems, and an object of the present invention is to provide a sequence controller that can perform a simulation without an actual input / output device.

[0006]

A sequence controller according to the present invention is a real I / O address which gives an I / O address of an actual input / output device and a virtual I / O which gives an I / O address of a virtual input / output device. It has a mapping table that stores an address, a valid flag indicating whether this virtual I / O address is valid, and a memory address corresponding to the real I / O address and the virtual I / O address.

[0007]

According to the present invention, the input / output information is normally exchanged between the actual input / output device and the I / O memory based on the correspondence between the actual I / O address and the memory address. Then, when the valid flag indicates that the virtual I / O address is valid, the virtual input / output device and the I / O are based on the correspondence between the virtual I / O address and the memory address.
Input / output information is exchanged with the memory.

[0008]

FIG. 1 is a block diagram of a sequence controller showing an embodiment of the present invention. Reference numeral 1 is a program memory that stores a sequence program (ladder program), 2 is a CPU that executes the sequence program stored in the memory 1 and realizes a function as a controller,
3 is an internal memory, 3a is an internal memory in the internal memory 3, and
I / O in which input / output information exchanged with O is written
The O memory 3b is a data memory that is also in the memory 3 and is used when the sequence program is executed.

Further, 4 is a work RAM used when executing a special instruction stored in a ROM (not shown), 5 is an I / O connector which is an input / output terminal of the controller, and 6 is an I / O connector.
It is a mapping table which stores the correspondence between the O space and the internal memory.

Next, the operation of such a sequence controller will be described. FIG. 2 is a diagram showing a state in which the correspondence between the I / O space and the internal memory is set on the mapping table 6. A is a position in the actual I / O space (actually I / O
A real I / O address indicating the connector number of the O connector 5, and B is a virtual I indicating a position in a virtual I / O space described later.
/ O address, C is real I / O address A and virtual I / O
An internal memory address indicating the position on the I / O memory 3a corresponding to the address B, and F is a valid flag indicating whether the virtual I / O address B is valid.

The CPU 2 of the sequence controller normally uses the real I / O address A set in the mapping table 6 and the real memory I based on the corresponding relationship between the real I / O address A and the internal memory address C.
Input / output information is exchanged between the / O and the I / O memory 3a. Input information obtained from the real I / O indicated by the real I / O address A, that is, information obtained from an input device such as a switch or a relay contact connected to an I / O card (not shown) attached to the I / O connector 5. Is read every scan and I / I indicated by the corresponding internal memory address C
It is written in the position of the O memory 3a. Thus, the CPU
2 can obtain input information from the real I / O.

Output information given to the real I / O indicated by the address A, that is, the I / O attached to the connector 5
The information given to the output device such as the motor and valve connected to the card is the I / O memory 3 indicated by the memory address C.
It is written in the position of a for each scan and is output to the I / O connector 5 indicated by the corresponding address A. In this way, output information is given from the sequence controller to the real I / O.

In the exchange of such input / output information, when the valid flag F becomes significant (for example, "1"), C
PU2 determines that the virtual I / O address B has become valid. Then, instead of the real I / O address A, the virtual I / O
Using O address B, virtual I / O space and I / O memory 3
Input / output information is exchanged with a. As the virtual I / O space, the data memory 3b, work RAM 4, real I / O
O space (here, I / O attached to I / O connector 5
Simulator module which is a kind of O card) can be set.

For example, the virtual I / of the mapping table 6
The address of the data memory 3b is set as the O address B, and a ladder program for simulation that allows the data memory 3b to function as a virtual input / output device is stored in the program memory 1. This allows the CPU
2 causes the program stored in the memory 1 to execute,
Input / output information of a virtual input / output device appears on the data memory 3b.

Here, if the effective bit F is significant, C
The PU 2 is a virtual I / O and has a data memory 3b and an I / O.
Input / output information is exchanged with the memory 3a. In this way, by operating the data memory 3b as a virtual input / output device, even if the actual I / O is not connected to the I / O connector 5, simulation can be performed only by the CPU 2 of the controller.

Similarly, the address of the work RAM 4 is set as the virtual I / O address B, and the work RAM 4 is set.
A special instruction for simulation is stored in the ROM to function as a virtual input / output device. The special instruction is provided by firmware by the manufacturer of the sequence controller, and the work RAM is a memory used when the special instruction is executed and cannot be directly accessed from the ladder program created by the user. Thus, if the valid bit F is made significant while the CPU 2 is executing this instruction, the same effect as described above can be obtained.

Further, a simulator module that operates in the same way as an actual I / O is attached to the I / O connector 5, and a virtual I / O is installed.
As the I / O address B, the number of the I / O connector 5 to which the simulator module is attached is set. In this case, the CPU 2 only needs to make the effective bit F significant.
Input / output information is exchanged between the simulator module and the I / O memory 3a. As a result, a simulation assuming an actual operation can be performed without changing the sequence program stored in the memory 1, and the program can be debugged.

[0018]

According to the present invention, by expanding the mapping table so that the virtual I / O address and the valid flag can be stored, the flag information can be validated.
Since the input / output information is exchanged between the virtual input / output device indicated by the virtual I / O address and the I / O memory indicated by the memory address, the simulation can be performed without the actual input / output device. .

[Brief description of drawings]

FIG. 1 is a block diagram of a sequence controller showing an embodiment of the present invention.

FIG. 2 is a diagram showing a state in which a correspondence relationship between an I / O space and an internal memory is set on a mapping table.

[Explanation of symbols]

1 ... Program memory, 2 ... CPU, 3 ... Internal memory,
3a ... I / O memory, 3b ... Data memory, 4 ... Work RAM, 5 ... I / O connector, 6 ... Mapping table, A ... Real I / O address, B ... Virtual I / O address,
C ... Internal memory address, F ... Valid flag.

Claims (1)

[Claims] 1. Input / output between an input / output device and an I / O memory based on a correspondence relationship between an I / O address indicating a connection position of the input / output device and a memory address indicating a position on the I / O memory. In a sequence controller that exchanges information, a real I / O address that gives an I / O address of an actual input / output device, a virtual I / O address that gives an I / O address of a virtual input / output device, and this virtual I / O A valid flag indicating whether the address is valid, and a mapping table storing memory addresses corresponding to the real I / O address and the virtual I / O address, and the valid flag indicating that the virtual I / O address is valid , The virtual I / O address is used instead of the real I / O address.