JPH08264582A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To ensure sealing between a semiconductor chip and an auxiliary wiring board piece by adopting a method such as to provide a sealing resin layer to a surface of an auxiliary wiring board piece opposite to a surface at the side of an electrode of a semiconductor chip. CONSTITUTION: A sealing resin layer 3 is provided in advance to a surface excepting an inside electrode 22 at the side of the inside electrode 22 of an auxiliary wiring board piece 2 with a wiring pattern consisting of an inside electrode 22 connected to an electrode 41 of a semiconductor chip 4, an outside electrode 23 connected to a conductor end of a mounting circuit board and a routing conductor 21 extending between the electrodes 22, 23. The electrode 41 of the semiconductor chip 4 is connected to the inside electrode 22 of the auxiliary wiring board piece 2 and a surface at the side of the electrode 41 of the semiconductor chip 4 is fused to a sealing resin layer 3. For example, the auxiliary wiring board piece 2 has insulation layers 11, 12 holding the routing conductor 21 therebetween and is prepared by using a plastic tape base. It is desirable to form the sealing resin layer 3 by using thermally fusing polyimide.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a chip scale package type semiconductor device.

[0002]

2. Description of the Related Art As a packaged semiconductor device, a semiconductor chip is mounted on a die pad of a lead frame, and an electrode of the semiconductor chip and an inner lead of the lead frame are wire bonded. A structure in which a semiconductor chip is sealed with a resin except a lead frame and an outer lead is well known. However, in such a package structure, it is necessary to make the pitch of the outer leads of the lead frame considerably wide in terms of soldering accuracy, and it is unavoidable that the package becomes large in size, which is disadvantageous to high density. Is.

Therefore, as shown in FIG. 8, between the inner electrode 22 'connected to the electrode 41' of the semiconductor chip 4 ', the outer electrode 23' connected to the conductor end of the mounted circuit board, and these electrodes. A chip-sized auxiliary wiring board piece 2'having a printed wiring pattern made up of extending wiring conductors 21 'is applied to the surface of the semiconductor chip 4'on the side of the electrode 41', and the inner electrode 22 of the auxiliary wiring board piece 2'is applied. It has been proposed that the'and the electrode 41 'of the semiconductor chip 4'be connected, and then sealed with a resin 5'by transfer molding or the like. In this resin sealing, it is necessary to press-fit the resin between the semiconductor chip 4'and the auxiliary wiring board piece 2'by voidless.

[0004]

However, the gap between the semiconductor chip and the inner electrode is narrow, and a high pressure is required to press the resin into this gap, which is not easy. In addition, since the resin enters from all four sides of the gap, it is unavoidable that air is trapped in the void, which makes voiding extremely difficult. However, it is possible to form air vent holes in the auxiliary wiring board piece, but the printed wiring space of the auxiliary wiring board piece becomes small, and in addition to the chip-sized flat space, Further, it is subject to severer restrictions, and it becomes difficult to achieve desired printed wiring.

An object of the present invention is to provide a printed wiring pattern including an inner electrode connected to an electrode of a semiconductor chip, an outer electrode connected to a conductor end of a mounted circuit board, and a lead conductor extending between these electrodes. In the semiconductor device in which the chip-sized auxiliary wiring board piece having the above is applied to the electrode-side surface of the semiconductor chip and the inner electrode of the auxiliary wiring board piece and the electrode of the semiconductor chip are connected, the semiconductor chip and the auxiliary wiring board piece are It is an object of the present invention to provide a method for manufacturing a semiconductor device that can reliably seal the gaps.

[0006]

Wiring comprising an inner electrode connected to an electrode of a semiconductor chip according to the present invention, an outer electrode connected to a conductor end of a mounted circuit board, and a lead conductor extending between these electrodes. A sealing resin layer is provided in advance on the surface of the auxiliary wiring board piece having the pattern on the inner electrode side except the inner electrode, and the electrode of the semiconductor chip is connected to the inner electrode of the auxiliary wiring board piece. The surface of the semiconductor chip on the electrode side is fused to the encapsulating resin layer described above. The plastic tape substrate is provided with an inner electrode connected to the electrode of the semiconductor chip and a mounted circuit. A large number of wiring patterns consisting of outer electrodes connected to the conductor ends of the plate and routing conductors extending between these electrodes are provided at predetermined intervals in the tape longitudinal direction, and the inner side of the inner electrode is provided with the wiring patterns. Resin layer for sealing excluding electrodes Obtained previously provided the film carrier,
The electrode of the semiconductor chip is connected to the inner electrode of each wiring pattern of this film carrier, and the surface of the semiconductor chip on the electrode side is fused to the sealing resin layer described above. It can be punched around the chip, that is, a film carrier method.

Further, the auxiliary wiring board piece or the routing conductor has an insulating layer sandwiching the routing conductor. Of these both insulating layers, the insulating layer on the semiconductor chip side and the sealing resin layer on the insulating layer are provided. A hole is provided from the lead conductor to the electrode of the semiconductor chip, and the metal filled in the hole and the metal bump formed so as to project from the hole form the inner electrode, and the outer electrode is formed on another insulating layer. It is desirable that a hole be provided and that the hole be composed of a metal. Furthermore, the electrode of the semiconductor chip can be connected to the inner electrode of the wiring pattern, and at the same time, the surface of the semiconductor chip on the electrode side can be fused to the sealing resin layer. It is preferable to use a heat-fusible polyimide.

[0008]

The sealing resin layer is provided in advance on the surface of the auxiliary wiring board piece that opposes the electrode side surface of the semiconductor chip, and if the auxiliary wiring board piece is brought into contact with the electrode side surface of the semiconductor chip, the contact will occur. The sealing resin naturally intervenes at the contact interface with its layer thickness, and the interface is uniformly sealed by fusion of the sealing resin layer and the electrode-side surface of the semiconductor chip. It In this case, unlike the sealing by press-fitting the resin, the problem of high resin pressure and the problem of air inclusion can be avoided, and the voidless resin can be easily sealed.

【Example】

The structure of the present invention will be described below with reference to the drawings. In order to manufacture a semiconductor device according to the present invention, it is first necessary to manufacture an encapsulating resin layer-attached auxiliary wiring board piece. FIG. 1 shows the encapsulating resin layer-attached auxiliary wiring board piece A (2 is an auxiliary wiring board). An example of a plate piece is shown. In FIG. 1, 11
And 12 are insulating layers, 21, 21 ... Leading conductors sandwiched between the insulating layers 11 and 12, 3 is a sealing resin layer provided on the insulating layer 11, and 221 is an insulating layer 11 and a sealing resin. Layer 3
The hole 22 is formed from one end of the lead conductor 21 to the side facing the electrode of the semiconductor chip, and 22 is composed of a metal 222 filled in the hole 221 and a metal bump 223 formed to project from the hole 221. An inner electrode 231 is a hole provided in the other insulating layer 12 at the other end of the conductor 21, and an outer electrode 23 is composed of a metal 232 filled in the hole 231.

To manufacture a semiconductor device according to the present invention,
First, as shown in FIG. 2A, the lead-out conductor 21 is formed on one surface of the insulating film 11 by a printing method, and the sealing resin layer 3 is provided on the other surface of the insulating film 11 from a thermoplastic resin or the like. It is preferable to use a method of chemically etching the metal foil of the metal foil laminated synthetic resin film into a predetermined routing pattern for the printed formation of the routing conductor 21. This metal foil laminated synthetic resin film uses a two-layer base material in which copper foil is fused to the synthetic resin film, a three-layer base material in which copper foil is adhered to the synthetic resin film with a thermoplastic or thermosetting adhesive, etc. If the synthetic resin film satisfies the heat resistance when forming the metal bumps by the wire-bumps method and the chemical resistance when forming the metal bumps by the plating method,
There is no particular restriction on the material, and an appropriate material can be used, for example, a polyimide film, a polyethylene terephthalate film, a polyetherimide film, a polyethersulfone film, a polyphenylene sulfide film, a polyetheretherketone film, etc. Can be used. The thickness of this synthetic resin film is usually 10 to 150.
μm.

A heat-fusible polyimide can be used for the sealing resin layer, and the thickness is usually 10 to 150 μm. A polyimide having a glass transition temperature of 200 ° C. or lower is used as the heat-fusible polyimide, and the glass transition temperature is 200 ° C. among the polyimide structures represented by the following formulas (1) to (5).
The following are preferably used. However, equation (1)-
In (5), R ₁ represents any of the following,

Embedded image R _{2 is, -C 3 H 6 -, -} C 4 H 8 - or

Embedded image , R ₃ represents an aromatic silicon diamine residue, and Ar represents an aromatic tetracarboxylic acid residue. n is 1
Is a positive integer up to 100, and a and b are a + b = 10
A positive number satisfying the relationship of 0, and 0.3 ≦ a / a + b ≦
It has a relationship of 0.9. Formulas (1) to (5) all represent a random copolymer and a block copolymer.

Embedded image

After the encapsulating resin layer 3 is provided as described above, the inner electrode hole 221 is formed in the insulating film 11 and the encapsulating resin layer 3 as shown in FIG. For this perforation, generally, a drilling process, a laser etching process, etc. can be used, and particularly when the sealing resin layer and the insulating film are polyimide, a wet drilling method such as alkali etching can be used. It is also possible to use photosensitive polyimide and perforate it by exposure. After punching the inner electrode hole 221, as shown in FIG.
The conductor 21 on the bottom surface of the hole 221 is plated with metal to form the hole 221.
Is filled with metal 222. Examples of metals include gold, silver,
Nickel, copper, palladium, etc. can be used.

After the inner electrode hole 221 is filled with the metal 222 in this way, as shown in FIG. 2D, a metal bump 223 having a height of 10 to 150 μm is formed on the filled metal surface.
Then, the formation of the inner electrode 22 is completed. The metal bumps 223 can be formed by a method in which the tip of a gold wire, a copper wire, or a solder wire is melted into a spherical shape by using a wire bonder, and the molten spherical metal is welded to the filling metal surface. When a gold wire is used, the upper layer of the filling metal 222 is preferably nickel in order to prevent the copper routing conductor 21 from coming into contact with gold. It is also possible to form metal bumps on the filling metal surface by a method of raising metal by wet plating.

When forming a metal bump using a wire bonder, since the periphery of the hole 221 is a synthetic resin surface (sealing resin layer surface) having low wettability to the molten metal, adhesion of the molten metal around the hole is performed. It is possible to form a spherical metal bump having a large contact angle on the filled metal surface in an orderly manner. Further, when the metal bumps 223 are formed by the plating method, the filling metal 22 may be used in both electrolytic plating and electroless plating.
A metal bump can be formed orderly by using the exposed end face of 2 as a nucleus. After forming the inner electrode 22 in this way, as shown in FIG. 2E, the insulating layer 12 is provided on the printed surface of the lead conductor 21, and further as shown in FIG. An outer electrode hole 231 is formed in the insulating layer 12, and as shown in FIG. 2G, the hole 231 is filled with the solder 232 by the above-described wire bonder or plating method.

When the encapsulating resin layer-equipped auxiliary wiring board piece A is manufactured as described above, as shown in FIG. 2C, the encapsulating resin layer-equipped auxiliary wiring board piece A (2 is (Auxiliary wiring board piece is shown) so that the metal bumps 223 of the inner electrode 22 are aligned with the electrodes 41 of the semiconductor chip 4, and a collective crimp connection such as a hot bar or a pulse heat or a single point bonder is performed. The individual electrode 41 of the semiconductor chip 4 and the inner electrode 22 of the auxiliary wiring board piece 2 are connected by individual thermocompression bonding
And the metal bumps 223 of
And the auxiliary wiring board piece 2 are joined electrically and mechanically.
When performing individual thermocompression bonding using a single point bonder, it is preferable to use ultrasonic bonding together to lower the thermocompression bonding temperature.

After the electrode 41 of the semiconductor chip 4 and the inner electrode 22 of the auxiliary wiring board piece 2 are connected,
The resin layer 3 for sealing and the resin layer 3 for sealing are fused by heating and pressurization to seal between the semiconductor chip 4 and the auxiliary wiring board piece 2. When the electrodes of the semiconductor chip and the inner electrodes of the auxiliary wiring board piece are collectively pressure-bonded by a hot bar, pulse heat, etc., heat fusion between the semiconductor chip and the sealing resin layer is performed by heating and pressurizing at that time. It is also possible to do simultaneously. It is also possible to use solder bumps for the metal bumps 223 of the inner electrode 22 and to join the auxiliary wiring board piece 2 and the semiconductor chip 4 by a reflow method. In this case, even if there is a slight deviation between the electrode 41 of the semiconductor chip 4 and the inner electrode 22 of the auxiliary wiring board piece 2, the surface tension of the molten solder automatically corrects it. It is unnecessary.

After the auxiliary wiring board piece 2 is bonded to the semiconductor chip 4 in this manner, the outer surface of the semiconductor chip 4 is sealed with the resin 5 as shown in FIG. In this case, transfer molding, potting, casting or the like can be used for resin sealing. After resin encapsulation in this way, solder bumps 233 are formed on the end faces of the filled metal of the outer electrode 23, as shown in FIG. To finish.

In the above, as a method for aligning the electrode 41 of the semiconductor chip 4 and the metal bump 223 of the inner electrode 22 of the auxiliary wiring board piece 2 at the stage shown in FIG. , An alignment bump 223a is attached to the dummy electrode 41a of the semiconductor chip 4, an alignment hole 221a is formed in the auxiliary wiring board piece 2, and the hole 221a and the alignment bump 223a are formed.
A method of fitting and can be used. In this case, the height of the alignment bump 223a is set to be slightly higher than that of the metal bump 223 of the inner electrode 22. For example, the height of the alignment bump 223a is set to 50 μm compared to 20 μm of the latter 223. Regarding the material of the alignment bump 223a, when the bump 223a is pressed against the electrode 41 of the semiconductor chip 4 and the inner metal bump 223 of the auxiliary wiring board piece 2 at the time of joining, a material that softens at the joining temperature is used. If it is not pressurized, it is not particularly limited. The hole diameter of the alignment hole 221a is set so that the positional deviation between the electrode 41 of the semiconductor chip 4 and the inner metal bump 223 of the auxiliary wiring board piece 2 is suppressed to 10% or less.

The semiconductor device according to the present invention as described above can be mounted by a reflow method. In this case, there is some deviation between the outer electrode of the semiconductor device and the conductor terminal of the mounted circuit board. Is also corrected by the surface tension of the molten solder. The size of the auxiliary wiring board piece 2 is equal to the plane dimension of the semiconductor chip 4 (usually 3 mm to 20 mm square) or 200% or less, preferably 130% or less of the plane dimension of the semiconductor chip 1. The outer electrodes 23, 2
The distance between the three is required to be as wide as possible within the plane dimension of the auxiliary wiring board piece 2 in order to prevent a solder bridge during soldering to the mounted circuit board, and is usually almost equal. It is considered as an interval.

An epoxy resin can be used as the sealing resin 5 on the outer surface of the semiconductor chip. Alternatively, the lateral edge portion or the back surface of the semiconductor chip 1 can be sealed by adhering an adhesive sheet (for example, an adhesive sheet using an epoxy-rubber resin as an adhesive). Furthermore, the semiconductor chip 1
Most of the back surface of is exposed to provide heat dissipation. It is also possible to fix a reinforcing frame (synthetic resin or metal) to the sealing resin layer on the outer surface of the semiconductor chip.

In order to improve the heat dissipation of the semiconductor chip,
As shown in (a) of FIG. 4, the back surface of the semiconductor chip 4 is completely exposed (5 is a sealing resin), and as shown in (b) of FIG. 4 or (c) of FIG. Or hi
Attaching the tospreader 61 (in FIG. 4B, the fin 61 is fixed by the heat conductive adhesive 62,
In FIG. 5C, the fin 61 is fixed by the sealing resin 5) is effective. Further, as shown in FIG. 4D, an inner metal filling hole 71 that does not contact the electrode of the semiconductor chip 4, an inner conductor 72 (not a lead conductor) thermally connected to the filling metal 71, and An outer metal filling hole 73 and a metal bump 74 that are thermally connected to the inner conductor 72 are provided, and the heat generated by the semiconductor chip 4 is radiated through these paths, as indicated by the dotted line in FIG. It is also effective to provide a heat dissipation dummy such as leaving the conductor (copper foil) 21a as much as possible with a predetermined insulating gap from the routing conductor 21 and using the remaining conductor 21a as a heat spreader.

In the above, the insulating layer (insulating film) 1
Increasing the adhesive force between 1 and the sealing resin layer 3 is effective in preventing moisture and ionic impurities from entering from this interface, and the reliability of the semiconductor device can be improved. Then, as is clear from the test result A described below, the surface tension (Zis
The critical surface tension calculated from the man plot is 35 m
If J / m ² or more, preferably 40 J / m ² or more is used, the adhesive force at the interface is 300 g / cm or more, more preferably 500 g / cm or more in 90 degree peel strength (room temperature, dry state). , Particularly preferably 1000 g / c
When it is at least m, the conductivity failure rate can be significantly reduced, and it is effective in improving the reliability of the semiconductor device (such a synthetic resin film has a surface tension of 35 mJ / m ² or less. It can be obtained by a chemical treatment such as an alkali solution treatment, a coupling agent treatment, a graft treatment, or a physical treatment such as corona discharge treatment, high frequency plasma treatment, or ion etching treatment.

[Experimental Results A] Table 1 (in Table 1, PI is polyimide, PET is polyethylene terephthalate, PP is polypropylene, and alkali treatment is dipping in 0.1 NKOH aqueous solution for 5 hours. Plasma) The treatment is performed in an oxygen gas atmosphere of 0.1 torr at 100
w (13.56 MHZ, 30 seconds glow discharge treatment). As the sealing resin 3, in Examples 1 to 5 and Comparative Examples 1 and 4, a heat-fusible polyimide represented by the following formula (6) was used, and Examples 6 to 1 were used.
0 and Comparative Examples 2 and 5 are heat-bondable polyimides represented by the following formula (7), and Examples 11 to 15 and Comparative Examples 3 and 6 are heat-bondable polyimides represented by the following formula (8). Each of the reactive polyimides was used. An inner electrode with a gold bump having a height of 50 μm was formed on an auxiliary wiring board piece (same size as the chip) using the supporting film and the heat-fusible polyimide, and the inner electrode had a thickness of 0.375 mm and a side length of 15. A 0 mm square semiconductor chip for reliability evaluation was joined to an auxiliary wiring board piece at 350 ° C., and a resin-sealed CSP with an outer dimension of 0.550 mm and a side length of 17.0 mm was used in Examples 1 to 15,
It was created as Comparative Examples 1 to 6. For these examples and comparative examples, the 90-degree peel strength and the conductivity failure rate after 200 hours in the 121 ° C. saturated steam pressure cooker test were measured.

[Chemical 4]

In order to increase the adhesive force between the insulating layer (insulating film) 11 and the sealing resin layer 3, as is apparent from the experimental result B described below, the entire surface of the insulating film is 0.0.
It is also effective to form unevenness having a diameter of 05 μm to 0.5 μm. [Experimental result B] The film having the thickness and the material shown in Table 3 was subjected to the surface treatment (in Table 3, the ion etching was performed in a nitrogen gas atmosphere at a high frequency of 3x10E-3 torr and 13.56MHZ for 200w for 5 minutes. 3 to xylene
Soak for hours. Alkaline treatment is 5
Soak for hours. UV treatment is 100w of UV irradiation. Corona treatment is 1200MHz, 33w, 1 minute low frequency corona irradiation. ), And what made the surface uneven | corrugated was made into the support film. Further, as the sealing resin 3, in Examples 1 ′ to 7 ′ and Comparative Examples 1 ′, 4 ′, and 7 ′, the heat-fusible polyimide represented by the above formula (1) was used, and Example 7 ′ was used. ˜19 ′ and Comparative Examples 2 ′, 5 ′, and 8 ′, the heat-fusible polyimide represented by the following formula (2) is used in Example 20 ′ and Comparative Examples 3 ′, 6 ′, and 9 ′. The heat fusible polyimides represented by the formula (3) were used respectively. An inner electrode with a gold bump having a height of 50 μm was formed on an auxiliary wiring board piece (same size as the chip) using the supporting film and the heat-fusible polyimide, and the inner electrode had a thickness of 0.375 mm and a side length of 15.
A 0 mm square semiconductor chip for reliability evaluation is bonded to an auxiliary wiring board piece at 350 ° C., and the outer dimension is 0.550 m.
A resin-encapsulated CSP having a length of m and a side length of 17.0 mm was prepared as Examples 1 ′ to 20 ′ and Comparative Examples 1 ′ to 9 ′. With respect to these examples and comparative examples, the 90-degree peel strength and the above-mentioned conductivity failure rate were measured, and the results are shown in Table 4.

The auxiliary wiring board piece 2 may have a multi-layer structure as shown in FIG. In FIG. 5, a pair of the electrode 41 of the semiconductor chip 4 and the conductor end 210 of the mounted circuit board to be electrically connected to the electrode 42 corresponds to the lead conductor 21 of one layer. A hole 221 facing the electrode 41 is provided in the insulating laminated layer 1, the hole 221 is filled with a metal 222, and a metal bump 223 is formed on the top surface of the filled metal 222 to form the inner electrode 22 for the one leading conductor 21. Has been formed. In addition, a hole 231 facing the one conductor end 210 of the mounted circuit board to be electrically connected to the one semiconductor chip electrode 41 from the one leading conductor 21 is provided in the insulating laminated layer 1, and the hole 231 is filled with the metal 232. Then, the metal bump 233 is formed on the top surface of the filling metal 232, and the outer electrode 23 for the one leading conductor 21 is formed. In FIG. 5, 3 indicates a sealing resin layer.

FIGS. 6A to 6H show another method of manufacturing a semiconductor device according to the present invention. In this manufacturing method, first, as shown in FIG. 6A, the lead conductor 21 is formed by printing on one surface of the insulating film 12, and the sealing resin layer 3 is provided on the printed surface. Then
As shown in FIG. 6B, the inner electrode hole 221 is formed in the sealing resin layer 3. After forming the inner electrode hole 221, as shown in FIG. 6C, the conductor 21 on the bottom surface of the hole 221 is plated with a metal, and the hole 221 is filled with the metal 222. In this way, the metal 222 is inserted into the inner electrode hole 221.
After the filling, the metal bumps 222 having a height of 10 to 150 μm are formed on the surface of the filled metal 222 as shown in FIG.
3 is formed, and the formation of the inner electrode 22 is completed. After forming the inner electrode 22 in this manner, as shown in FIG. 6E, an outer electrode hole 231 is formed in the insulating layer 12, and further, as shown in FIG. Then, the hole 231 is filled with the solder 232 by the above-described wire bonder to manufacture the auxiliary wiring board piece A with the resin layer for sealing.

In this way, the auxiliary wiring board piece A with a sealing resin layer (three sealing resin layers, 2 shows auxiliary wiring board pieces respectively) is manufactured, and as shown in FIG. As shown
The auxiliary wiring board piece 2 is aligned so that the metal bumps 223 of the inner electrodes 22 are aligned with the electrodes 41 of the semiconductor chip 4, and the individual thermocompression bonding is performed by a collective crimp connection such as a hot bar or a pulse heat or a single point bonder. By connection, the electrode 41 of the semiconductor chip 4 and the metal bump 223 of the inner electrode 22 of the auxiliary wiring board piece 2 are metal-to-metal bonded, and the semiconductor chip 4 and the auxiliary wiring board piece 2 are electrically and mechanically bonded.

In this way, the electrode 41 of the semiconductor chip 4 is
After connecting with the inner electrode 22 of the auxiliary wiring board piece 2,
The semiconductor chip 4 and the sealing resin layer 3 are fused by heating and pressurizing to seal between the semiconductor chip and the auxiliary wiring board piece. When the electrodes of the semiconductor chip and the inner electrodes of the auxiliary wiring board piece are collectively pressure-bonded by a hot bar, pulse heat, etc., heat fusion between the semiconductor chip and the sealing resin layer is performed by heating and pressurizing at that time. It is also possible to do simultaneously. After the auxiliary wiring board piece 2 is bonded to the semiconductor chip 4 in this manner, the outer surface of the semiconductor chip 4 is sealed with the resin 5 as shown in FIG. Filling metal 23
Solder bumps 233 are formed on the two end faces, and the manufacture up to the package process of the semiconductor device is completed.

It is advantageous in terms of production efficiency to carry out the present invention by a film carrier method. FIG. 7 shows (a) of FIG.
2 shows a film carrier used when the method of manufacturing a semiconductor device according to the present invention shown in FIG. In FIG. 7, 1
Reference numerals 1 and 12 are insulating films, and 3 is a sealing resin layer provided on the insulating film 11, for example, a heat-fusible polyimide layer. P, ... Are a plurality of wiring groups of the same pattern, which are provided at predetermined intervals in the longitudinal direction of the film carrier, and one wiring pattern corresponds to one semiconductor chip. , Each wiring pattern has a routing conductor 21, an inner electrode 22, and an outer electrode 23 sandwiched between the insulating layers 11 and 12.
The inner electrode 22 is provided around the insulating layer 11 and the encapsulating resin layer 3, and the hole 221 is formed so as to face the electrode side of the semiconductor chip from the conductor 21, the metal 222 filled in the hole 221 and the hole 221. 221 and the metal bumps 223 formed so as to project from the outer electrode 221.
2 and a metal 232 filled in the hole 231.

In order to carry out the method of manufacturing a semiconductor device according to the present invention shown in FIGS. 2A to 2B by the film carrier method, the film carrier shown in FIG. The semiconductor chip is mounted in the mounting station and the electrode of the chip is connected to the inner electrode of the wiring pattern, and at the time of this connection or in the next heating / pressing station, the semiconductor chip and the sealing resin. The layers are heat-sealed, and the outer surface of the mounted semiconductor chip is resin-sealed by transfer molding, potting, casting, etc. Finally, the film carrier is punched out around the semiconductor chip and the package auxiliary wiring A semiconductor chip with a plate piece is obtained, and the manufacturing of the semiconductor device up to the packaging step is completed.

[0031]

According to the present invention, a printed wiring pattern comprising an inner electrode connected to an electrode of a semiconductor chip, an outer electrode connected to a conductor end of a mounted circuit board, and a lead conductor extending between these electrodes. Apply a chip-sized auxiliary wiring board piece having a solder to the electrode-side surface of the semiconductor chip,
For the semiconductor device that connects the inner electrode of the auxiliary wiring board piece and the electrode of the semiconductor chip, the sealing between the semiconductor chip and the auxiliary wiring board piece is performed by a simple operation such as heating and pressurizing with a press. It is possible to surely carry out the process without entrapment, and it is possible to efficiently manufacture a reliable semiconductor device with the film carrier.

[Table 1]

[Table 2]

[Table 3]

[Table 4]

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing an example of an auxiliary wiring board with a sealing resin layer used in the present invention.

FIG. 2 is an explanatory view showing an embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is an explanatory diagram showing an example of a semiconductor device manufactured by the present invention.

FIG. 4 is an explanatory view showing a different example of a semiconductor device different from the above manufactured by the present invention.

FIG. 5 is an explanatory view showing an example of a semiconductor device manufactured by the present invention, which is different from the above.

FIG. 6 is an explanatory view showing another embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 7 is an explanatory diagram showing an example of a film carrier used in the method for manufacturing a semiconductor device according to the present invention.

FIG. 8 is an explanatory diagram showing a known package semiconductor device having a chip size.

[Explanation of symbols]

 11 Insulating Layer 12 Insulating Layer 2 Auxiliary Wiring Board Piece 21 Routing Conductor 22 Inner Electrode 221 Hole 222 Filling Metal 223 Metal Bump 23 Outer Electrode 231 Hole 232 Filling Metal 3 Sealing Resin Layer 4 Semiconductor Chip 41 Semiconductor Chip Electrode

Front page continuation (72) Inventor Hideyuki Usui 1-2 1-2 Shimohozumi, Ibaraki City, Osaka Prefecture Nitto Denko Corporation (72) Nobuhiko Yoshio 1-2 1-2 Shimohozumi, Ibaraki City, Osaka Nitto Denko Stock In-house (72) Inventor Kuki Ito 1-2 1-2 Shimohozumi, Ibaraki City, Osaka Prefecture Nitto Denko Corporation

Claims (6)

[Claims] 1. A wiring pattern comprising an inner electrode connected to an electrode of a semiconductor chip, an outer electrode connected to a conductor end of a mounted circuit board, and a lead conductor extending between these electrodes.
A resin layer for encapsulation is provided in advance on the inner electrode side surface of the auxiliary wiring board piece having a semiconductor chip, and the electrode of the semiconductor chip is connected to the inner electrode of the auxiliary wiring board piece. A method for manufacturing a semiconductor device, characterized in that the electrode side surface of the is fused to the sealing resin layer. 2. The auxiliary wiring board piece has an insulating layer sandwiching the routed conductor, and is routed to the insulating layer on the semiconductor chip side and the sealing resin layer on the insulating layer among these two insulating layers. The conductor is provided with a hole facing the electrode of the semiconductor chip, the metal filled in the hole and the metal bump formed so as to project from the hole constitute an inner electrode, and the outer electrode is provided with a hole in another insulating layer. The method of manufacturing a semiconductor device according to claim 1, wherein the hole is formed of a metal filled in the hole. 3. A wiring comprising a plastic tape base material, an inner electrode connected to an electrode of a semiconductor chip, an outer electrode connected to a conductor end of a mounted circuit board, and a lead conductor extending between these electrodes. A plurality of patterns are provided at predetermined intervals in the tape longitudinal direction, and a film carrier in which a sealing resin layer is preliminarily provided on the surface of the inner electrode except the inner electrode is manufactured. The electrodes of the semiconductor chip are connected to the inner electrodes of each wiring pattern, and the surface of the semiconductor chip on the electrode side is fused to the above-mentioned sealing resin layer, after which the film carrier is placed around the semiconductor chip. A method for manufacturing a semiconductor device, which comprises punching. 4. The routing conductor has an insulating layer sandwiching the routing conductor, and the insulating conductor on both sides of the insulating layer on the semiconductor chip side and the sealing resin layer on the insulating layer is provided from the routing conductor. A hole facing the electrode of the semiconductor chip is provided, the metal filled in the hole and a metal bump formed so as to project from the hole form an inner electrode, and the outer electrode has a hole provided in another insulating layer. The method of manufacturing a semiconductor device according to claim 3, wherein the hole is formed of a metal. 5. The semiconductor device according to claim 1, wherein the electrode of the semiconductor chip is connected to the inner electrode of the wiring pattern, and at the same time, the electrode-side surface of the semiconductor chip is fused to the sealing resin layer. Manufacturing method. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the sealing resin layer is a heat-meltable polyimide.