JPH08264537A - Semiconductor device and monitoring method therefor - Google Patents

Abstract

PURPOSE: To facilitate the monitoring by providing a contact connecting with a second layer interconnection such that the contact can be monitored on the substrate. CONSTITUTION: In a device having three layer interconnection structure, a contact 3 is made in a signal line using a second layer interconnection 1 when layout is designed. Consequently, the waveform of second layer interconnection 1 can be monitored on a third layer interconnection 2. In other words, measurement by means of a picoprobe A using a convenient tester or measurement by means of an electron beam B using an EB tester can be carried out on the third layer interconnection 2. Consequently, the efficiency is enhanced in the analysis of defect using the EB tester or the convenient tester. According to the invention, the time required for machining causes no delay in the monitoring of signal line which can thereby be carried out conveniently.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a semiconductor device monitoring method. INDUSTRIAL APPLICABILITY The present invention can be suitably used for a semiconductor device in which wiring functions as a signal line, for example,
It can be used as a storage device.

[0002]

2. Description of the Related Art Regarding a semiconductor device in which wirings of one to three layers are formed in order from the substrate side and these function as signal lines, regarding the monitoring of the signal lines, in the prior art, Was done like. That is,
When monitoring the signal line on the two-layer wiring 1 shown in FIG. 4,
Since this cannot be directly monitored on the three-layer wiring 2, the wiring must be processed by FIB (focused ion beam) or the like as shown in FIG. I have to. (Note that FIG. 4 and FIG.
(A) is a cross-sectional view, and (b) is a configuration diagram viewed from a plane. Further, in FIG. 5, reference numeral 41 indicates window opening by FIB processing or the like).

Therefore, in the prior art, it takes a long time to process the FIB and the like, which causes a problem that the feedback to the process is delayed.

[0004]

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems of the prior art, and when monitoring a signal line, there is no delay in processing time or the like, and simple monitoring is possible. It is an object of the present invention to provide a semiconductor device and a method of monitoring the semiconductor device capable of performing the above.

[0005]

According to the present invention, there is provided a semiconductor device comprising:
In a semiconductor device in which at least two layers of wiring are formed on a substrate, a contact for connecting to an upper second layer wiring is provided, and the contact can be monitored on the substrate.

On the substrate, the first to third layers are arranged from the substrate side.
In the semiconductor device in which the layer wiring is formed, a contact for connecting to the second layer wiring is provided, and the contact can be monitored in the third layer wiring.

In the method for monitoring a semiconductor device of the present invention, at least two layers of wiring are formed on a substrate, and at least the upper second layer wiring serves as a signal line. A contact connected to the layer wiring is provided, and the contact can be monitored on the substrate.

Further, on the substrate, from the substrate side to the first layer to the third layer.
In a method of monitoring a semiconductor device in which a layer wiring is formed, and at least the second layer wiring functions as a signal line, a contact for connecting to the second layer wiring is provided, and the contact can be monitored in the third layer wiring. It was done.

[0009]

According to the present invention, since the second layer wiring can be monitored on the substrate or on the third layer wiring which is an upper layer thereof, the monitoring can be achieved without the need for window opening processing. Therefore, it becomes possible to monitor easily without causing inconvenience such as delay of feedback to the process.

[0010]

Embodiments of the present invention will be described below. However, as a matter of course, the present invention is not limited to the following examples.

Embodiment 1 In this embodiment, the present invention is applied to a three-layer structure device ram (in particular, a DRAM having a bit line BL and a word line WL in this embodiment).

FIG. 1 is a cross-sectional view of the principal part of a three-layer structure device ram according to the present embodiment produced by using the present invention, and FIG. 2 is a plan layout diagram thereof. The contact between the two-layer wiring and the three-layer wiring according to the present invention is provided in the portion of FIG. In FIG. 2, is a BL and BLB contact part, and is a WL contact part. FIG. 3 is an enlarged detailed view of a portion of the layout diagram of FIG. 2, and a portion indicated by reference numeral C is a waveform monitor bit line contact portion in the lower layer second layer wiring (A) wiring. (W) is shown.

That is, in this embodiment, as shown in FIG. 1, at least two layers of wiring (a second layer wiring 1 shown in the figure, and a first layer wiring which is not shown and is lower than this) are provided on the substrate.
In the semiconductor device in which is formed the contact 3, which is connected to the upper layer second layer wiring 1, is provided, and the contact can be monitored on the substrate.

Particularly, in this embodiment, the first to third layers are arranged from the substrate side.
A contact 3 for connecting to the second layer wiring 1 on which the layer wiring is formed is provided, and the contact 3 can be monitored in the third layer wiring 2.

In this embodiment, the wirings of the first to third layers serve as signal lines.

Since the semiconductor device of this embodiment has the above structure, the contact 3 connected to the upper second layer wiring 1
This can be monitored on the substrate.

Particularly, in this embodiment, the contact is constructed so that it can be monitored by the three-layer wiring.

This embodiment will be described in more detail below.
It is as follows. In the present embodiment, in the three-layer wiring structure device, the contact 3 is installed on the signal line using the second layer wiring 1 at the time of layout design. As a result, the waveform monitor of the second layer wiring 1 becomes possible on the third layer wiring 2.

Therefore, as shown in FIG. 1, the measurement with the pico probe A by the simple tester or the measurement with the electron beam B by the EB tester is possible on the three-layer wiring 2. As a result, the failure analysis efficiency using the EB tester and the simple tester is improved. In addition, it leads to vertical start-up of the process.

In the present embodiment, the contact 3 is formed through the interlayer film 4 between the second layer wiring 1 and the third layer wiring 2 (see FIG. 1), which is, for example, photolithography technique and etching technique. Can be formed by a method of forming an opening in the interlayer film 4 by using, and burying W therein.

In FIG. 2, reference numeral 51 is a memory cell, 52 is a precharge section, 53 is a space amplifier section, 54 is an equalize section, and 55 is a word line driver.

According to the present embodiment, the following advantages can be obtained when it is necessary to monitor the waveforms of word lines and bit lines in design verification, defect analysis, and the like. First, the signal line can be confirmed on the monitor section regardless of the presence or absence of the third layer wiring. Secondly, when observing waveforms with a simple tester,
Interlayer film etching between the third layer and the second layer is unnecessary. Thirdly, when the waveform is observed by the EB tester, the influence (charge up) due to the interlayer film is eliminated, and the waveform can be confirmed more accurately.

As described above, the structure of this embodiment can improve the accuracy of design verification and speed up failure analysis.

[0024]

As described above, according to the semiconductor device and the method of monitoring the semiconductor device of the present invention, when the signal line is monitored, delay does not occur due to processing time and the like, and the monitoring can be performed easily. It will be possible.

[Brief description of drawings]

FIG. 1 is a diagram showing a cross section of a main part of a first embodiment of the present invention.

FIG. 2 is a diagram showing a planar layout of the first embodiment of the present invention.

FIG. 3 is an enlarged view of a main part of a planar layout according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a conventional technique and its problems.

FIG. 5 is a diagram showing a conventional technique and its problems.

[Explanation of symbols]

 1 Second Layer Wiring 2 Third Layer Wiring 3 Contact 4 Interlayer Film 51 Memory Cell 52 Precharge Section 53 Space Amplifier Section 54 Equalize Section 55 Word Line Driver

Claims (5)

[Claims] 1. A semiconductor device in which at least two layers of wiring are formed on a substrate, a contact for connecting to an upper second layer wiring is provided, and the contact can be monitored on the substrate. Semiconductor device. 2. A semiconductor device in which wirings of first to third layers are formed on a substrate from a substrate side, and a contact connecting to a second layer wiring is provided, and the contact can be monitored in the third layer wiring. A semiconductor device having the above-mentioned configuration. 3. The semiconductor device according to claim 1, wherein at least the second layer wiring functions as a signal line. 4. In a method of monitoring a semiconductor device, wherein at least two layers of wiring are formed on a substrate, and at least the upper second layer wiring serves as a signal line, and a contact for connecting to the upper second layer wiring is provided. A method for monitoring a semiconductor device, wherein the contact is configured to be monitorable on a substrate. 5. A method of monitoring a semiconductor device, wherein wirings of first to third layers are formed on a substrate from the side of the substrate, and at least the second layer wiring functions as a signal line in a monitoring method of a semiconductor device. A method of monitoring a semiconductor device, wherein a contact to be connected is provided, and the contact can be monitored by a three-layer wiring.