JPH08263433A - Data bus controller - Google Patents

Abstract

PURPOSE: To transfer data while varying its bit length corresponding to a quantity of required information in the case of serial data transfer. CONSTITUTION: A transmission channel of a data bus controller is composed of a controller 3 for controlling the transfer of transmissive data stored in a memory 2, compression circuit 8 for compressing the transmissive data set to a register 4, bit counter 7 for setting the bit length of the compressed transmissive data, and transmission circuit 5 for transmitting the compressed data onto a data bus 1. Besides, its reception channel is composed of a reception circuit 6 for receiving serial data from the data bus 1 and a compression circuit 8 for restoring the compressed data and storing them in a register 4. When transferring data onto the data bus in the case of serial data transfer, those data are transferred after its number of bits is shortened so that the time for transferring data can be shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data bus control device which enables variable bit lengths of transfer data to be transferred depending on the amount of information required in serial data transfer.

[0002]

2. Description of the Related Art FIG. 7 shows a conventional data bus controller, in which 1 is a data bus, 2 is a memory for storing transfer data, 3 is a controller for controlling data transfer, and 4 is transfer data. A register for storing 5 is a transmitting circuit for transmitting the transfer data onto the data bus, and 6 is a receiving circuit for receiving the transfer data from the data bus.

The conventional data bus controller is constructed as described above, a series of data to be transmitted is stored in the memory 2, and the transmission data is read from the memory 2 and set in the register 4. The transmission data set in the register 4 is converted into serial data by the transmission circuit 5 and transmitted to the data bus 1. The serial data transferred onto the data bus 1 is received by the receiving circuit 6, converted into parallel data, stored in the register 4, and then stored in the memory 2.

[0004]

In the above data bus control device, the bit length of transfer data is fixed,
Depending on the information data to be transferred, even the unnecessary bits are transferred, so that there is a problem that the transfer time increases as the data amount increases.

The present invention has been made in order to solve the above problems, and it is possible to obtain the effective bit length of transfer data.
An object of the present invention is to obtain a data bus control device that can shorten the data transfer time by making the bit length during data transfer variable.

[0006]

In the data bus control device according to the first embodiment of the present invention, the transmission channel serializes data having only valid bits on the data bus by presetting the effective bit length of the transmission data.・ Send as data. On the other hand, the receiving channel recognizes the set effective bit length in advance and then receives the serial data and stores it in the memory.

In the data bus control device according to the second embodiment of the present invention, the transmission channel is related to the transmission data,
Data is compressed on the data bus by setting the effective bit length of the compressed data.
Send as data. On the other hand, the reception channel recognizes the effective bit length of the reception data in advance, receives the serial data, restores the compressed reception data to the original, and stores the data in the memory.

In the data bus control device according to the third embodiment of the present invention, the transmission channel is related to the transmission data,
Data compression is performed and the effective bit length of the compressed data is determined. Also, the effective bit length of the compressed data is determined by different methods, the data bit numbers of both are compared, and the transfer bit number The data having the smaller value is selected and the data is transmitted as serial data on the data bus. On the other hand, the reception channel recognizes the effective bit length of the reception data in advance, receives the serial data, restores the compressed reception data to the original, and stores the data in the memory.

In the data bus control device according to the fourth embodiment of the present invention, the reception channel is related to the reception data,
The effective bit length is recognized in advance, serial data is received, the compressed received data is restored, and the data is stored in the memory. On the other hand, with respect to the transmission data, the transmission channel switches between transmitting data on the compressed data bus and transmitting the compressed data received through the reception channel directly on the data bus by the selector, Data is transmitted as serial data on the data bus.

[0010]

According to the first embodiment of the present invention, by presetting the bit length of data transferred as serial data on the data bus, only the bits required as information can be transferred. It is possible to shorten the transfer time.

According to the second embodiment of the present invention, the number of bits required for information is reduced by compressing the data transferred as serial data on the data bus and setting the bit length. Therefore, the transfer time can be shortened.

According to the third embodiment of the present invention, the data to be transferred is compressed to obtain its bit length, and the data to be transferred by another method is compressed to obtain its bit length, and both data are compressed. By comparing the subsequent bit lengths and transferring the data with the shorter bit length as serial data on the data bus, the number of bits required for information can be reduced and the transfer time can be reduced. It is possible to shorten.

According to the fourth embodiment of the present invention, when data is transferred between terminal devices via a computer, first one terminal device transfers the data to the computer and then the computer transfers the data to the other terminal device. Need to transfer. At this time, even when data is received in a compressed form from the terminal device on the transmitting side, the compressed data is restored on the computer, stored in the memory, then taken out from the memory, compressed again, and then the terminal device on the receiving side. By transmitting the data in a compressed form to the receiving side terminal device instead of transmitting it to the terminal device, the recompression process can be omitted and the transfer time can be shortened.

[0014]

【Example】

Embodiment 1 FIG. 1 is a block diagram showing an embodiment of the present invention, in which 1 is a data bus, 2 is a memory for storing transfer data, 3 is a controller for controlling data transfer, and 4 is transfer data. A register for storing, 5 is a transmission circuit for transmitting transfer data onto the data bus 1, and 6 is the data bus 1
The receiving circuit 7 receives the transfer data from, and 7 is a bit counter for counting the bit length of the transfer data.

Next, the operation will be described. A series of data to be transmitted is stored in the memory 2, and the data to be transmitted is read from the memory 2 and set in the register 4. Only valid bits of the transmission data set in the register 4 are serialized by the transmission circuit 5 by the controller 3.
It is converted into data and transmitted on the data bus 1. At this time, the bit length to be transmitted is set in the bit counter 7 by the controller 3 to control the number of transmission bits.

The serial data transferred onto the data bus 1 is received by the receiving circuit 6, converted into parallel data, set in the register 4, and stored in the memory 2. At this time, the bit length of the received data is counted by the bit counter 7, and when the data is stored in the memory 2 from the register 4, the data other than the valid bit is added and stored in the memory 2.

Embodiment 2 FIG. 2 is a block diagram showing an embodiment of the present invention, in which 1 is a data bus, 2 is a memory for storing transfer data, 3 is a controller for controlling data transfer, and 4 is a controller. A register for storing the transfer data, 5 is a transmission circuit for transmitting the transfer data to the data bus 1, and 6 is the data bus 1
Is a receiving circuit for receiving the transfer data from the device, 7 is a bit counter for counting the bit length of the transfer data, and 8 is a compression circuit for compressing the transfer data.

Next, the operation will be described. A series of data to be transmitted is stored in the memory 2, and the data to be transmitted is read from the memory 2 and set in the register 4. The transmission data set in the register 4 is compressed by the compression circuit 8 to calculate the number of data bits after compression. The compressed data is converted into serial data by the transmission circuit 5 and transmitted on the data bus 1. At this time, the bit length of the data to be transmitted after data compression is set in the bit counter 7 by the controller 3 to control the number of transmission bits.

The serial data transferred on the data bus 1 is received by the receiving circuit 6, converted into parallel data, set in the register 4, and stored in the memory 2. At this time, when the bit length of the received data is counted by the bit counter 7 and stored in the memory 2 from the register 4, the compressed data is restored by the compression circuit 8 and stored in the memory 2.

Third Embodiment FIG. 3 is a block diagram showing an embodiment of the present invention. In the figure, 1 is a data bus, 2 is a memory for storing transfer data, 3 is a controller for controlling data transfer, and 4 is a controller. A register for storing the transfer data, 5 is a transmission circuit for transmitting the transfer data to the data bus 1, and 6 is the data bus 1
Is a receiving circuit for receiving the transfer data from the device, 7 is a bit counter for counting the bit length of the transfer data, 8 is a compression circuit for compressing the transfer data, and 9 is a selector for selecting the transmission data.

Next, the operation will be described. A series of data to be transmitted is stored in the memory 2, and the data to be transmitted is read from the memory 2 and set in the register 4. The transmission data set in the register 4 is compressed by the compression circuit 8 to calculate the number of data bits after compression. The method of reading data from the memory 2 to the register 4 is carried out by two different methods. The selector 9 selects the compressed data which is the output of the compression circuit 8 having the shorter bit length as a result of the data compression of the data of the register 4 read from the memory 2 by the compression circuit 8 by the two methods. Only the compressed bits are converted into serial data by the transmission circuit 5 and transmitted to the data bus 1. At this time, the bit length of the transmission data after data compression is set in the bit counter 7 by the controller 3 to control the number of transmission bits.

The serial data transferred onto the data bus 1 is received by the receiving circuit 6, converted into parallel data, set in the register 4, and stored in the memory 2. At this time, when the bit length of the received data is counted by the bit counter 7 and stored in the memory 2 from the register 4, the compressed data is restored by the compression circuit 8 and stored in the memory 2.

As the data compression method on the transmitting side, the transfer data stored in the memory 2 is considered as a block, and as shown in FIG. 4, a method of reading data in the horizontal direction and a method of reading data in the vertical direction are considered. To be When the register is stored on the receiving side, the information on the data compression direction is transferred together with the data to determine the method of decompressing the compressed data.

Embodiment 4 FIG. 5 is a block diagram showing an embodiment of the present invention, in which 1 is a data bus, 2 is a memory for storing transfer data, 3 is a controller for controlling data transfer, and 4 is a controller. A register for storing the transfer data, 5 is a transmission circuit for transmitting the transfer data to the data bus 1, and 6 is the data bus 1
Is a receiving circuit for receiving the transfer data from the device, 7 is a bit counter for counting the bit length of the transfer data, 8 is a compression circuit for compressing the transfer data, and 9 is a selector for selecting the transmission data.

Next, the operation will be described. A series of data to be transmitted is stored in the memory 2, and the data to be transmitted is read from the memory 2 and set in the register 4. The transmission data set in the register 4 is compressed by the compression circuit 8 to calculate the number of data bits after compression,
The compressed data is converted by the controller 3 into serial data by the transmission circuit 5 and transmitted to the data bus 1. At this time, the bit length of the data to be transmitted after data compression is set in the bit counter 7 by the controller 3 to control the number of transmission bits.

The serial data transferred on the data bus 1 is received by the receiving circuit 6, converted into parallel data, set in the register 4, and stored in the memory 2. At this time, when the bit length of the received data is counted by the bit counter 7 and stored in the memory 2 from the register 4, the compressed data is restored by the compression circuit 8 and stored in the memory 2.

The data bus control device 12 is used in the configuration shown in FIG. 6, and the data bus control device 12 in the computer 11 is connected to the terminal device 10 by the data bus 1 on a one-to-one basis. The bus controller 12 reads the data from the memory 2 and transmits the data to the terminal device 10. At the time of reception, the data bus control device 12 receives data from the terminal device 10 and stores the received data in the memory 2.
At this time, the transfer data is transferred using compressed data. When transferring data from the terminal device 10 to another terminal device 10,
If it is not necessary to store data in the memory 2 in the computer 11, the compressed serial data transferred from the terminal device 10 on the transmitting side onto the data bus 1 is received by the receiving circuit 6 and converted into parallel data. The output of the receiving circuit 6 is selected by the selector 9 on the receiving side capable of selecting the output data of the receiving circuit 6 and the transmission data at the time of normal transmission, and the output of the receiving circuit 6 is converted into serial data and transmitted to the data bus 1. By doing so, the data received from the transmitting side terminal device 10 is transmitted to the receiving side terminal device 10. In this transfer, the bit length of the transferred data is set by counting the bit length of the received data by the bit counter 7 on the receiving side and notifying the bit length to the bit counter 7 on the transmitting side.

[0028]

According to the first to fourth embodiments of the present invention, in serial data transfer, when the transfer data is transferred onto the data bus, the number of bits can be shortened before the data transfer. It has the effect of shortening the time.

[Brief description of drawings]

FIG. 1 is a first embodiment of a data bus control device according to the present invention.
FIG.

FIG. 2 is a second embodiment of the data bus control device according to the present invention.
FIG.

FIG. 3 is a third embodiment of the data bus control device according to the present invention.
FIG.

FIG. 4 is a diagram showing an example of a data read method according to a third embodiment.

FIG. 5 is a fourth embodiment of the data bus control device according to the present invention.
FIG.

FIG. 6 is a diagram showing a usage configuration of a data bus control device.

FIG. 7 is a diagram showing a conventional data bus control device.

[Explanation of symbols]

 1 data bus 2 memory 3 controller 4 register 5 transmitting circuit 6 receiving circuit 7 bit counter 8 compression circuit 9 selector 10 terminal device 11 computer 12 data bus control device

Claims (4)

[Claims] 1. A memory for storing transfer data, a register for storing transmission data, a transmission circuit for transmitting the transmission data set in the register as serial data on a data bus, and receiving serial data from the data bus. A data bus control device comprising a receiving circuit, a register for storing received data, a bit counter for counting the bit length of data to be transferred, and a controller for controlling the entire transfer. 2. A memory for storing transfer data, a register for storing transmission data, a compression circuit for compressing the transmission data set in the register, and transmitting the compressed transmission data as serial data on a data bus. A transmission circuit, a reception circuit that receives serial data from the data bus, a compression circuit that restores compressed reception data to its original state, a register that stores reception data, a bit counter that counts the bit length of the data to be transferred, and an entire transfer. A data bus control device comprising a cotton roller for controlling. 3. A memory for storing transfer data, a first register for reading and storing transmission data from the memory, a first compression circuit for compressing the transmission data set in the first register, and transmission data. A second register for reading and storing from the memory; a second compression circuit for compressing data set in the second register;
A selector that selects one of the outputs of the two compression circuits, a transmission circuit that transmits the compressed transmission data output from the selector as serial data on the data bus, and a reception circuit that receives the serial data from the data bus. , A data bus control characterized by comprising a compression circuit for restoring compressed received data to an original state, a register for storing the received data, a bit counter for counting the bit length of the data to be transferred, and a controller for controlling the entire transfer apparatus. 4. A memory for storing transfer data, a register for storing transmission data, a compression circuit for compressing transmission data set in the register, a selector for selecting compressed data and reception data, and a selector for the selector. A transmission circuit that transmits the compressed transmission data that is the output as serial data on the data bus, a reception circuit that receives the serial data from the data bus, a compression circuit that restores the compressed reception data to the original, and the reception data is stored Register, a bit that counts the bit length of the data to be transferred.
A data bus control device comprising a counter and a controller for controlling the entire transfer.