JPH08255863A - Lead frame, semiconductor device employing it, and manufacture thereof - Google Patents

Abstract

PURPOSE: To obtain a lead frame for mounting a semiconductor chip in a lead- on-chip system and a semiconductor device in which the manufacturing cost is reduced while preventing short circuit of the wire. CONSTITUTION: A stage 54 having a smaller size than the mounting surface of a semiconductor chip 55 is disposed at the lower part between the opposite inner end parts of the inner lead 53a of a lead 53. The inner lead 53a is located above the semiconductor chip 55 being mounted in the lead-on-chip system.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame and a semiconductor device on which a semiconductor chip is mounted by a lead-on-chip method. In recent years, semiconductor devices have been packaged in a DIP (Dual In-line Packag) in order to improve mounting efficiency.
e) to SOP (Small Outline Package), SOJ (Sma
ll Outline J-Lead Package), QFP (Quad Flat Pac
Kage) and then TSOP (Thin-SOP). Further, further improvement in mounting efficiency is required, and therefore it is necessary to realize a high density package at low cost.

[0002]

2. Description of the Related Art Conventionally, LSI packages have been made highly functional,
The chip size tends to increase as the density increases. Therefore, a so-called LOC (Lead On Chip) method of arranging the leads above the semiconductor chip has been adopted as a method for reducing the size of the package and improving the mounting efficiency.

FIG. 8 is a sectional view showing the structure of a conventional lead-on-chip semiconductor device. A semiconductor device 11 shown in FIG. 8 uses a multi-lead frame composed of first and second lead frames 12 and 13. The first lead frame 12 has a predetermined number of leads 12a, The lead frame 13 has a stage 13a. The semiconductor chip 1 is mounted on the stage 13a of the second lead frame 13.
4 is mounted, and when the first lead frame 12 is overlaid, the tip portions of the leads 12a, which are inner leads, are located above the upper surface of the semiconductor chip 14.

That is, on the upper surface of the semiconductor chip 14,
An electrode pad (not shown in the figure) is formed on the substantially center line of the upper surface, and the lead 12a is formed near the electrode pad.
Is positioned, and electrical connection is made by the wire 15 between the electrode pad and the lead 12a. here,
As an assembly order in which such positioning and wire connection can be performed, the semiconductor chip 14 is diced on the second lead frame 13 and then the first lead frame 12 is overlapped by welding. Then, the package 16 is formed of the mold resin.

FIG. 9 shows the internal structure of another structure of the lead-on-chip. The semiconductor device 21 shown in FIG.
A semiconductor chip 24 similar to the semiconductor chip 14 described with reference to FIG. 8 is attached and mounted by, for example, a polyimide adhesive tape 23 in the vicinity of the inner tip that serves as an inner lead in the lead frame 22 in which only a predetermined number of leads 22a are formed. Then, the electrode pad of the semiconductor chip 24 and the lead 22a are electrically connected by the wire 25.

Next, FIG. 10 shows a sectional view of a conventional lead-on-chip semiconductor device using a multi-lead frame having a bus bar, and FIG. 11 shows a view for explaining the multi-lead frame of FIG. A semiconductor device 31 shown in FIG. 10 uses a multi-lead frame composed of first and second lead frames 32 and 33 as in the case of FIG. The first lead frame 32 is shown in FIG.
As shown in (A), a predetermined number of leads 35a, 35b are formed between the cradle 34a, 34b with their tips facing each other, and arranged so that the leads 35a, 35b on each side are surrounded by bus bar leads 36a, 36b, respectively. It

The second lead frame 33 is shown in FIG.
As shown in FIG. 1 (B), a stage 39 is formed between the gredols 37a and 37b via the support bars 38a and 38b. A state in which the first lead frame 32 is superimposed on the second lead frame 33 is shown in FIG. 11 (C). That is, the tips of the leads 35a and 35b of the first lead frame 32 and the bus bar leads 36a and 36b are arranged above the stage 39.

Therefore, referring back to FIG.
A semiconductor chip 40 similar to the semiconductor chip 14 described in FIG. 8 is mounted on the stage 39 of the lead frame 33. At this time, the leads 35a, 35b and the bus bar leads 36a, 36b are located above the vicinity of the electrode pads (not shown in the figure) on the semiconductor chip 40, and they are electrically connected to each other by the wires 41. Then, the package 42 is formed of the mold resin.

In the case of the LOC system, the semiconductor chip 4
Within 0, the power supply and the ground are not routed, but they are routed on the lead frame.
36b is formed on the first lead frame 32.

[0010]

However, the semiconductor device 11 of the semiconductor system of the lead-on-chip system shown in FIG. 8 uses the first and second lead frames 12 and 13, resulting in high cost, and FIG. The lead-on-chip type semiconductor device 21 shown in (1) has a problem that the cost of the adhesive tape for mounting the semiconductor chip 24 is high and the cost is high as a whole.

On the other hand, the lead-on-chip type semiconductor device 31 shown in FIG. 10 is a semiconductor chip 40 as a multi-lead frame having bus bar leads 36a and 36b.
When connecting the leads 35a and 35b with the wire 41, the wires are wired over the bus bar leads 36a and 36b, so that there is a problem that a wire short circuit may occur during bonding or in resin mode.

Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide a lead frame and a semiconductor device which can reduce the cost and prevent the wire short circuit.

[0013]

According to a first aspect of the present invention, there is provided a predetermined number of lead portions which are positioned above the mounted semiconductor chip so that their inner tips are opposed to each other at a predetermined interval and are electrically connected to the semiconductor chip. And a stage part formed below the inner ends of the lead parts that face each other and having a smaller size than the mounting surface of the semiconductor chip, thereby forming a lead frame.

According to a second aspect, the lead frame according to the first aspect, the semiconductor chip mounted on the stage portion of the lead frame, and the connection for electrically connecting the semiconductor chip and the lead portion of the lead frame. A semiconductor device is configured to include a means and a package portion that covers the periphery of the semiconductor chip and forms a part of each lead portion of the lead frame by extending to the outside.

According to a third aspect of the present invention, a tape-shaped adhesive member is interposed between the semiconductor chip according to the second aspect and the stage portion of the lead frame on which the semiconductor chip is mounted.
According to a fourth aspect of the present invention, when mounting the semiconductor chip on the stage portion of the lead frame according to the first aspect, the semiconductor chip is tilted from between inner ends of the lead portions of the lead frame facing each other, and the stage of the lead frame is inclined. The method of manufacturing a semiconductor device includes a step of inserting the semiconductor chip on the side of the stage and a step of horizontally positioning the semiconductor chip inserted on the side of the stage portion of the lead frame on the stage portion.

According to a fifth aspect, in mounting the semiconductor chip on the stage portion of the lead frame according to the first aspect,
Inserting the semiconductor chip in a substantially horizontal state from between the lead portion of the lead frame and the stage portion;
A method of manufacturing a semiconductor device is configured including a step of positioning the inserted semiconductor chip on the stage portion.

According to a sixth aspect of the present invention, a predetermined number of leads are superposed on the first frame portion and the first frame portion which is formed with the inner tip portions facing each other at a predetermined interval. A stage for mounting a semiconductor chip which is arranged below the opposing leads when the one frame portion is superposed, and for routing a predetermined electrical system formed in a predetermined number around the stage. A lead frame is configured to have a second frame portion having a bus portion.

According to a seventh aspect of the present invention, the predetermined number of leads formed on the first frame portion according to the sixth aspect include a lead for routing a predetermined electric system. In claim 8, the lead frame according to claim 6 or 7, a semiconductor chip mounted on the stage of the second lead frame in the lead frame, the semiconductor chip, the lead of the first frame portion, And connecting means for electrically connecting between the corresponding bus parts of the second frame part and the periphery of the semiconductor chip, and extending a part of each lead of the first frame part to the outside. And a package portion formed as described above, and a semiconductor device is configured.

[0019]

As described above, according to the first to third aspects of the invention, the stage having a size smaller than the mounting surface of the semiconductor chip for mounting the semiconductor chip below the inner tips of the lead portions facing each other at a predetermined interval. A semiconductor chip is mounted on a lead frame having a portion formed thereon, and a tape-shaped adhesive member is appropriately interposed on the stage portion of the lead frame, and electrical connection is performed by a connecting means to form a package portion. This makes it possible to form a single lead frame in the lead-on-chip system when the lead portion is located above the semiconductor chip, and a small amount of tape-shaped adhesive member that is appropriately used may be used. It is possible to reduce the cost of the lead frame and eventually the semiconductor device.

According to the invention of claim 4 or 5, with respect to the lead frame of claim 1, which is formed in a single structure, the semiconductor chip is inclined from the inner tip of the lead portion and inserted into the stage portion, or A semiconductor chip is inserted between the lead portion and the stage portion in a substantially horizontal state, and the semiconductor chip is positioned on the stage portion. This makes it possible to easily mount a semiconductor chip on a single lead-on-chip type lead frame, and to achieve cost reduction.

According to the present invention, the leads including the leads for routing the predetermined electric system are appropriately arranged on the first frame portion, and the stage and the predetermined electric system are routed on the second frame portion. And a semiconductor chip is mounted on the stage of the lead frame, and a corresponding predetermined portion is electrically connected by a connecting means to form a package portion. Accordingly, since the bus section is arranged on the stage side, it is possible to prevent a short circuit to the other in the electrical connection of the semiconductor chip in the read-on-chip method.

[0022]

FIG. 1 shows a configuration diagram of a first embodiment of the present invention. 1A is a vertical cross-sectional view of a semiconductor device, FIG.
FIG. 4 is a plan view of a lead frame used in a continuous arrangement state. A semiconductor device 51 shown in FIG. 1A is of a lead-on-chip type, and a lead frame 52 is composed of a lead 53 as a lead portion and a stage 54 as a stage portion, and a semiconductor chip 55 is provided on the stage 54. Is formed so that the tip portion of the inner lead 53a of the lead 53 is disposed above the semiconductor chip 55 when the semiconductor chip 55 is mounted.

Here, the lead frame 52 is shown in FIG.
As shown in (B), it is one semiconductor device of the continuous lead frame 61, and tie bars 63a and 63b are formed in a erected state between the cradle 62a and 62b at a predetermined interval. Leads 53 are formed. The leads 53 are on the stage 54 side, and the inner leads 53a are located inside the package portion, which will be described later, and the outer leads 53b are extended outside the package portion.

A predetermined number of stages 54 are provided between the cradle 62a and 62b (two stages 54 in FIG. 1B).
Is formed by being supported by the support bars 64a and 64b. The stage 54 is arranged such that the front end portions of the inner leads 53a of the leads 53 are located facing each other at a predetermined interval, and is formed in such a size that the entire area of the stage 54 on the plane can be recognized. That is, the size of the stage 54 is formed smaller than the mounting surface of the semiconductor chip 55 to be mounted. In this case, the distance between the tip portions of the inner leads 53a is set to a distance required to mount the semiconductor chip 55, which will be described later, in an inclined manner.

Then, a predetermined number of the lead frames 52 are continuously provided so that the continuous lead frame 61 is integrally formed of a single metal member. That is, since the size of the stage 54 is located between the opposing tips of the inner leads 53a, it can be formed of a single metal member. The continuous lead frame 61 is formed, for example, by etching or pressing a nickel alloy-based or copper alloy-based metal member. In this case, the stage 54 is the lead 53
On the other hand, it is formed at a step position of at least the thickness of the semiconductor chip 55, and when the continuous lead frame 61 is formed by pressing, it is performed at the same time.

Then, returning to FIG. 1 (A) and explaining,
The semiconductor chip 55 is mounted on the stage 54 with an adhesive tape 56 (may be an adhesive material such as silver paste) made of PI (polyimide), which is a tape-shaped adhesive member, interposed.
The semiconductor chip 55 has a predetermined number of electrode pads (at least the number of leads 53) on the center line in the lead arrangement direction on the upper surface.
It is formed (not shown in the figure, see FIG. 7), and is electrically connected by bonding with a wire 57 as a connecting means between the electrode pad and the corresponding inner lead 53a. In this state, unnecessary parts such as the cradle 62, 62b, the tie bars 63a, 63b, the support bars 64a, 64b of the continuous lead frame 61 of FIG. 1B are cut and removed.

Then, the package portion 58 is formed by packaging with a mold resin. The outer lead 53b of the lead 53 extends from the package portion 58 and is bent into a desired shape such as a lead insertion shape, a gull wing shape, or a J lead shape.

FIG. 2 shows an assembly process diagram of the chip-on of FIG. As shown in FIGS. 2A and 2B, the semiconductor chip 55 is inclined and inserted into the stage 54 side from between the opposing tip portions of the inner leads 53 of the leads 53. When the insertion of the semiconductor chip 55 into the stage 54 side is completed, the semiconductor chip 55 is brought into a horizontal state as shown in FIG. 2C, and the stage 54 as shown in FIG.
The position is slid to the regular position above. 2A to 2D, the adhesive tape 56 on the stage 54 is omitted. In this case, since the semiconductor chip 55 is slid, it may adhere when using a paste-like adhesive, and it is preferable to use the adhesive tape 56. This also applies to FIG.

Further, FIG. 3 shows another assembly configuration diagram of the chip-on of FIG. FIG. 3 shows the inner lead 5 of the lead 53.
3a and the lower stage 54 between the semiconductor chip 55
Is inserted in a substantially horizontal state and is slid in that state to position the semiconductor chip 55 at a regular position on the stage 54.

As shown in FIGS. 2 and 3, a lead 54 of the lead-on-chip system is mounted on a stage 54.
The semiconductor chip 55 can be easily positioned on top. Subsequently, FIG. 4 shows an explanatory view of another lead frame structure of the first embodiment. The lead frame 52 shown in FIG. 4 shows a case where the stage 54 is supported not by the cradle 62a, 62b but by the support bars 65a, 65b extended from the tie bars 63a, 63b. The structure is the same as that in FIG.

As shown in the first embodiment, the stage 5
By arranging 4 as a small size and arranging the whole area between the tip portions of the inner leads 53a which face each other, the lead frame 52 used in the lead-on-chip method can be constructed in a single structure, and the lead of the conventional two-sheet method can be used. The cost can be reduced as compared with the frame, and eventually the semiconductor device 51.
It is possible to reduce the cost. In this case, when mounting the semiconductor chip 55 on the stage 54, the adhesive tape 56 is used, but since the stage 54 has a small size and the amount of the adhesive tape 56 used is small, the cost is affected. Does not give.

Next, FIG. 5 shows a cross-sectional structural view of a second embodiment of the present invention. A semiconductor device 71 shown in FIG. 5 is of a lead-on-chip type and has a structure having a bus bar lead which is a bus section. In FIG. 5, the multi-lead frame 7 includes a first frame portion 73 having a predetermined number of leads 72 formed therein and a second frame portion 76 having the stage 74 and bus bar leads 75a and 75b formed therein.
7 is configured (described in FIG. 6).

A semiconductor chip 78 is mounted on the stage 74 by an adhesive material 78a such as silver paste (or an adhesive tape such as PI). Electrode pads 78b as shown in FIG. 7 to be described later are formed on the upper surface of the semiconductor chip 78 so as to correspond to at least the number of leads 72 in the lead arrangement direction. The electrode pads 78b and the semiconductor chips 78 in the leads 72 are formed. Inner lead 72a positioned above the
(Positioned in a package portion described later) is bonded and electrically connected by a wire 79 that is a connecting means. Further, a wire 79 electrically connects the predetermined inner lead 72a and the bus bar leads 75a and 75b.

Then, the package portion 80 is formed by covering the periphery of the semiconductor chip 78 (the inner leads 72a, the bus bar leads 75, etc.) with a molding resin. Outer leads (integral with the inner leads 72a) 72b of the leads 72 are extended from the package portion 80 and bent into a desired shape such as a gull wing shape.

FIG. 6 shows a block diagram of the multi-lead frame of the second embodiment. FIG. 6A shows the first frame portion 73, in which tie bars 82a and 82b are formed between the cradle 81a and 81b at a predetermined interval in a erected state, and a predetermined number of leads 72 are integrated with the tie bar 82a and 82b. Formed. The lead located between the tie bars 82a and 82b becomes the inner lead 72a, and the lead located outside is the outer lead 72b.

The first frame portion 73 is made of, for example, a nickel alloy or copper alloy metal member and is integrally formed by etching or pressing. Also, FIG. 6B shows the second frame portion 74, and the credor 83
The stage 74 is integrally formed by being supported by the support bars 84a and 84b between a and 83b, and the support bars 85a, 85b, 86a and 8 are provided on both sides of the stage 74.
The bus bar leads 75a and 75b are integrally formed by being supported by 6b. Like the first frame portion 73, the second frame portion 74 is integrally formed of a nickel alloy-based or copper alloy-based metal member by etching or pressing, and when pressing is performed as shown in FIG. The stage 74 and the bus bar leads 75a and 75b are simultaneously formed at desired step positions.

Then, as shown in FIG. 6C, the first
The frame portion 73 and the second frame portion 74 are welded together, for example.
Are overlaid by. Welding is on stage 74
This is performed after the semiconductor chip 78 is mounted on. There
FIG. 7 is an explanatory diagram of the wire bonding of the second embodiment.
Is shown. Here, the lead 72 (inner lead 72a)
Among them, the predetermined lead is the dummy lead 72a. ₁, 72a₂
Has a role as. This dummy lead 72a
₁, 72a ₂Is a power supply system or ground system as a predetermined electric system
For routing the bus bar leads 75a, 75
It has the same role as b. Then, the semiconductor chip 78
Of the corresponding electrode pad 78b and inner lead 72a of
Electrical connection by bonding the wire 79 between
To continue.

In this case, the dummy leads 72a ₁ and 72a
₂ is the corresponding electrode pad (power system or ground system) 7
8b and the wire 79 and the bus bar leads 75a and 75b by the wire 79. As described above, since other members such as bus bar leads do not exist in the vicinity when the electrical connection is made by the wire 79, it is possible to prevent the occurrence of wire short circuit.

[0039]

As described above, according to the inventions of claims 1 to 3, the semiconductor chip mounting surface for mounting the semiconductor chip is located below the inner ends of the lead portions facing each other at a predetermined interval. A lead frame having a small-sized stage section is formed, and a semiconductor chip is mounted on the stage section of the lead frame with a tape-shaped adhesive member interposed therebetween to electrically connect the package section by connecting means. By forming it, it is possible to form a single lead frame in the lead-on-chip method when the lead portion is located above the semiconductor chip, and a small amount of tape-shaped adhesive member that is appropriately used may be used. It is possible to reduce the cost of the lead frame and eventually the semiconductor device.

According to the fourth or fifth aspect of the invention, with respect to the lead frame of the first aspect, which is formed in a single piece, the semiconductor chip is inserted into the stage portion side while being inclined from between the inner ends of the lead portions. Alternatively, by inserting the semiconductor chip between the lead part and the stage part in a substantially horizontal state and positioning the semiconductor chip on the stage part, the semiconductor chip can be easily mounted on a single lead-on-chip type lead frame. Can be mounted, and cost reduction can be achieved.

According to the present invention, the leads including the leads for routing the predetermined electrical system are appropriately arranged in the first frame portion, and the stage and the predetermined electrical system are provided in the second frame portion. By forming a lead frame in which a bus portion for routing is arranged, a semiconductor chip is mounted on the stage of this lead frame, and a corresponding predetermined portion is electrically connected by a connecting means to form a package portion. Since the bus portion is arranged on the stage side, it is possible to prevent a short circuit to the other in the electrical connection of the semiconductor chip in the lead-on-chip system.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a first embodiment of the present invention.

FIG. 2 is a chip-on assembly process diagram of FIG. 1;

3 is another assembly configuration diagram of the chip-on of FIG. 1. FIG.

FIG. 4 is an explanatory diagram of another lead frame structure of the first embodiment.

FIG. 5 is a sectional configuration diagram of a second embodiment of the present invention.

FIG. 6 is a configuration diagram of a multi-lead frame according to a second embodiment.

FIG. 7 is an explanatory diagram of wire bonding according to the second embodiment.

FIG. 8 is a cross-sectional configuration diagram of a conventional lead-on-chip semiconductor device.

FIG. 9 is an internal configuration diagram of another structure of the lead-on-chip.

FIG. 10 is a cross-sectional configuration diagram of a lead-on-chip semiconductor device using a multi-lead frame having a conventional bus bar.

11 is an explanatory diagram of a configuration of the multi-lead frame of FIG.

[Explanation of symbols]

 51, 71 semiconductor device 52 lead frame 53, 72 lead 53a inner lead 53b outer lead 64, 74 stage 55, 78 semiconductor chip 56 adhesive tape 57, 79 wire 58, 80 package part 61 continuous lead frame 73 first frame part 75a , 75b Busbar lead 76 Second frame part 77 Multi-lead frame

Claims (8)

[Claims] 1. A predetermined number of lead portions which are located above the mounted semiconductor chip so as to face each other with their inner tips facing each other at a predetermined interval and are electrically connected to the semiconductor chips, and the inner tips where the lead portions face each other. A lead frame formed below the space between the semiconductor chips and having a size smaller than the mounting surface of the semiconductor chip. 2. The lead frame according to claim 1, a semiconductor chip mounted on a stage part of the lead frame, and a connecting means for electrically connecting the semiconductor chip and the lead part of the lead frame. A semiconductor device, comprising: a package part that covers the periphery of the semiconductor chip and forms a part of each lead part of the lead frame by extending to the outside. 3. A semiconductor device, wherein a tape-shaped adhesive member is interposed between the semiconductor chip according to claim 2 and a stage portion of the lead frame on which the semiconductor chip is mounted. 4. When mounting a semiconductor chip on the stage portion of the lead frame according to claim 1, the semiconductor chip is inclined from between the inner ends of the lead portions of the lead frame facing each other, and the stage of the lead frame is inclined. And a step of horizontally placing the semiconductor chip inserted on the side of the stage portion of the lead frame on the stage portion, and a step of inserting the semiconductor chip on the stage portion. 5. A step of inserting the semiconductor chip in a substantially horizontal state between a lead part of the lead frame and the stage part when mounting the semiconductor chip on the stage part of the lead frame according to claim 1. And a step of positioning the inserted semiconductor chip on the stage portion, the method of manufacturing a semiconductor device. 6. A first frame portion, wherein a predetermined number of leads are formed with their inner tip portions facing each other at a predetermined interval, and the first frame portion is superposed on the first frame portion.
A stage for mounting a semiconductor chip, which is arranged below the opposing leads when the first frame portions are overlapped with each other, and a predetermined electric system formed around the stage. Second with a bus section for
A lead frame, comprising: 7. The lead, wherein the predetermined number of leads formed on the first frame portion according to claim 6 includes a lead for routing a predetermined electric system. flame. 8. The lead frame according to claim 6, a semiconductor chip mounted on a stage of the second lead frame in the lead frame, the semiconductor chip, a lead of the first frame portion, And connecting means for making electrical connection between the corresponding bus parts of the second frame part, covering the periphery of the semiconductor chip, and extending a part of each lead of the first frame part to the outside. A semiconductor device comprising: a package portion formed by;