JPS59115551A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS59115551A
JPS59115551A JP57225210A JP22521082A JPS59115551A JP S59115551 A JPS59115551 A JP S59115551A JP 57225210 A JP57225210 A JP 57225210A JP 22521082 A JP22521082 A JP 22521082A JP S59115551 A JPS59115551 A JP S59115551A
Authority
JP
Japan
Prior art keywords
elements
resin sealing
lead
package
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57225210A
Other languages
Japanese (ja)
Inventor
Toshihiro Kato
加藤　俊博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP57225210A priority Critical patent/JPS59115551A/en
Publication of JPS59115551A publication Critical patent/JPS59115551A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To enhance the mounting density of a semiconductor device by adjacently forming resin seals for sealing semiconductor elements at the same lead-frame, bonding the frames from the boundary of them, superposing them as a package, drawing the first and second outer leads from the bottom as a dual line array. CONSTITUTION:Semiconductor elements 12a, 12b are die bonded at first and second element arranging units 11a, 11b by a lead-frame 11 in which the first and second units 11a, 11b are adjacently provided. Then, the end 11c of an inner lead and the elements 12a, 12b are connected via wirings 13. Thereafter, the elements 12a, 12b are sealed with resin in a transfer mold, seals 14a, 14b are then provided, bent and superposed at the center line A-A' of the seals 14a, 14b as a boundary with notches 15a, 15b as marks. In this manner, the elements 12a, 12b are opposed and folded, and the first and second outer leads 18a, 18b are drawn from the lower parts of the elements.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は芙装法の改良されたデュアルインライン型の
半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a dual in-line type semiconductor device using an improved mounting method.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

従来より、半導体素子のパッケージとして、いくつかの
型の樹脂封止型パッケージが用いられている。最も広（
用いられているのにＤＩＰ（Ｄｕａｌ　−Ｉｎ　−Ｌｉ
ｎｅ　−Ｐａｃｋａｇｅ　）や５ＩＰ（Ｓｉｎｇｌ　−
Ｉｎ　−Ｌｉｎｅ　−Ｐａｃｋａｇｅ　）がある。Conventionally, several types of resin-sealed packages have been used as packages for semiconductor devices. The widest (
DIP (Dual-In-Li)
ne-Package) and 5IP (Singl-Package) and 5IP (Singl-Package)
In-Line-Package).

ＤＩＰ型のものは半導体チップの収納された樹脂からな
る本体両側より規格化された２列のアウターリードが引
き出されているものであり、ＳＩＰ型のものは本体の底
面から一列に並んだアウターリードが引き出されたもの
である。The DIP type has two standardized rows of outer leads drawn out from both sides of the resin body in which the semiconductor chip is housed, while the SIP type has outer leads lined up in a row from the bottom of the body. is extracted.

このようなり　Ｉ　Ｐａ或いはＳＩＰ型の半導体装置は
プリント基板への実装が容易なため広く用いられている
が、冥装密度が十分でないという欠点があった。As described above, IPa or SIP type semiconductor devices are widely used because they can be easily mounted on a printed circuit board, but they have the disadvantage that the packaging density is not sufficient.

この他、半導体素子の収納された樹脂本体やアウターリ
ード等を薄く小さくしたフラットパッケージやミニフラ
ットパッケージ等も使用される。これらのパッケージで
は実装密度が向上されるものの、プリント基板上への実
装が困難であり、汎用性に欠ける。In addition, flat packages, mini flat packages, etc., in which the resin body containing the semiconductor element, outer leads, etc. are made thin and small are also used. Although these packages improve packaging density, they are difficult to mount on printed circuit boards and lack versatility.

また、１つのパッケージ内に２個以上の半導体チップ（
半導体素子）を収納したい場合もあるが、この場合には
ＤＩＰ型、ＳＩＰ型またフラットパッケージ型のいずれ
の場合でもパッケージの本体が大きくなり、実装上好ま
しくない。In addition, two or more semiconductor chips (
In some cases, it is desired to house a semiconductor device (semiconductor element), but in this case, the main body of the package becomes large regardless of whether it is a DIP type, a SIP type, or a flat package type, which is not preferable in terms of mounting.

このため、内部に半導体チップが収納されパッケージの
裏面にはんだ付可能な電極パッドが引き出され内部に半
導体チップが収納されたチップキャリアをマザーボード
に直接はんだ付して接続するチップキャリア方式の装置
がある。For this reason, there is a chip carrier type device in which a semiconductor chip is housed inside, a solderable electrode pad is pulled out from the back of the package, and the chip carrier with the semiconductor chip housed inside is connected directly to the motherboard by soldering. .

このチップキャリア方式のものは、１つのパッケージ内
に複舷個のチップを搭載でき、実装密度を大幅に向上で
きるが、マザーボードが高価であり、またアセンブリ（
組立）が困難である等の欠点がある。This chip carrier type allows multiple chips to be mounted in one package, greatly improving packaging density, but the motherboard is expensive and the assembly
There are disadvantages such as difficulty in assembly.

この他の手段としてＤＩＰ型のパッケージの背面にさら
にもう１個のＤＩＰ型のパッケージを２段に重ねたいわ
ゆるＰ　ｉｇｇｙ　−ｂａｃｋ　−ｐａｃｋａｇｅとい
う構造もある。この型のものは、コス・ト面では有利で
あるが実装密度的にはまだ不十分である。As another means, there is also a structure called a so-called Piggy-back-package in which another DIP-type package is stacked in two layers on the back side of a DIP-type package. Although this type is advantageous in terms of cost, it is still insufficient in terms of packaging density.

〔発明の目的〕[Purpose of the invention]

この発明は上記のような点に鑑みなされたもので、実装
コストの大幅な上昇を招くことなく、実装法が簡便であ
り、実装密度の向上した半導体装置を提供しようとする
ものである。The present invention has been made in view of the above points, and aims to provide a semiconductor device with a simple mounting method and improved packaging density without causing a significant increase in packaging costs.

〔発明の概要〕[Summary of the invention]

すなわちこの発明ζこ係る半導体装置では、同一リード
フレーム上の離間した位置に第１．第２の樹脂封止部を
形成し、少な（とも一方で半導体素子を封止するように
同一リードフレーム上の離間した位置に第１および第２
の樹脂封止部を形成し、上記第１．第２の樹脂封止部間
のリードフレームを中心に折り曲げ゛加工を施して、第
１．第２の樹脂封止部を重ね合わせ一体と成しパッケー
ジ本体とする。そしてこの本体底面すなわち重ねられた
第１および第２の樹脂封止部の底面からそれぞれ第１お
よび第２のアウターリードを引き出し、これらのアウタ
ーリード配列がデュアルインライン配列を成しているよ
うにしたものである。That is, in the semiconductor device according to the present invention, the first. A second resin sealing portion is formed, and a first and second resin sealing portion is formed at a spaced apart position on the same lead frame so that one side seals the semiconductor element.
A resin sealing portion is formed, and the resin sealing portion is formed as described above in the first step. The lead frame between the second resin sealing parts is bent and processed. The second resin sealing portion is overlaid and integrated to form a package body. Then, the first and second outer leads were drawn out from the bottom of the main body, that is, the bottom of the stacked first and second resin sealing parts, respectively, so that these outer leads were arranged in a dual in-line arrangement. It is something.

〔発明の実施例〕[Embodiments of the invention]

以下図面を参照してこの発明の一実施例を説明する。ま
ず、リードフレーム材となる金属板を第１図に示すよう
に打ち抜いて、破線１０枠内の１個分の半導体装置のリ
ードフレーム内に第１の素子配設部１２ａおよび第２の
素子配設部５　１２ｂの設けら第１たリードフレーム１
１を形成する。An embodiment of the present invention will be described below with reference to the drawings. First, a metal plate serving as a lead frame material is punched out as shown in FIG. The first lead frame 1 provided with the provision portion 5 12b
form 1.

続いて、このリードフレーム１１の第１および第２の素
子配設部１１ａ、ＩＺｂ上に半導体素子１２ａ、１２ｂ
をダイボンディングする。Subsequently, semiconductor devices 12a and 12b are placed on the first and second device placement portions 11a and IZb of this lead frame 11.
die bonding.

その後、ワイヤ１３を用いてインナーリードの先端１１
ｃと素子１２ａ、ｚ２ｂとを接続する。Then, using the wire 13, the tip 11 of the inner lead
c is connected to the elements 12a and z2b.

次いで、第２図（Ａ）　、　（Ｂ）の平面図および側面
図に示−すようにトランスファモールド技術を用いて第
１および第２の素子１２ａ、１２ｂをそれぞれ樹脂封止
し、それぞれ第１および第２の樹脂封止部１４ａ、１４
ｂを形成する。Next, as shown in the plan view and side view of FIGS. 2A and 2B, the first and second elements 12a and 12b are each resin-sealed using transfer molding technology, and the first and second elements 12a and 12b are respectively sealed with resin. and second resin sealing parts 14a, 14
form b.

ここで、上記リードフレーム１１を後工程において第１
および第２の樹脂封止部１４ａ。Here, the lead frame 11 is first
and second resin sealing part 14a.

ＪＪｂ間の中心線Ａ−ＡＩを中心にして曲げるため、パ
ッケージの方向を示すノツチ部１５ａ。Notch portion 15a indicates the direction of the package for bending around the center line A-AI between JJb.

１５ｂは中心線Ａ　−Ａ’に対して向い合った位置に設
ける。15b is provided at a position facing the center line A-A'.

次に、リードフレーム１１の不要な枠部分やタイバ一部
分を切り落とし、第１．第２の樹脂封止部１４ａ、１４
ｂ間の連結リード部１６において折り曲げ加工を行ない
、第３図に示すように第１および第２の樹脂封止部１４
ａ、１４ｂを重ねて固定し、パッケージ本体１７と成す
。Next, the unnecessary frame portion and tie bar portion of the lead frame 11 are cut off. Second resin sealing parts 14a, 14
A bending process is performed on the connecting lead portion 16 between the first and second resin sealing portions 14 as shown in FIG.
A and 14b are stacked and fixed to form a package body 17.

この後、適宜仕上げ工程を行い必要であれば、装置本体
１７の背面に露出した連結リード部１６の絶縁処理等を
行う。また、図の１８３゜１８ｂはそれぞれ第１．第２
の樹脂封止部１４ａ。Thereafter, finishing steps are performed as appropriate, and if necessary, the connection lead portion 16 exposed on the back side of the device main body 17 is insulated. Also, 183° 18b in the figure is the 1st. Second
The resin sealing part 14a.

１４ｂの底面から引き出さｎたデュアルイン配列の第１
．第２のアウターリード列である。The first of the dual-in array pulled out from the bottom of 14b.
．． This is the second outer lead row.

同、上記実施例では第１の樹脂封止部１４ａおよび第２
の樹脂封止部１４ｂ内にそれぞれ第１および第２の素子
１２ａ、Ｚ２ｂを収納する場合につき述べたが、必すし
も、第１．第２の封止部内にそれぞれ１個ずつ収納しな
くとも艮（、例えば一方でのみ素子を収納しても良い。Similarly, in the above embodiment, the first resin sealing part 14a and the second resin sealing part 14a
Although the case where the first and second elements 12a and Z2b are respectively housed in the resin sealing part 14b of the first element 1. It is not necessary to house each element one by one in the second sealing part (for example, the elements may be housed only in one side).

また一方の封止部に素子を２個塔載しても良い。Furthermore, two elements may be mounted on one sealing part.

〔発明の効果〕〔Effect of the invention〕

次に上記のような半導体装置の利点を述べる。 Next, the advantages of the semiconductor device as described above will be described.

従来のパッケージ本体の両側面がらアウターリード列が
引き出されるＤＩＰ型のもののアウタＺ（ｂを重ねるよ
うなものでは、半導体素子１２ａ、１２ｂの取り付けら
れた素子配設部１１ａ、ｌｌｂが、プリント基板等の実
装面に対し垂面に並んだ状態で実装されるために、例え
ば、従来アウターリード開帳が０．７６２　Ｃｍのもの
と同程度の素子の取り付けられたものでは、アウターリ
ード開帳を約０．２’５４Ｃｍ程度に狭めることができ
る。In a conventional DIP type package in which the outer lead rows are pulled out from both sides of the package body, the outer Z(b) overlaps, the element mounting portions 11a and llb to which the semiconductor elements 12a and 12b are attached are attached to a printed circuit board, etc. For example, in a device mounted with an element of the same size as a conventional one with an outer lead opening of 0.762 cm, the outer lead opening is approximately 0.762 cm. It can be narrowed to about 2'54 cm.

その上、実施例のように１個の装置内に２個の半導体素
子が組み込まれる場合には、従来のＤＩＰ型に比べ実装
面積を％〜ｙ４以下にすることが可能である。Furthermore, when two semiconductor elements are incorporated into one device as in the embodiment, the mounting area can be reduced to %~y4 or less compared to the conventional DIP type.

また、パッケージ本体から引き出された足すなわちアウ
ターリードは２列に並んだ配列をしており、従来のＤＩ
Ｐとほぼ同等の大きさおよび強度を有するようにできる
。従って従来のＤＩＰと同様にプリント基板上に設けら
れた穴にアウターリードを挿入し半田付は等を行うＤＩ
Ｐ型の実装法を用いることができ、従来のフラットパッ
ケージ型のものに比べはるかに容易な実装が可能である
。In addition, the legs or outer leads pulled out from the package body are arranged in two rows, unlike conventional DI
It can be made to have approximately the same size and strength as P. Therefore, as with conventional DIP, the outer leads are inserted into the holes provided on the printed circuit board and soldering is done.
A P-type mounting method can be used, and mounting is much easier than that of a conventional flat package type.

また、第３図の装置の製造には殆んど従来のＤＩＰ型の
製造装置および部品材料を使用できるため、大幅なコス
ト上昇を招く恐れもない。Further, since most conventional DIP type manufacturing equipment and component materials can be used to manufacture the device shown in FIG. 3, there is no risk of a significant increase in costs.

以上のようにこの発明によれば、実装コストの大幅な上
昇を招くことなく実装法が容易で実装密度の向上され、
た半導体装置を提供できる。As described above, according to the present invention, the mounting method is easy and the mounting density is improved without causing a significant increase in the mounting cost.
A semiconductor device can be provided.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図および第２図はこの発明の一実施例に係る半導体
装置の製造過程を説明する図、第３図はこの発明の一実
施例に係る半導体装置の外観を示す図である。 １１・・・リードフレーム、１１ａ・・・第１の素子配
設部、ｌｌｂ・・・第２の素子配設部、１２ａ・・・第
１の半導体素子、１２ｂ・・・第２の半導体素子、１３
・・・ワイヤ、１４ａ・・・第１の樹脂封止部、１４ｂ
・・第２の樹脂封止部、１６・・・連結リード部、１７
・・・パッケージ本体、１８ａ・・・第１のアウターリ
ード列、１８ｂ・・・第２のアウターリード列。 出願人代理人　弁理士　鈴　江　武　彦２３１ １１′ 第２図 第３図1 and 2 are diagrams for explaining the manufacturing process of a semiconductor device according to an embodiment of the present invention, and FIG. 3 is a diagram showing the appearance of a semiconductor device according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 11... Lead frame, 11a... 1st element arrangement part, llb... 2nd element arrangement part, 12a... 1st semiconductor element, 12b... 2nd semiconductor element , 13
...Wire, 14a...First resin sealing part, 14b
...Second resin sealing part, 16...Connection lead part, 17
. . . package body, 18a . . . first outer lead row, 18b . . . second outer lead row. Applicant's agent Patent attorney Takehiko Suzue 231 11' Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 少なくとも一方に半導体素子が収納され、互いに一体的
に重ねられることによりパッケージ本体を構成する第１
および第２の樹脂封止部と、上記第１および第２の樹脂
封止部の接合する線が露出する面の一つよりそれぞれ引
き出された一体的にデュアルインライン配列を成してい
る第１および第２のアウターリード列と、上記アウター
リード列の引き出される面と異なる面の上記第１および
第２の樹脂封止部の側面から引き出されこの第１および
第２の樹脂封止部内のインナーリードと電気的に接続す
る連結リード部とを具備していることを特徴とする半導
体装置。A semiconductor device is housed in at least one of the first parts, and the first parts are stacked integrally with each other to form a package body.
and a second resin sealing part and a first resin sealing part integrally formed in a dual in-line arrangement, each of which is drawn out from one of the exposed surfaces of the joining line of the first and second resin sealing parts. and a second outer lead row, and inner wires in the first and second resin sealing portions that are pulled out from the side surfaces of the first and second resin sealing portions on a surface different from the surface from which the outer lead rows are drawn out. A semiconductor device comprising a connecting lead portion electrically connected to a lead.
JP57225210A 1982-12-22 1982-12-22 Semiconductor device Pending JPS59115551A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57225210A JPS59115551A (en) 1982-12-22 1982-12-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57225210A JPS59115551A (en) 1982-12-22 1982-12-22 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS59115551A true JPS59115551A (en) 1984-07-04

Family

ID=16825704

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57225210A Pending JPS59115551A (en) 1982-12-22 1982-12-22 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59115551A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0416573A1 (en) * 1989-09-05 1991-03-13 Kabushiki Kaisha Toshiba Resin sealing type semiconductor device having outer leads designed for multi-fonctions

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0416573A1 (en) * 1989-09-05 1991-03-13 Kabushiki Kaisha Toshiba Resin sealing type semiconductor device having outer leads designed for multi-fonctions
US5031024A (en) * 1989-09-05 1991-07-09 Kabushiki Kaisha Toshiba Resin sealing type semiconductor device having outer leads designed for multi-functions

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