JPH08250650A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH08250650A JPH08250650A JP7049813A JP4981395A JPH08250650A JP H08250650 A JPH08250650 A JP H08250650A JP 7049813 A JP7049813 A JP 7049813A JP 4981395 A JP4981395 A JP 4981395A JP H08250650 A JPH08250650 A JP H08250650A
- Authority
- JP
- Japan
- Prior art keywords
- lid
- semiconductor device
- semiconductor
- elements
- added
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/1627—Disposition stacked type assemblies, e.g. stacked multi-cavities
Landscapes
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】この発明は、半導体素子の実装密
度を高めた半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a high mounting density of semiconductor elements.
【0002】[0002]
【従来の技術】半導体素子をパッケージで封止して作ら
れる半導体装置は、システムエレクトロニクス製品の小
型、高速化のために、パッケージの面積を広げずに半導
体素子の実装密度を高めることが不可欠になってきてい
る。2. Description of the Related Art In a semiconductor device made by encapsulating a semiconductor element in a package, it is indispensable to increase the packaging density of the semiconductor element without expanding the area of the package in order to reduce the size and speed of system electronic products. It has become to.
【0003】その要求に応えるべく開発されている半導
体装置の一例を図4に示す。この装置は、回路導体を有
するセラミック板を複数枚重ねて作られるセラミック積
層基板1の中央上下両面にキャビティ2を設け、その2
つのキャビティ2の底面にそれぞれ半導体素子3を接着
実装して基板1の上下両面を上蓋4と下蓋5で封止した
ものであり、例えば、特開昭60−74659号公報等
に開示されている。FIG. 4 shows an example of a semiconductor device developed to meet the demand. In this device, a cavity 2 is provided on both upper and lower sides of the center of a ceramic laminated substrate 1 which is made by stacking a plurality of ceramic plates having circuit conductors.
A semiconductor element 3 is adhesively mounted on the bottom surface of each cavity 2 and the upper and lower surfaces of the substrate 1 are sealed by an upper lid 4 and a lower lid 5, which are disclosed in, for example, Japanese Patent Laid-Open No. 60-74659. There is.
【0004】[0004]
【発明が解決しようとする課題】図4の装置は、セラミ
ック積層基板の両面に半導体素子を設けるので、基板の
片面のみを実装面としていた従前の半導体装置に比べる
と実装密度が2倍になっている。しかしながら、ひとつ
の装置に2個の半導体素子を設けるその構造では、更な
る高密度化の要求に満足に応えきれなくなってきてい
る。Since the semiconductor device is provided on both sides of the ceramic laminated substrate in the device of FIG. 4, the mounting density is doubled as compared with the conventional semiconductor device in which only one surface of the substrate is used as the mounting surface. ing. However, the structure in which two semiconductor elements are provided in one device cannot satisfy the demand for higher density.
【0005】そこで、本発明は、半導体素子の実装密度
をより一層高められるようにすることを第1の課題とし
ている。また、この高密度実装には発熱量の増加、電磁
波ノイズによる誤動作の増加の問題が伴うので、これ等
の問題にも対処できるようにすることを第2、第3の課
題としている。Therefore, the first object of the present invention is to further increase the packaging density of semiconductor elements. Further, since this high-density mounting involves problems such as an increase in heat generation and an increase in malfunction due to electromagnetic noise, it is the second and third problems to deal with these problems.
【0006】[0006]
【課題を解決するための手段】上記の課題を解決するた
め、本発明においては、セラミック積層基板の中央上下
両面にキャビティを設けてそれぞれのキャビティの底面
に半導体素子を接着実装することに加え、少なくとも上
下いずれかの蓋の内面にも半導体素子を接着実装する構
成を採用する。In order to solve the above problems, in the present invention, in addition to providing a cavity on the upper and lower surfaces of the center of a ceramic laminated substrate and bonding and mounting a semiconductor element on the bottom surface of each cavity, A structure in which a semiconductor element is adhesively mounted on the inner surface of at least one of the upper and lower lids is adopted.
【0007】また、場合によっては、上蓋の上面に放熱
フィンを、下蓋の下面にプリント基板との間の熱伝達板
を各々付加する。さらに、より好ましくは、セラミック
積層基板の両面のキャビティ間及び同一キャビティ内に
ある半導体素子間に電磁シールド層を付加する。Further, in some cases, a radiation fin is added to the upper surface of the upper lid, and a heat transfer plate between the printed wiring board and the lower lid is added to the lower lid. Furthermore, more preferably, an electromagnetic shield layer is added between the cavities on both sides of the ceramic laminated substrate and between the semiconductor elements in the same cavity.
【0008】[0008]
【作用】本発明では、蓋の内面にも半導体素子を実装す
るので、ひとつのパッケージに対する素子実装数が3個
又は4個になり、図4の装置との比較で実装密度が1.
5倍又は2倍に高まる。In the present invention, since the semiconductor elements are also mounted on the inner surface of the lid, the number of elements mounted in one package is three or four, and the mounting density is 1.
5 times or 2 times higher.
【0009】また、放熱フィンと放熱板を付加したもの
は、上蓋及び下蓋を伝っての熱の逃げがスムーズにな
り、放熱特性が向上して装置の熱劣化、熱による性能悪
化が抑制される。Further, in the case where the heat radiation fin and the heat radiation plate are added, the heat can smoothly escape through the upper lid and the lower lid, the heat radiation characteristic is improved, and the heat deterioration of the device and the performance deterioration due to the heat are suppressed. It
【0010】さらに、基板両面のキャビティ間、及び、
キャビティ底面と蓋内面の半導体素子間に電磁シールド
層を付加したものは、各素子間での電磁波ノイズの相互
侵入が阻止され、素子の電磁波ノイズによる誤動作が防
止される。Further, between the cavities on both sides of the substrate, and
In the case where the electromagnetic shield layer is added between the semiconductor elements on the bottom surface of the cavity and the inner surface of the lid, mutual intrusion of electromagnetic noise between the elements is prevented, and malfunction of the elements due to electromagnetic noise is prevented.
【0011】[0011]
【実施例】図1に、本発明の半導体装置の第1実施例を
示す。図中1は回路導体7を有する積層セラミック基板
である。この基板1は、セラミック板を必要枚数積層し
て作られたものであって、中央上下面にキャビティ2を
有し、それぞれのキャビティ2の底面に半導体素子3が
接着実装されている。FIG. 1 shows a first embodiment of the semiconductor device of the present invention. In the figure, reference numeral 1 is a laminated ceramic substrate having a circuit conductor 7. This substrate 1 is made by laminating a required number of ceramic plates, has a cavity 2 in the center upper and lower surfaces, and a semiconductor element 3 is adhesively mounted on the bottom surface of each cavity 2.
【0012】4は基板1の上部に取付ける上蓋、5は基
板1の下部に取付ける下蓋であり、これ等の蓋が低融点
ガラス等で基板1に接着固定されて上下のキャビティ2
が密封される。半導体素子3はこの上蓋4及び下蓋5の
内面にも接着実装されている。Reference numeral 4 denotes an upper lid which is attached to the upper portion of the substrate 1, and 5 is a lower lid which is attached to the lower portion of the substrate 1. These lids are adhered and fixed to the substrate 1 with a low-melting glass or the like to form the upper and lower cavities 2.
Is sealed. The semiconductor element 3 is also adhesively mounted on the inner surfaces of the upper lid 4 and the lower lid 5.
【0013】8は、各半導体素子3を対応した回路導体
7に接続するボンディングワイヤである。上蓋4及び下
蓋5は、内面に半導体素子3を接着実装し、その素子を
蓋の内面に設けられている回路導体7にボンディングワ
イヤ8で結線した後、素子の実装、結線を終えている基
板1に取付けられる。Reference numeral 8 is a bonding wire for connecting each semiconductor element 3 to the corresponding circuit conductor 7. After the semiconductor element 3 is adhesively mounted on the inner surfaces of the upper lid 4 and the lower lid 5 and the elements are connected to the circuit conductor 7 provided on the inner surface of the lid by the bonding wires 8, the mounting and connection of the elements are completed. It is attached to the substrate 1.
【0014】回路導体7は、対応するリードピン6に電
気的に導通しており、電源用、信号用、接地用の各リー
ドピン6をプリント基板11上の電源、信号、接地の各
回路に接続してプリント基板に対する半導体装置の実装
が行われる。なお、リードピン6を通した下蓋の孔は、
ガラス封止でリードピンとの間の隙間を塞いである。The circuit conductor 7 is electrically connected to the corresponding lead pin 6, and connects the power supply, signal, and ground lead pins 6 to the power supply, signal, and ground circuits on the printed circuit board 11. The semiconductor device is mounted on the printed circuit board. In addition, the hole of the lower lid through the lead pin 6,
The gap between the lead pin is closed by glass sealing.
【0015】図2は第2実施例である。この半導体装置
は、図1の装置の上蓋4上に放熱フィン9を付け、さら
に、下蓋5の下面に下蓋とプリント基板11との間に挾
み込む伝熱板10を付加したものである。この装置は、
上蓋4に流れた熱が放熱フィン9経由で大気に放出さ
れ、また、下蓋5に流れた熱が伝熱板10経由で表面
積、熱容量ともに大きいプリント基板11に吸収される
ので、素子も含めて装置の温度が低く保たれる。FIG. 2 shows a second embodiment. In this semiconductor device, a radiation fin 9 is attached on the upper lid 4 of the apparatus of FIG. 1, and a heat transfer plate 10 which is sandwiched between the lower lid and the printed circuit board 11 is added to the lower surface of the lower lid 5. is there. This device
The heat that has flowed to the upper lid 4 is released to the atmosphere via the radiation fins 9, and the heat that has flowed to the lower lid 5 is absorbed by the printed circuit board 11 that has a large surface area and large heat capacity via the heat transfer plate 10. The device temperature is kept low.
【0016】図3(a)は、図2の装置に更に、電磁シ
ールド層を付加した第3実施例である。基板1の上下の
キャビティ2、2間を仕切る部分を2層にして層間に印
刷導体、気相成膜やメッキによる導体、或いは箔導体か
ら成る電磁シールド層12を設け、さらに、同一キャビ
ティ内にある半導体素子間にそれぞれ電磁シールド層1
3を設けている。素子間の電磁シールド層13は、図3
(b)に示すようなメッシュ導体13aを用い、そのメ
ッシュ導体の周縁を、キャビティ2を作り出す額縁状セ
ラミックの層間に挾んで作り出している。この電磁シー
ルド層13は、表面に額縁コート層を具備させるとボン
ディングワイヤ8が接触しても問題が起こらず、空間的
余裕が少なくて済むため装置のより一層の小型化が図れ
る。FIG. 3A shows a third embodiment in which an electromagnetic shield layer is added to the device of FIG. An electromagnetic shield layer 12 composed of a printed conductor, a conductor formed by vapor deposition or plating, or a foil conductor is provided between the two layers by partitioning the space between the upper and lower cavities 2 of the substrate 1 into two layers. Electromagnetic shield layer 1 between certain semiconductor elements
3 are provided. The electromagnetic shield layer 13 between the elements is shown in FIG.
The mesh conductor 13a as shown in (b) is used, and the periphery of the mesh conductor is sandwiched between the frame-shaped ceramic layers that form the cavity 2. If the electromagnetic shield layer 13 is provided with a frame coating layer on the surface, no problem occurs even if the bonding wire 8 comes into contact with the surface, and the space margin is small, so that the device can be further downsized.
【0017】なお、電磁シールド層12、13は、接地
用リードピンに直接又は間接的に接続されている。The electromagnetic shield layers 12 and 13 are directly or indirectly connected to the ground lead pin.
【0018】この第3実施例は、各半導体素子間での電
磁波ノイズの相互侵入が電磁シールド層12、13によ
って防止されるので、半導体素子の誤動作が起こり難
く、信頼性がより高まる。In the third embodiment, since the electromagnetic shield layers 12 and 13 prevent mutual intrusion of electromagnetic noise between the respective semiconductor elements, malfunction of the semiconductor elements is unlikely to occur and reliability is further enhanced.
【0019】[0019]
【発明の効果】以上説明したように、本発明によれば、
パッケージの蓋の内面にも半導体素子を実装するので、
パッケージの面積を増やさずに素子の実装数を、両面実
装タイプの従来装置の1.5倍又は2倍に高めることが
できる。As described above, according to the present invention,
Since the semiconductor element is also mounted on the inner surface of the package lid,
The number of mounted elements can be increased to 1.5 times or twice that of the conventional double-sided mounting type device without increasing the area of the package.
【0020】また、放熱特性の改善、電磁波ノイズによ
る素子の誤動作の低減も可能ならしめたので、信頼性が
高くて耐久性にも優れる小型の高密度実装半導体装置を
実現でき、システムエレクトロニクス製品の更なる小
型、高速化が図れるようになる。Further, since it is possible to improve the heat dissipation characteristic and reduce the malfunction of the element due to electromagnetic noise, it is possible to realize a small-sized high-density mounting semiconductor device which is highly reliable and has excellent durability. Further miniaturization and higher speed can be achieved.
【図1】第1実施例の断面図FIG. 1 is a sectional view of a first embodiment.
【図2】第2実施例の断面図FIG. 2 is a sectional view of a second embodiment.
【図3】(a):第3実施例の断面図 (b):第3実施例に用いるメッシュ導体の斜視図FIG. 3A is a sectional view of a third embodiment. FIG. 3B is a perspective view of a mesh conductor used in the third embodiment.
【図4】従来の半導体装置の一例を示す断面図FIG. 4 is a sectional view showing an example of a conventional semiconductor device.
1 セラミック積層基板 2 キャビティ 3 半導体素子 4 上蓋 5 下蓋 6 リードピン 7 回路導体 8 ボンディングワイヤ 9 放熱フィン 10 伝熱板 11 プリント基板 12、13 電磁シールド層 13a メッシュ導体 1 Ceramic Laminated Substrate 2 Cavity 3 Semiconductor Element 4 Upper Lid 5 Lower Lid 6 Lead Pin 7 Circuit Conductor 8 Bonding Wire 9 Radiating Fin 10 Heat Transfer Plate 11 Printed Circuit Board 12, 13 Electromagnetic Shielding Layer 13a Mesh Conductor
Claims (3)
を構成するセラミック積層基板の中央上下両面にキャビ
ティを有し、それぞれのキャビティの底面と少なくとも
上下いずれかの蓋の内面とに半導体素子を接着実装した
ことを特徴とする半導体装置。1. A ceramic laminated substrate, which constitutes a package in combination with an upper lid and a lower lid, has cavities on the upper and lower sides of the center thereof, and a semiconductor element is bonded and mounted on the bottom surface of each cavity and at least the inner surface of either the upper or lower lid. A semiconductor device characterized by the above.
下面にプリント基板との間の熱伝達板を各々付加してあ
る請求項1記載の半導体装置。2. The semiconductor device according to claim 1, wherein a heat radiation fin is added to an upper surface of the upper lid, and a heat transfer plate between the printed wiring board and the lower lid is added.
間及び同一キャビティ内にある半導体素子間に電磁シー
ルド層を付加してある請求項1又は2記載の半導体装
置。3. The semiconductor device according to claim 1, wherein an electromagnetic shield layer is added between the cavities on both sides of the ceramic laminated substrate and between the semiconductor elements in the same cavity.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7049813A JPH08250650A (en) | 1995-03-09 | 1995-03-09 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7049813A JPH08250650A (en) | 1995-03-09 | 1995-03-09 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH08250650A true JPH08250650A (en) | 1996-09-27 |
Family
ID=12841574
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7049813A Pending JPH08250650A (en) | 1995-03-09 | 1995-03-09 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH08250650A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002374127A (en) * | 2001-06-14 | 2002-12-26 | Seiko Epson Corp | Piezoelectric oscillator |
JP2006080521A (en) * | 2004-09-10 | 2006-03-23 | Samsung Electronics Co Ltd | Stacked board-on-chip package having mirror structure and double-sided memory module on which the same is mounted |
US8030752B2 (en) | 2007-12-18 | 2011-10-04 | Samsung Electro-Mechanics Co., Ltd. | Method of manufacturing semiconductor package and semiconductor plastic package using the same |
EP1657749A3 (en) * | 2004-10-29 | 2013-05-29 | Thales | Multilevel microelectronic package with internal shielding |
JP2020109821A (en) * | 2018-12-28 | 2020-07-16 | 長瀬産業株式会社 | Semiconductor device and manufacturing method thereof |
-
1995
- 1995-03-09 JP JP7049813A patent/JPH08250650A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002374127A (en) * | 2001-06-14 | 2002-12-26 | Seiko Epson Corp | Piezoelectric oscillator |
JP2006080521A (en) * | 2004-09-10 | 2006-03-23 | Samsung Electronics Co Ltd | Stacked board-on-chip package having mirror structure and double-sided memory module on which the same is mounted |
EP1657749A3 (en) * | 2004-10-29 | 2013-05-29 | Thales | Multilevel microelectronic package with internal shielding |
US8030752B2 (en) | 2007-12-18 | 2011-10-04 | Samsung Electro-Mechanics Co., Ltd. | Method of manufacturing semiconductor package and semiconductor plastic package using the same |
US8174128B2 (en) | 2007-12-18 | 2012-05-08 | Samsung Electro-Mechanics Co., Ltd. | Method of manufacturing semiconductor package having a first board, second boards electrically connected to both sides of the first board, and at least one component connected to the first board by a flip chip method |
JP2020109821A (en) * | 2018-12-28 | 2020-07-16 | 長瀬産業株式会社 | Semiconductor device and manufacturing method thereof |
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