JPH08250645A - Semiconductor device and amplifying circuit - Google Patents

Semiconductor device and amplifying circuit

Info

Publication number
JPH08250645A
JPH08250645A JP4825195A JP4825195A JPH08250645A JP H08250645 A JPH08250645 A JP H08250645A JP 4825195 A JP4825195 A JP 4825195A JP 4825195 A JP4825195 A JP 4825195A JP H08250645 A JPH08250645 A JP H08250645A
Authority
JP
Japan
Prior art keywords
semiconductor device
resistor
terminal
diode
resistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4825195A
Other languages
Japanese (ja)
Inventor
Masaaki Sudo
公明 須藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP4825195A priority Critical patent/JPH08250645A/en
Publication of JPH08250645A publication Critical patent/JPH08250645A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To provide a semiconductor device and a buffer circuit wherein the space and the cost are reduced by reducing the number of components. CONSTITUTION: Only when an input voltage is higher than the divided voltage VA determined by resistors 4c, 6 in a semiconductor device 4, an input signal is amplified by a common emitter amplifier constituted of resistors 1, 3 and a transistor 2, and further amplified by the next stage common emitter amplifier constituted of resistors 7, 9 and a transistor 8. When the input is lower than VA, the transistors 2, 8 are turned into the state of cutoff, and the output becomes equal to the earth potential.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、複数の抵抗器とダイオ
ードをワンチップ化した半導体装置と、それを応用した
増幅回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a plurality of resistors and diodes are integrated into one chip, and an amplifier circuit to which the semiconductor device is applied.

【0002】[0002]

【従来の技術】近年、半導体装置は、高集積化が著しい
ことは衆知の事実である。その一方で、これら高集積化
された回路間を結ぶ場合、依然として抵抗器やダイオー
ドを介したディスクリート部品で接続されているのも事
実である。この原因は、電源電圧の違いや接地電位の違
いを放置して接続すると、高集積化されているだけに、
入力部の耐圧や耐電流が小さくなっている為、高価な高
集積回路そのものを破壊する恐れがあるためである。
2. Description of the Related Art It is a well-known fact that semiconductor devices have been highly integrated in recent years. On the other hand, when connecting these highly integrated circuits, it is a fact that they are still connected by discrete components via resistors and diodes. The reason for this is that if you connect while leaving the difference in the power supply voltage or the difference in the ground potential, it will be highly integrated,
This is because the withstand voltage and withstand current of the input section are reduced, and the expensive highly integrated circuit itself may be destroyed.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、このよ
うなディスクリート部品を用いた保護回路等を用いる場
合、必然的に部品点数が多くなり、またその部品を実装
する基板の面積が、ランドマークを多く必要としたり、
このランドマークをエッチング時に接触したりしないよ
うに所定の幅だけ離してやる必要があるため、大きくな
り、コスト高と小型化の障害となるという問題点があっ
た。
However, when a protection circuit or the like using such discrete components is used, the number of components is inevitably increased, and the area of the board on which the components are mounted has many landmarks. Needed or
Since it is necessary to separate the landmarks by a predetermined width so that they do not come into contact with each other during etching, the landmarks become large, and there is a problem that they become an obstacle to high cost and miniaturization.

【0004】本発明は、上記問題点に鑑み成されたもの
であり、部品点数を減らし、その結果、省スペースとコ
ストダウンを目指す半導体装置およびバッファ回路を提
供することを目的とする。
The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device and a buffer circuit aiming at space saving and cost reduction by reducing the number of parts.

【0005】[0005]

【課題を解決するための手段】上記目的を達成するため
に、本発明の半導体装置は、ダイオードと、このダイオ
ードの第1の電極に直列に接続された第1、第2の抵抗
器とを備え、上記第1の抵抗器と上記第2の抵抗器の接
続点につながる第1端子と、前記第2の抵抗器の他端に
つながる第2端子と、前記ダイオードの第2の電極につ
ながる第3端子を設け、かつ上記ダイオードと上記第1
及び第2の抵抗器を1つのモールド・パッケージに収め
たことを特徴とするものである。
In order to achieve the above object, a semiconductor device of the present invention comprises a diode and first and second resistors connected in series to a first electrode of the diode. A first terminal connected to a connection point between the first resistor and the second resistor, a second terminal connected to the other end of the second resistor, and a second electrode of the diode A third terminal is provided, and the diode and the first terminal are provided.
And the second resistor in one molded package.

【0006】また、本発明の増幅回路は、前記第1端子
を第3の抵抗器を介して電源に接続し、前記第2端子を
基準電位点に接続し、前記第3端子をエミッタ接地型増
幅器のエミッタに接続して成るものである。
Also, in the amplifier circuit of the present invention, the first terminal is connected to a power source through a third resistor, the second terminal is connected to a reference potential point, and the third terminal is a grounded-emitter type. It is connected to the emitter of the amplifier.

【0007】[0007]

【作用】上記した構成により、請求項1の半導体装置で
は、ダイオードと、このダイオードの第1の電極に直列
に接続された第1、第2の抵抗器とを備え、第1の抵抗
器と第2の抵抗器の接続点につながる第1端子と、前記
第2の抵抗器の他端につながる第2端子と、前記ダイオ
ードの第2の電極につながる第3端子を設け、かつダイ
オードと第1及び第2の抵抗器を1つのモールド・パッ
ケージに収めたことにより、部品点数を減らし、その結
果、省スペースとコストダウンを目指すこととなる。
With the above structure, the semiconductor device according to the present invention comprises the diode and the first and second resistors connected in series to the first electrode of the diode. A first terminal connected to the connection point of the second resistor, a second terminal connected to the other end of the second resistor, and a third terminal connected to the second electrode of the diode are provided, and the diode and the By housing the first and second resistors in one mold package, the number of parts can be reduced, and as a result, space saving and cost reduction can be achieved.

【0008】上記した構成により、請求項2の増幅回路
では、前記第1端子を第3の抵抗器を介して電源に接続
し、前記第2端子を基準電位点に接続し、前記第3端子
をエミッタ接地型増幅器のエミッタに接続して成るの
で、部品点数を減らし、その結果、省スペースとコスト
ダウンを目指すこととなる。
With the above structure, in the amplifier circuit according to the second aspect, the first terminal is connected to the power source through the third resistor, the second terminal is connected to the reference potential point, and the third terminal is connected. Is connected to the emitter of the grounded-emitter amplifier, the number of parts is reduced, and as a result, space saving and cost reduction are aimed at.

【0009】[0009]

【実施例】以下、本発明の一実施例について、図面を参
照しながら説明する。図1は本発明の一実施例における
半導体装置とそれを応用した増幅回路の回路図を示すも
のである。図1において、1、3、6、7と9は抵抗
器、2はNPNのトランジスタ、5はコンデンサ、8は
PNPのトランジスタ、4は本願の半導体装置である。
以上のように構成された本発明の半導体装置とそれを応
用した増幅回路につき、以下にその動作を説明する。
An embodiment of the present invention will be described below with reference to the drawings. 1 is a circuit diagram of a semiconductor device and an amplifier circuit to which the semiconductor device is applied according to an embodiment of the present invention. In FIG. 1, 1, 3, 6, 7, and 9 are resistors, 2 is an NPN transistor, 5 is a capacitor, 8 is a PNP transistor, and 4 is a semiconductor device of the present application.
The operation of the semiconductor device of the present invention configured as described above and the amplifier circuit to which the semiconductor device is applied will be described below.

【0010】入力されて来た信号は、トランジスタ2の
ベース端子に入力され、抵抗器3の抵抗値をR1、抵抗
器1の抵抗値をR2としたとき、(R2/R1)倍に増
幅される。ここで、半導体装置4内の抵抗器4cの抵抗
値をR3、抵抗器6の抵抗値をR4としたとき、図上の
A点の電位VAは、次式で与えられる。
The input signal is input to the base terminal of the transistor 2 and is amplified by (R2 / R1) times, where R1 is the resistance value of the resistor 3 and R2 is the resistance value of the resistor 1. It Here, when the resistance value of the resistor 4c in the semiconductor device 4 is R3 and the resistance value of the resistor 6 is R4, the potential VA at the point A in the figure is given by the following equation.

【0011】[0011]

【数1】 [Equation 1]

【0012】この電位VAは、抵抗器4bを介してダイ
オード4aからトランジスタ2のエミッタに供給され
る。ここで、ダイオードの順方向の動作電圧とトランジ
スタ2のベース・エミッタ間の動作電圧はほぼ同じであ
るから、図上のA点の電位と入力電圧が同じかそれ以上
ないとトランジスタ2は、カットオフすることになる。
したがって、図1の増幅回路では、入力が上式(1)の
VA以上無いときには働かない構造となっている。な
お、コンデンサ5は単なるパスコンである。
This potential VA is supplied to the emitter of the transistor 2 from the diode 4a via the resistor 4b. Here, since the operating voltage in the forward direction of the diode and the operating voltage between the base and emitter of the transistor 2 are almost the same, the transistor 2 is cut off if the potential at the point A on the figure and the input voltage are the same or higher. Will be turned off.
Therefore, the amplifier circuit of FIG. 1 has a structure that does not work when the input is not more than VA of the above formula (1). The capacitor 5 is just a decap.

【0013】さて、このような電圧VA以上の場合に
は、抵抗器1、3とトランジスタ2から成るエミッタ接
地型増幅器の出力は、次段の抵抗7と9およびトランジ
スタ8から成るエミッタ接地型増幅器において更に増幅
され出力されることになる。ここで、抵抗器7の抵抗値
をR7、抵抗器9の抵抗値をR9とすれば、この図1の
回路の増幅率は、(R2/R1)・(R7/R9)とな
る。逆に入力が電圧VA以下の場合には、トランジスタ
2はカットオフするので、トランジスタ8もカットオフ
し、出力はグランド電位となる。
When the voltage is higher than VA, the output of the grounded-emitter amplifier composed of resistors 1 and 3 and transistor 2 is the grounded-emitter amplifier composed of resistors 7 and 9 and transistor 8 in the next stage. Will be further amplified and output at. Here, if the resistance value of the resistor 7 is R7 and the resistance value of the resistor 9 is R9, the amplification factor of the circuit of FIG. 1 is (R2 / R1) · (R7 / R9). On the contrary, when the input is equal to or lower than the voltage VA, the transistor 2 is cut off, so that the transistor 8 is also cut off and the output becomes the ground potential.

【0014】ここで、半導体装置4は、ワンチップのモ
ールド樹脂でコーティングされた1個の素子であり、図
2の(a)のような配置でパッケージ内に内蔵されてい
る。従って、この図1の回路の素子数は全てで9個であ
り、半導体装置4を別々の素子で構成した場合に較べ
て、2個削減できている。また、半導体素子4をプリン
ト基板上に実装する際は、端子数が3個であるから、別
々の素子を組み合わせた場合には6個となることを考慮
すると、3個のランドマークが削減できることになる。
Here, the semiconductor device 4 is one element coated with a one-chip mold resin, and is incorporated in the package in the arrangement as shown in FIG. Therefore, the number of elements in the circuit of FIG. 1 is nine in total, which is two compared with the case where the semiconductor device 4 is composed of separate elements. Further, when the semiconductor element 4 is mounted on the printed circuit board, the number of terminals is three, so that it is possible to reduce three landmarks considering that the number of terminals is six when the different elements are combined. become.

【0015】なお、以上の実施例では、図2の(a)の
ような半導体装置を用いたが、例えば、その他の回路と
しては図2の(b)のようにダイオードの向きを逆にし
てもよい。また、これらの図2の半導体装置の用途とし
ては、上述のようなアナログの増幅回路のみではなく、
例えば従来の技術の項で述べたように集積回路間の接続
に用いても良い。その他、本発明は、上記実施例に限定
される物ではなく、種々変形実施可能である。
In the above embodiment, the semiconductor device as shown in FIG. 2A was used, but for other circuits, for example, the diode direction is reversed as shown in FIG. 2B. Good. The semiconductor device of FIG. 2 may be used not only in the analog amplifier circuit as described above,
For example, it may be used for connection between integrated circuits as described in the section of the prior art. In addition, the present invention is not limited to the above-mentioned embodiment, and various modifications can be made.

【0016】[0016]

【発明の効果】以上のように本発明によれば、請求項1
の半導体装置では、ダイオードと、このダイオードの第
1の電極に直列に接続された第1、第2の抵抗器とを備
え、第1の抵抗器と第2の抵抗器の接続点につながる第
1端子と、前記第2の抵抗器の他端につながる第2端子
と、前記ダイオードの第2の電極につながる第3端子を
設け、かつダイオードと第1及び第2の抵抗器を1つの
モールド・パッケージに収めたことにより、部品点数を
減らし、その結果、省スペースとコストダウンを目指す
ことができるという効果がある。
As described above, according to the present invention, claim 1
In the semiconductor device of 1), the diode and the first and second resistors connected in series to the first electrode of the diode are provided, and the first resistor connected to the connection point of the first resistor and the second resistor. One terminal, a second terminal connected to the other end of the second resistor, and a third terminal connected to the second electrode of the diode are provided, and the diode and the first and second resistors are formed in one mold. -By putting it in a package, the number of parts can be reduced, and as a result, space saving and cost reduction can be achieved.

【0017】さらにまた、回路面積を小さくすることに
より、伝送の速度が向上することができるという効果が
ある。また、基板上の隣接する電子部品間の配線数が削
減できるので、雑音を拾うことが少なくなり、高性能化
が図れるという効果もある。また、基板上の電子部品の
実装数が減るので、実装不良を自ずと低減できるという
効果もある。
Furthermore, there is an effect that the transmission speed can be improved by reducing the circuit area. Further, since the number of wirings between adjacent electronic components on the substrate can be reduced, noise is less picked up, and there is an effect that high performance can be achieved. Further, since the number of electronic components mounted on the board is reduced, it is possible to reduce the number of mounting defects.

【0018】また、請求項2の増幅回路では、前記第1
端子を第3の抵抗器を介して電源に接続し、前記第2端
子を基準電位点に接続し、前記第3端子をエミッタ接地
型増幅器のエミッタに接続して成るので、部品点数を減
らし、その結果、省スペースとコストダウンを目指すこ
とができるという効果がある。
Further, in the amplifier circuit according to claim 2, the first circuit is provided.
Since the terminal is connected to the power source through the third resistor, the second terminal is connected to the reference potential point, and the third terminal is connected to the emitter of the grounded-emitter amplifier, the number of parts is reduced, As a result, there is an effect that space saving and cost reduction can be aimed at.

【0019】さらにまた、回路面積を小さくすることに
より、伝送の速度が向上することができるという効果が
ある。また、基板上の隣接する電子部品間の配線数が削
減できるので、雑音を拾うことが少なくなり、高性能化
が図れるという効果もある。また、基板上の電子部品の
実装数が減るので、実装不良を自ずと低減できるという
効果もある。
Furthermore, there is an effect that the transmission speed can be improved by reducing the circuit area. Further, since the number of wirings between adjacent electronic components on the substrate can be reduced, noise is less picked up, and there is an effect that high performance can be achieved. Further, since the number of electronic components mounted on the board is reduced, it is possible to reduce the number of mounting defects.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の一実施例に係る半導体装置を応用し
た増幅回路の回路図である。
FIG. 1 is a circuit diagram of an amplifier circuit to which a semiconductor device according to an embodiment of the present invention is applied.

【図2】 同実施例における半導体装置の他の構成例を
示す図である。
FIG. 2 is a diagram showing another configuration example of the semiconductor device in the example.

【符号の説明】[Explanation of symbols]

1、3、6、7、9 抵抗器 2 NPNトランジスタ 4 半導体装置 5 コンデンサ 8 PNPトランジスタ 1, 3, 6, 7, 9 Resistor 2 NPN transistor 4 Semiconductor device 5 Capacitor 8 PNP transistor

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 ダイオードと、 このダイオードの第1の電極に直列に接続された第1、
第2の抵抗器と、を備え、上記第1の抵抗器と上記第2
の抵抗器の接続点につながる第1端子と、前記第2の抵
抗器の他端につながる第2端子と、前記ダイオードの第
2の電極につながる第3端子を設け、かつ上記ダイオー
ドと上記第1及び第2の抵抗器を1つのモールド・パッ
ケージに収めたことを特徴とする半導体装置。
1. A diode, a first electrode connected in series to a first electrode of the diode,
A second resistor; and the first resistor and the second resistor
A first terminal connected to the connection point of the resistor, a second terminal connected to the other end of the second resistor, and a third terminal connected to the second electrode of the diode, and the diode and the third terminal. A semiconductor device in which the first and second resistors are housed in a single molded package.
【請求項2】 前記第1端子を第3の抵抗器を介して電
源に接続し、前記第2端子を基準電位点に接続し、前記
第3端子をエミッタ接地型増幅器のエミッタに接続して
成る増幅回路。
2. The first terminal is connected to a power source through a third resistor, the second terminal is connected to a reference potential point, and the third terminal is connected to the emitter of a grounded-emitter amplifier. Amplifier circuit consisting of.
JP4825195A 1995-03-08 1995-03-08 Semiconductor device and amplifying circuit Pending JPH08250645A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4825195A JPH08250645A (en) 1995-03-08 1995-03-08 Semiconductor device and amplifying circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4825195A JPH08250645A (en) 1995-03-08 1995-03-08 Semiconductor device and amplifying circuit

Publications (1)

Publication Number Publication Date
JPH08250645A true JPH08250645A (en) 1996-09-27

Family

ID=12798233

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4825195A Pending JPH08250645A (en) 1995-03-08 1995-03-08 Semiconductor device and amplifying circuit

Country Status (1)

Country Link
JP (1) JPH08250645A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016152416A (en) * 2015-02-17 2016-08-22 立昌先進科技股▲分▼有限公司 Multi-function miniaturized surface-mount device and method for producing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016152416A (en) * 2015-02-17 2016-08-22 立昌先進科技股▲分▼有限公司 Multi-function miniaturized surface-mount device and method for producing the same

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