JPH08249265A - Storage device and control method - Google Patents

Abstract

PURPOSE: To evade the collision of address signals and data signals on a bus even in the case of using a low-speed ROM by performing control so as to output the output state of the output part of a memory to the bus while read request signals are valid and attain a state where the output part and the bus are cut off while the read request signals are invalid. CONSTITUTION: A CPU 1 reads data from a memory unit 10 and executes the various kinds of the control. The memory unit 10 is provided with a gate circuit 5 for performing the gate control to the CPU 1 of ROM data signals outputted by the ROM 4. The data signals outputted at the time of the read operation of the ROM 4 are passed through to an address/data bus as they are when RD* signals are active by the gate circuit 5, the address/data bus is cut off when they become disable and the output of the gate circuit 5 is turned to high impedance. Thus, the collision of the address signals outputted by the CPU 1 and the data signals outputted by the ROM 4 is preventated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device, and more particularly to a storage device and a control method for transmitting an address signal and a data signal in multiplex on the same bus.

[0002]

2. Description of the Related Art A CPU that multiplexes an address signal and a data signal for use in a conventional memory device
Outputs address signals and inputs / outputs data signals on the same bus (address / data bus). Therefore R
When performing the data read operation from the OM, the circuit configuration as shown in FIG. 3 is used, and the read operation is performed at the timing as shown in the timing chart of FIG. In this operation, the latch circuit 2 latches with the ASTB * signal output from the CPU 1 and outputs an address latch signal. Further, this address latch signal is decoded by the decode circuit 3 to become a select signal (CS *), and the memory 4 is selected. Further, the CPU 1 outputs an RD * signal for instructing the reading of data to the memory 4. In response to these address signal, CS * signal and RD * signal, the memory 4 outputs a data signal on the address / data bus.

[0003]

However, in the above-mentioned conventional storage device, when a particularly low-speed low-speed ROM is used and the CPU is further speeded up, the following problems occur. First, because the ROM is slow, RD *
It takes a time (output disable / output floating time) until the data signal terminal of the ROM outputting the data signal becomes high impedance after the signal is disabled. On the other hand, since the CPU has a high speed, the data signal at the next timing is output from the CPU before the data signal terminal of the ROM becomes high impedance. Therefore, there arises a problem that the data signal output from the CPU at the next timing and the data signal output from the ROM before becoming high impedance collide on the address / data bus. For example, in FIG.
Then, before the data signal output terminal of the ROM becomes high impedance, the CPU shifts to the next read cycle and outputs the address signal. As a result, ROM
Data signal and the CPU address signal collide.

The present invention has been made in view of the above problems. In a storage device that multiplexes an address signal and a data signal for use, an address on a bus is generated especially when a low-speed ROM is used. An object of the present invention is to provide a storage device and a control method that avoid collision of signals and data signals.

[0005]

A storage device according to the present invention for achieving the above object has the following configuration. That is, it is a storage device that switches and transmits an address signal and a data signal on the same bus, and outputs from a data signal output unit in response to an address signal and a read request signal input from the address signal input unit. A memory for outputting data, a latch means for latching an address signal sent on the bus and supplying the address signal to the input part of the memory, and a latch means for supplying the address signal while the read request signal is valid. The output state of the output section of the memory is output to the bus,
Output control means is provided for controlling the output unit and the bus to be in a disconnected state while the read request signal is invalid.

A control method according to the present invention for achieving the above object has the following configuration. That is, it is a control method for transmitting an address signal and a data signal by switching them on the same bus, in which an output unit for a data signal is output from an output unit for a data signal according to an address signal and a read request signal input from an input unit for the address signal. An output step of outputting data from the memory, a step of latching an address signal sent on the bus and supplying the address signal to be provided to an input part of the memory, and a period during which the read request signal is valid. Outputting the output state of the output unit of the memory to the bus, and controlling the output unit and the bus to be in a disconnected state while the read request signal is invalid.

Preferably, the output control means is composed of a gate element whose output signal is switched to three types of "1", "0" and "high impedance" according to the input signal. This is because the gate element has a fast switching response speed and is small in size, so that the speed and size of the storage device can be easily reduced.

[0008] Preferably, the memory further comprises selection means for outputting a selection signal indicating whether to output a data signal from the memory based on the address signal latched and output by the latch means. When the selection signal indicates to output the data signal, the data signal is output according to the address signal and the read request. This is because the memory selection process is performed according to the address, so that it becomes easy to connect a plurality of storage devices to the same bus.

[0009]

According to the above structure, the memory has a memory for outputting data from the output section for the data signal in response to the address signal input from the input section for the address signal and the read request signal. Provided is a storage device that multiplexes signals and signals on the same bus. here,
The address signal sent on the bus is latched by the latch means and provided to the input section of the memory. Upon receiving the read request, the memory outputs a data signal based on this address signal. The output control means outputs the output state of the output section of the memory to the bus while the read request signal is valid, and the output section and the bus are disconnected while the read request signal is invalid. The connection between the output unit and the bus is controlled so that

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing the circuit configuration of the embodiment.

In FIG. 1, one CPU is used to read data from the memory unit 10 and execute various controls. 2 is a latch circuit for latching the address signal output from the CPU 1 and outputting an address / latch signal; 3
Is a decoding circuit for decoding the address / latch signal and outputting a CS * signal for selecting the ROM, 4 is a ROM, 5
Is a gate circuit for performing gate control for the CPU of the ROM / data signal output from the ROM 4.

The ROM 4 is an ordinary ROM chip having an address signal input terminal (Ax) and a data signal output terminal (I / Ox) individually.

Next, the ROM read cycle operation using the above configuration will be described.

FIG. 2 is a diagram showing a timing chart of the ROM read cycle of the embodiment.

The CPU 1 shares the same terminal ADx for an address signal and a data signal. Therefore, RO
When the read process of M4 is performed, an address signal is first output as shown in the AD signal of FIG. Latch circuit 2
ASTB * which this address signal is output from CPU1
The data is latched by the signal (a in FIG. 2) and the address data is used as the address latch signal (c in FIG. 2) of the ROM 4
Output to x terminal. The decode circuit 3 decodes the address latch signal and outputs a CS * signal (e in FIG. 2) for selecting the ROM 4. ROM4 is CS * signal and
A data signal (f in FIG. 2) is output from the I / Ox terminal by inputting the address latch signal and the RD signal (c in FIG. 2) output by the CPU 1.

In the circuit of FIG. 3, when the ROM 4 is slow, the time from when the RD * signal (c in FIG. 2) is disabled until the I / Ox terminal output from the ROM 4 becomes high impedance is delayed. Become. In this way, the I / Ox terminal that takes a long time to reach high impedance is C
When directly connected to the AD signal line of PU1 (b of FIG. 2), it collides with the address signal output from the CPU1 at the next timing as shown in FIG.

In this embodiment, the gate circuit 5 is provided. The gate circuit 5 is a gate whose output has three states of "0", "1", and "high impedance". The gate circuit 5 is switched between the binary state and the high impedance state by the RD * signal. Here, the binary state is a state in which the output signal is switched to "1" and "0" according to the input signal, and the high impedance state is a state in which the output is high impedance. B1 in FIG. 2 is the output state of the gate circuit 5 (binary state / high impedance)
The timing of switching is shown. As shown in b1 of FIG. 2, while the RD * signal is “0”, the output from the I / Ox terminal is in a binary state in which it is output as it is. Also, RD
* When the signal is "1", the output terminal of the gate circuit 5 has high impedance. This gate circuit 5 makes it possible to avoid a collision between the address signal output by the CPU 1 and the output of the ROM 4, as indicated by the AD signal in FIG.

As described above, according to the above embodiment, the ROM
When the RD * signal is active by the gate circuit 5, the data signal output during the read operation of 4 is passed through the address / data bus as it is, and when it is disabled, the address / data bus is disconnected and the gate is turned on. Circuit 5
By making the output of the high impedance
It is possible to prevent a collision between the address signal output by 1 and the data signal output by the ROM 4.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of a single device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0021]

As is clear from the above description, according to the present invention, even if an inexpensive low speed memory is used in a storage device for multiplexing and transmitting an address signal and a data signal, it can be used on a bus. A storage device and a control method capable of avoiding a collision between an address signal and a data signal can be provided.

[0022]

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of an embodiment.

FIG. 2 is a diagram showing a timing chart of a ROM read cycle according to the embodiment.

FIG. 3 is a block diagram showing a circuit configuration of a conventional example.

FIG. 4 is a diagram showing a timing chart of a ROM read cycle in a conventional example.

[Explanation of symbols]

 1 CPU 2 Latch circuit 3 Decode circuit 4 ROM 5 Gate circuit 10 Memory unit

Claims (4)

[Claims] 1. A storage device for switching between an address signal and a data signal for transmission on the same bus, wherein the storage device is for a data signal in response to an address signal and a read request signal input from an input unit for the address signal. A memory for outputting data from an output section, a latch means for latching an address signal sent on the bus and supplying the address signal to the input section of the memory, and the read request signal are effective. Output control means for outputting the output state of the output part of the memory to the bus during the interval, and controlling the output part and the bus to be in a disconnected state while the read request signal is invalid. A storage device characterized by the above. 2. The output control means is composed of a gate element whose output signal is switched to three types of “1”, “0”, and “high impedance” according to an input signal. The storage device described. 3. The memory further includes a selection unit that outputs a selection signal indicating whether or not to output a data signal from the memory based on an address signal latched and output by the latch unit. 2. The storage device according to claim 1, wherein the data signal is output in accordance with the address signal and the read request when the output of the data signal is indicated. 4. A control method for switching and transmitting an address signal and a data signal on the same bus, wherein the data signal is supplied in response to an address signal and a read request signal input from an address signal input section. An output step of outputting data from the memory from the output section, a step of latching an address signal sent on the bus and supplying the address signal to be provided to the input section of the memory, and the read request signal being valid While outputting the output state of the output unit of the memory to the bus, and controlling the output unit and the bus to be in a disconnected state while the read request signal is invalid. A control method characterized by the above.