JPH08242155A - Driving circuit device of power mosfet - Google Patents
Driving circuit device of power mosfetInfo
- Publication number
- JPH08242155A JPH08242155A JP7348406A JP34840695A JPH08242155A JP H08242155 A JPH08242155 A JP H08242155A JP 7348406 A JP7348406 A JP 7348406A JP 34840695 A JP34840695 A JP 34840695A JP H08242155 A JPH08242155 A JP H08242155A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- terminal
- power mosfet
- amplifier
- mosfet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/06—Modifications for ensuring a fully conducting state
- H03K17/063—Modifications for ensuring a fully conducting state in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0081—Power supply means, e.g. to the switch driver
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、 ａ）パワーＭＯＳＦＥＴのゲート端子に電圧増倍器の出
力端子が接続され、 ｂ）電圧増倍器は供給電圧源に接続可能である パワーＭＯＳＦＥＴの駆動回路装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power MOSFET driving circuit in which a) the output terminal of a voltage multiplier is connected to the gate terminal of a power MOSFET, and b) the voltage multiplier is connectable to a supply voltage source. Regarding the device.
【０００２】[0002]
【従来の技術】このような回路装置は例えばヨーロッパ
特許第０２３６９６７号明細書に記載されている。この
回路装置は、負荷抵抗に起因するソース電位変化が導通
制御を妨害するにも拘わらず、ソース側負荷を備えたＭ
ＯＳＦＥＴを完全に導通制御するために使われる。従っ
て、完全に導通制御するために、ゲート電位はアースを
基準として電圧増倍器によって供給電圧より大きい値に
高められる。2. Description of the Related Art Such a circuit arrangement is described, for example, in EP 0 236 967. This circuit device has a source side load M even though the source potential change due to the load resistance interferes with conduction control.
It is used to completely control the conduction of the OSFET. Thus, for full conduction control, the gate potential is raised to a value above the supply voltage by the voltage multiplier with reference to ground.
【０００３】今日、電子機器における開発は供給電圧を
ますます低くすることに向けられている。このための例
は２．７〜３Ｖの電池電圧を持つコードレス電話及び
３．３Ｖの電池電圧を持つラップトップコンピュータで
ある。しかしながら、このような低い供給電圧はパワー
ＭＯＳＦＥＴを完全に導通制御するのに十分ではない。
部分的に導通制御されたパワーＭＯＳＦＥＴは、しかし
ながら、完全に導通制御されたパワーＭＯＳＦＥＴに比
較して、大きい順方向抵抗ＲDSonを有し、このことは大
きい損失となる。Today, developments in electronic equipment are directed towards ever lowering supply voltages. Examples for this are cordless phones with a battery voltage of 2.7-3V and laptop computers with a battery voltage of 3.3V. However, such a low supply voltage is not sufficient to fully control the power MOSFET.
Partially conduction-controlled power MOSFETs, however, have a large forward resistance R DSon compared to fully conduction-controlled power MOSFETs, which results in large losses.
【０００４】この問題は複数のパワーＭＯＳＦＥＴの並
列接続又は大きなチップ面積によって解決することがで
きる。しかしながら、このような解決は高い費用を用い
てのみ可能である。This problem can be solved by parallel connection of a plurality of power MOSFETs or a large chip area. However, such a solution is possible only at high cost.
【０００５】[0005]
【発明が解決しようとする課題】そこで、本発明の課題
は、使用し得る供給電圧がパワーＭＯＳＦＥＴを完全に
導通制御するのに必要なゲート−ソース間電圧より小さ
い場合にもパワーＭＯＳＦＥＴの完全な導通制御を保証
するパワーＭＯＳＦＥＴの駆動回路装置を提供すること
にある。SUMMARY OF THE INVENTION The object of the present invention is therefore to achieve a complete power MOSFET even when the supply voltage which can be used is less than the gate-source voltage required to fully control the conduction of the power MOSFET. It is an object of the present invention to provide a drive circuit device for a power MOSFET that guarantees conduction control.
【０００６】[0006]
【課題を解決するための手段】上述の課題を解決するた
め、本発明によれば、 ｃ）電圧増倍器の出力端はパワーＭＯＳＦＥＴのゲート
端子とソース端子との間に接続され、 ｄ）電圧増倍器は使用し得る供給電圧より大きい出力電
圧を供給する。In order to solve the above problems, according to the present invention, c) the output terminal of the voltage multiplier is connected between the gate terminal and the source terminal of the power MOSFET, and d). The voltage multiplier provides an output voltage that is greater than the available supply voltage.
【０００７】[0007]
【実施例】本発明の実施例を図１及び図２を参照して詳
細に説明する。Embodiments of the present invention will be described in detail with reference to FIGS.
【０００８】図１に示された回路装置におけるパワーＭ
ＯＳＦＥＴは１を付されている。このパワーＭＯＳＦＥ
Ｔ１のドレイン端子Ｄは端子３に接続され、パワーＭＯ
ＳＦＥＴ１のソース端子Ｓは固定電位、例えばアース電
位に接続されている。パワーＭＯＳＦＥＴ１のゲート端
子Ｇは電圧増倍器２の第１の出力端子７に接続されてい
る。電圧増倍器２の第２の出力端子８はパワーＭＯＳＦ
ＥＴ１のソース端子Ｓに接続されている。電圧増倍器２
の第２の出力端子８は同様に固定電位、例えばアース電
位に接続されている。この第２の出力端子８はさらに入
力端子６に接続されている。電圧増倍器２は端子４及び
端子８を介して供給電圧ＶBB、例えば３Ｖの電池電圧に
接続されている。電圧増倍器は別の入力端子５を有して
いる。端子５、６は電圧増倍器２の入力端を形成してい
る。Power M in the circuit arrangement shown in FIG.
The OSFET is labeled 1. This power MOSFE
The drain terminal D of T1 is connected to terminal 3 and the power MO
The source terminal S of SFET1 is connected to a fixed potential, for example the ground potential. The gate terminal G of the power MOSFET 1 is connected to the first output terminal 7 of the voltage multiplier 2. The second output terminal 8 of the voltage multiplier 2 is a power MOSF
It is connected to the source terminal S of ET1. Voltage multiplier 2
The second output terminal 8 of is also connected to a fixed potential, for example ground potential. The second output terminal 8 is further connected to the input terminal 6. The voltage multiplier 2 is connected via a terminal 4 and a terminal 8 to a supply voltage V BB , for example a battery voltage of 3V. The voltage multiplier has a further input terminal 5. The terminals 5, 6 form the input of the voltage multiplier 2.
【０００９】パワーＭＯＳＦＥＴ１を導通制御するため
に、電圧増倍器２は入力端５、６を介して図２ａに示さ
れている入力電圧ＶINを与えられる。この入力電圧ＶIN
の大きさは例えば３Ｖの供給電圧ＶBBと高々同じであ
る。In order to control the conduction of the power MOSFET 1, the voltage multiplier 2 is supplied via the inputs 5, 6 with the input voltage V IN shown in FIG. 2a. This input voltage V IN
Is at most the same as the supply voltage V BB of , for example, 3V.
【００１０】入力電圧ＶINが電圧増倍器２の入力端に印
加されている間、電圧増倍器２は出力側でパワーＭＯＳ
ＦＥＴ１のゲート端子Ｇへ図２ｂに示されている例えば
６Ｖの大きさの高められた出力電圧ＶGSを供給する。こ
の大きさはパワーＭＯＳＦＥＴ１を完全に導通制御する
のに十分である。While the input voltage V IN is being applied to the input end of the voltage multiplier 2, the voltage multiplier 2 has a power MOS on the output side.
The gate terminal G of the FET 1 is supplied with an increased output voltage V GS of the magnitude shown in FIG. This size is sufficient to completely control the power MOSFET 1.
【００１１】この実施例の電圧増倍器２は例えばヨーロ
ッパ特許第０２３６９６７号明細書に記載されている電
圧二倍化の公知の原理に基づいて構成することができ
る。この場合、ソースホロワとして作動されるＭＯＳＦ
ＥＴを駆動するために電圧二倍器が使用される。この電
圧二倍器はＭＯＳＦＥＴのゲートリード線内に位置して
直列に接続された２つのダイオードと、１つのコンデン
サとを含んでいる。コンデンサの第１の端子は両ダイオ
ードの中間接続点に接続され、コンデンサの第２の端子
にはパルス発生器からクロック化された直流電圧が供給
される。これによって、ＭＯＳＦＥＴのゲート端子に接
続されている方のコンデンサの端子における電圧は、動
作電圧より大きくしかもＭＯＳＦＥＴを完全に導通させ
る電圧に充電される。The voltage multiplier 2 of this embodiment can be constructed on the basis of the known principle of voltage doubling, for example as described in EP 0 236 967. In this case, MOSF operated as a source follower
A voltage doubler is used to drive the ET. The voltage doubler includes two diodes located in the gate lead of the MOSFET and connected in series, and a capacitor. The first terminal of the capacitor is connected to the intermediate connection point of both diodes, and the second terminal of the capacitor is supplied with the clocked DC voltage from the pulse generator. As a result, the voltage at the terminal of the capacitor which is connected to the gate terminal of the MOSFET is charged to a voltage higher than the operating voltage and yet to bring the MOSFET into full conduction.
【００１２】この実施例においてはパルス発生器は電圧
増倍器２の構成要素である。パルス発生器は、入力電圧
ＶINが電圧増倍器２の入力端に印加されている間、その
入力電圧ＶINによって制御されて、クロック化された直
流電圧を発生する。しかしながら、パルス発生器は入力
端５、６にも接続することができ、従ってクロック化さ
れた直流電圧を外部から供給することができる。In this embodiment, the pulse generator is a component of the voltage multiplier 2. Pulse generator, while the input voltage V IN is applied to the input terminal of the voltage multiplier 2 is controlled by the input voltage V IN, it generates a clocked DC voltage. However, the pulse generator can also be connected to the inputs 5, 6 and can therefore be supplied with a clocked DC voltage externally.
【図１】本発明による回路装置を示す接続図である。FIG. 1 is a connection diagram showing a circuit device according to the present invention.
【図２】ａは電圧増倍器の入力端における電圧（ＶIN）
の時間的変化、ｂは電圧増倍器の出力端における電圧
（ＶGS）の時間的変化を示す波形図である。FIG. 2a is a voltage (V IN ) at the input terminal of the voltage multiplier
Is a waveform diagram showing the temporal change of the voltage (V GS ) at the output terminal of the voltage multiplier.
１ パワーＭＯＳＦＥＴ ２ 電圧増倍器 ３ 端子 ４ 端子 ５ 入力端子 ６ 入力端子 ７ 第１出力端子 ８ 第２出力端子 1 power MOSFET 2 voltage multiplier 3 terminal 4 terminal 5 input terminal 6 input terminal 7 first output terminal 8 second output terminal
───────────────────────────────────────────────────── フロントページの続き (72)発明者 イエネ チハニ ドイツ連邦共和国 85551 キルヒハイム イザールヴエーク 13 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Jene Hani Germany Federal Republic of Germany 85551 Kirchheim Isarwewijk 13
Claims (5)
電圧増倍器の出力端子が接続され、 ｂ）電圧増倍器は供給電圧源に接続可能であるパワーＭ
ＯＳＦＥＴの駆動回路装置において、 ｃ）電圧増倍器（２）の出力端（７、８）はパワーＭＯ
ＳＦＥＴ（１）のゲート端子（Ｇ）とソース端子（Ｓ）
との間に接続され、 ｄ）電圧増倍器（２）は使用し得る供給電圧（ＶBB）よ
り大きい出力電圧（ＶGS）を供給する ことを特徴とするパワーＭＯＳＦＥＴの駆動回路装置。1. A power M in which a) a gate terminal of a power MOSFET is connected to an output terminal of a voltage multiplier, and b) the voltage multiplier is connectable to a supply voltage source.
In the drive circuit device of the OSFET, c) the output terminals (7, 8) of the voltage multiplier (2) are power MO
Gate terminal (G) and source terminal (S) of SFET (1)
D) The voltage multiplier (2) supplies an output voltage (V GS ) larger than the usable supply voltage (V BB ) and a driving circuit device for a power MOSFET.
（１）と同じケース内に組込まれていることを特徴とす
る請求項１記載の回路装置。2. The voltage multiplier (2) is a power MOSFET.
The circuit device according to claim 1, wherein the circuit device is incorporated in the same case as (1).
されていることを特徴とする請求項１又は２記載の回路
装置。3. Circuit arrangement according to claim 1, characterized in that the voltage multiplier (2) is formed as an integrated circuit.
（１）とは同一チップ上に集積されていることを特徴と
する請求項３記載の回路装置。4. A voltage multiplier (2) and a power MOSFET.
4. The circuit device according to claim 3, wherein (1) is integrated on the same chip.
ことを特徴とする請求項３又は４記載の回路装置。5. Circuit arrangement according to claim 3 or 4, characterized in that the voltage multiplier (2) comprises a pulse generator.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE4446327.8 | 1994-12-23 | ||
| DE4446327A DE4446327A1 (en) | 1994-12-23 | 1994-12-23 | Power MOSFET trigger circuit esp for cordless telephone or laptop computer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08242155A true JPH08242155A (en) | 1996-09-17 |
Family
ID=6536934
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7348406A Withdrawn JPH08242155A (en) | 1994-12-23 | 1995-12-18 | Driving circuit device of power mosfet |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPH08242155A (en) |
| KR (1) | KR960027330A (en) |
| DE (1) | DE4446327A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015520537A (en) * | 2012-04-04 | 2015-07-16 | クリー インコーポレイテッドＣｒｅｅ Ｉｎｃ． | High voltage driver |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8963576B2 (en) | 2012-10-19 | 2015-02-24 | Cree, Inc. | Increased transition speed switching device driver |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE6900750U (en) * | 1968-12-04 | 1969-06-04 | Wilhelm Koenig | TRUCKS FOR IN PARTICULAR MONITAR TRACKS |
| US4737667A (en) * | 1986-03-11 | 1988-04-12 | Siemens Aktiengesellschaft | Driving circuitry for a MOSFET having a source load |
-
1994
- 1994-12-23 DE DE4446327A patent/DE4446327A1/en not_active Ceased
-
1995
- 1995-12-18 JP JP7348406A patent/JPH08242155A/en not_active Withdrawn
- 1995-12-22 KR KR1019950054326A patent/KR960027330A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015520537A (en) * | 2012-04-04 | 2015-07-16 | クリー インコーポレイテッドＣｒｅｅ Ｉｎｃ． | High voltage driver |
Also Published As
| Publication number | Publication date |
|---|---|
| KR960027330A (en) | 1996-07-22 |
| DE4446327A1 (en) | 1996-07-04 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Application deemed to be withdrawn because no request for examination was validly filed |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20030304 |