JPH0823993B2 - Semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a serial memory device that can quickly return to an address 0 from an arbitrary address.

(Prior Art) A serial storage device (hereinafter referred to as a serial memory) is a memory that is being rapidly developed with the development of digital processing technology for video signals. That is, since the input / output format of this memory, which can perform writing and reading serially, is very suitable for digital processing of video signals, it is actively used in this technical field today.

Currently developed memory structures of this type usually consist of a matrix storage plane of static semiconductor storage cells. Here, the external data is from the 0th address of the 1st row and 1st column attached to each intersection of the matrix to the last mth row and nth row.
In the memory cells arranged one by one up to the address k of the column, one bit is sequentially written in sequence according to the order of array addresses, and is immediately read in this order. Therefore, when it is composed of 7 to 11 bits like a digital coded signal of a video signal, as many matrix storage planes as the number of bits are prepared.

By the way, in order to serially read the written external data from this storage plane, first, the respective address storage data of the first row are read at once and then sequentially output in the column number order. While this read operation is being performed, the next data is written in each address storage cell of the second row and the read preparation is completed. Therefore, the same operation is performed for each address of the second row. The reading is continued. The final m-th
Each address storage data up to the nth row is sequentially written and read out serially according to the control system of the storage device.

(Problems to be Solved by the Invention) As described above, in a normal use state, the entire storage plane is activated and writing and reading from addresses 0 to k are repeatedly executed. However, it is often the case that only a partial area of the storage plane should be limitedly used in this serial memory. For example, a case where another video signal is inserted into a part of one video signal and a small screen is simultaneously displayed on the television receiving surface corresponds to this. In such a case, since the serial memory on the video signal side to be inserted is limitedly used only in a partial area of the storage plane, writing and reading from address 0 to an arbitrary address are repeated unlike the usual case. Must be carried out. That is, 0 from any address
It is required to have a reset function to quickly return to the address.

According to the conventional serial memory, this reset function responds to a write inhibit signal from the outside to inhibit writing after a specified address and resets each row and column selection operation by a series of control operations. Given. However, the reset request to the address 0 occurs at an indefinite time, as is clear when considering the scene of inserting a small screen on the television receiving surface. Therefore, in the conventional reset operation of starting the write / read operation of each address memory cell of the first row including the address 0 after the external write inhibit signal is input, a large delay occurs in the access time. It is impossible to promptly output the data of address 0 and below at the time.

(Object of the Invention) In view of the above situation, it is an object of the present invention to provide a semiconductor memory device having a serial memory configuration that can return to address 0 from any address extremely quickly.

(Structure of the Invention) In a semiconductor memory device of the present invention, a memory plane in which a plurality of memory cells are arranged in a matrix of rows and columns, and a row in which the memory cells in the memory plane are selected and read in row units A selection read circuit, a column selection output circuit that sequentially selects the memory cells read by the row selection read circuit in units of rows and serially outputs the memory cells to the first data bus, the row selection read circuit, and the column selection A reset signal generation circuit connected to the output circuit, and when the reset signal is output from the reset signal generation circuit, the row selection read circuit and the column selection output circuit are reset to store the start address of the storage plane. In a semiconductor memory device for selecting cells,
A latch circuit that receives and latches the data in the memory cell at the head address via a second data bus independent of the first data bus, and a read signal every time the row selection read circuit is reset. A signal generating circuit for generating a latch circuit is provided, and the latch circuit outputs the latched data in response to the read signal, and is selected by the column selection output circuit excluding the memory cell at the head address during this period. The data of the stored memory cell is read onto the first data bus, whereby the data of the latch circuit is output every time the row selection read circuit is reset, and then the data of the first data bus is output. It is characterized by being done.

(Means for Solving Problems) That is, according to the present invention, a read control system independent of other address storage cells is prepared for the 0th address storage cell. That is, the read preparation system is capable of immediately reading the written data regardless of the read control system of the storage device and latching it via a dedicated data bus and immediately outputting it in response to the generation of a reset signal to address 0. A read control system that arranges the above is independently provided.

(Function) The reset signal to the address 0 is read when the reading from the last address k is completed in the normal use state, and when the limited use of the memory plane is completed, the reading from the specified arbitrary address is completed. When each is generated. This is exactly the same as the conventional one. However, in any case, the data written in the address 0 is output almost at the same time when the read operation returns to the address 0. At this time, the write and read operations are prepared while the 0-address data is being output to each address storage cell after the 1-address, and the 0-address data is continuously output. Therefore, it is necessary in any case. It is possible to promptly output write data at addresses 0 and below at the time. Hereinafter, the present invention will be described in detail with reference to the drawings.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of the present invention.
In this embodiment, each address storage cells arranged in a matrix of external data, i.e., address 0 stored cells M _0, 1 address memory cells M _1, ..., a address storage cell M _a, ..., i addresses memory cells M _i 、…
And the serial data write storage plane 1 for serially writing to the last k address storage cells and the write data of each address storage cell after the first address except the 0th address storage cell M ₀ , the row selection address signal of the storage device. In response to, the row selection read circuit 2 for sequentially reading in units of row (for example, from address 1 to address a)
A column select output circuit 4 comprising a shift register for outputting the read write data to the first data bus 3 in the column number order in response to the output drive signal p _{1; A} second data bus 5 exclusively occupied by 0, and an address latch circuit 6 connected to this second data bus for immediately latching write data read by a memory cell at address 0 regardless of a row selection address signal. In response to a reset signal (not shown) for the row selection read circuit 2 generated when the storage device completes reading the final address or a similar reset signal p ₃ generated by a write inhibit signal p ₂ from the outside. An address read signal generation circuit 7 and a reset signal generation circuit 8 of the column selection output circuit 2 which operate,
Selective output circuit 9 outputs serially read output D with address 0 data unlatched by address read signal p ₄ and read data from the first data bus.
Here, 10 and 11 generate a reset signal p ₃ for the write inhibit circuit and row selection read circuit 2 for inhibiting all writing to the memory cells after the specified address in response to the external write inhibit signal p ₂ , respectively. Reset circuit.

Although only one bit of storage plane is shown in this embodiment, this is sufficient to understand the write / read operation. That is, since all one data is written in the same address, no matter how many bits this data consists of, the leading input data are all stored in the address 0 storage cell M ₀ in this figure.
Further, it is safe to consider that all the following input data are serially written in the address 1 storage cell M ₁ . According to this explanation, the leading input data written at the address 0 is immediately read out regardless of the write / read operation of the data to be subsequently input at the addresses 1 and thereafter, and is passed through the proprietary second data bus 5. Address 0 data latch circuit 6
It is ready to output at any time. The address 0 data placed in this state is unlatched by the address 0 read signal p ₄ generated every time the reading of the memory device returns to address 0, that is, every time the row selection read circuit 2 is reset, and the selected output is immediately output. It is output from the circuit 9. At this time, the address 0 read signal p ₄ is always activated in response to the reset signal of the row selection read circuit 2 even when the memory device is in the normal use state or the limited use state. Since the address read signal generation circuit 7 outputs it, even if a read reset from an arbitrary address to address 0 is unexpectedly applied at an indefinite time, 0 address data is set to 1 in response to this.
Address data can be output prior to other address data below. This read reset from an arbitrary address to address 0 prohibits all writing after the specified address by the write inhibit circuit 10 which responds to the write inhibit signal p ₂ as in the conventional case, and the row selection read circuit 2 and the column selection output. This is performed by resetting each of the circuits 4. However, during this period, the preparation for the data writing and reading operation for the addresses 1 and below is completed and the data is continuously output after the address 0, so that there is no problem in delaying the access time. Absent.

The semiconductor memory device of the present invention has the highest speed when all memory cells are formed by static semiconductor memory elements. However, it does not prevent the use of the dynamic memory cell except for the address 0 memory cell. That is, a part of the memory cells including the address 0 may be formed as a static semiconductor memory cell and all the remaining address memory cells may be formed as a dynamic semiconductor memory cell, or a memory plane division method as is conventionally done. May be incorporated into this. In this way, it is possible to achieve high integration of the storage device without significantly affecting the operation speed.

(Effects of the Invention) As described in detail above, according to the present invention, the write data to the address 0 memory cell is immediately read and latched, and immediately output in response to the occurrence of the read reset. Therefore, a serial read-out function with an excellent read reset function that can return from any address to address 0 very quickly
Since it is suitable for the structure of the memory, it can be used effectively in the field of digital processing of video signals, for example.

[Brief description of drawings]

The drawing is a block diagram showing an embodiment of the present invention. 1 ... Serial data writing / storage plane, 2 ... Row selection / reading circuit, 3 ... First data bus, 4 ... Column selection output circuit, 5 ... Second data bus, 6 ... 0 address data latch circuit, 7 ... 0 address data read signal generation circuit, 8,
11 …… Reset signal generation circuit, 9 …… Selection output circuit, 10
...... write inhibit circuit, M ₀ ...... 0 address memory cells, M _1, M _a,
M _i , M _k ... each address storage cell, p ₁ ... output drive signal, p ₂ ...
… Write inhibit signal, p ₃ , p ₅ …… Reset signal, p ₄ …… Address 0 data read signal, D …… Serial read output.

Front page continuation (72) Inventor Shuichi Imaseki 5-7-15 Shiba, Minato-ku, Tokyo NEC Electricity Microcomputer System Co., Ltd. (72) Hiroaki Ikeda 5-7-15 Shiba, Minato-ku, Tokyo Japan Electric Icy Microcomputer System Co., Ltd. (56) References JP-A-53-136924 (JP, A)

Claims (1)

[Claims] 1. A storage plane in which a plurality of storage cells are arranged in a matrix of rows and columns, a row selection read circuit for selecting and reading out the storage cells in the storage plane row by row, and the row selection. A column selection output circuit that sequentially selects the memory cells read in row units by the reading circuit and serially outputs the memory cells to the first data bus, and a reset signal connected to the row selection reading circuit and the column selection output circuit. A semiconductor memory device including a generating circuit, and resetting the row selection reading circuit and the column selection output circuit when the reset signal is output by the reset signal generating circuit to select a memory cell at a head address of the memory plane. A latch circuit for receiving and latching the data of the memory cell at the head address via a second data bus independent of the first data bus, and the row selective reading A signal generating circuit for generating a read signal to the latch circuit each time the path is reset, and the latch circuit outputs the latched data in response to the read signal, and during this period, the start address The data of the memory cells selected by the column selection output circuit excluding the memory cells is read onto the first data bus, whereby the data of the latch circuit is output every time the row selection read circuit is reset. After that, the data of the first data bus is output, and the semiconductor memory device is characterized.