JPH08236700A - High frequency integrated circuit - Google Patents

Abstract

PURPOSE: To reduce leakage of signal to the pad side over a wide band by selecting the effective electrical length of a DC feeder line equal to a predetermined amount of the wavelength of signal and inserting a thin film resistor into the DC feeder line. CONSTITUTION: A line connected with an active element 1 and terminated at via holes 7, 17 through first thin film capacitors 4, 14 is connected with pads 2, 12 through DC feeder lines 5, 15. The line is also connected with the via holes 7, 17 through second thin film capacitors 3, 13 at the joints of the DC feeder lines 5, 15 and the pads 2, 12. Furthermore, the effective electrical length between the effective short circuit point of the via holes 7, 17 through the second thin film capacitors 3, 13 and the joint of the lines 8, 22 and the DC feeder lines 5, 15 is selected equal to a quarter of the wavelength of signal and thin film resistors 6, 16 are inserted into the DC feeder line 5, 15. Since the signal is attenuated through the thin film resistors 6, 16, the characteristics can be improved over a wide range.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit for high frequencies such as microwaves and millimeter waves, which is provided with active elements such as FETs and HEMTs. High frequency integrated circuits are MMIC (MICROWA
ve Monolithic Integrated Circuit) structures are becoming common, and FET (field effect transistor) and H
A bias circuit for supplying a DC bias to an active element such as an EMT (high electron mobility transistor) is configured, and it is necessary to prevent a signal component from leaking through this bias circuit.

[0002]

2. Description of the Related Art FIG. 4 is an explanatory view of a conventional example.
A case where a (field effect transistor) is used as the active element 31 is shown. G is a gate terminal, S is a source terminal, D is a drain terminal, 32 and 42 are bias supply pads, and 33 and 3 are.
4, 43 are thin film capacitors, 35, 36, 45 and 46 are lines, 37 and 47 are via holes, 38 is an input terminal,
39 indicates an output terminal.

The source S of the active element 31 is a balanced type and is connected to the ground by via holes 37 and 47, and a DC bias is supplied from the bias supply pad 42 to the gate G of the active element 31 through lines 45 and 46. , The drain D of the active element 31 from the pad 32 through the line 35
A DC bias is supplied to the input terminal to operate as a source-grounded amplifier, and the input signal from the input terminal 38 is amplified by the active element 31 and output from the output terminal 39.

Each of the thin film capacitors 33, 34 and 43 has a dielectric thin film interposed between an upper electrode and a lower electrode, and the lower electrode is grounded by the via holes 37 and 47. As a result, the line 46 connected between the input terminal 38 and the gate terminal G and the thin film capacitor 4
3 and the via hole 47 form a terminating short circuit stub for matching, and the line 45 from the pad 42 is also connected to the thin film capacitor 43. The pad 42 is connected to the DC bias power source and a gold wire (not shown). It is connected and a DC bias is supplied to the gate G.

Further, the line 36 connected between the output terminal 39 and the drain terminal D, the thin film capacitor 33, and the via hole 37 form a terminating short circuit stub for matching, and the thin film capacitor 33 is formed on the pad 32. , 34 are connected to the pad 32 by a DC power supply (not shown) and a gold wire or the like to supply a DC bias to the drain terminal D.

Also in the path for supplying the DC bias from the pad 42, it is possible to connect the thin film capacitor 43 and the other thin film capacitor to the line 45 as in the case of the pad 32 side.

FIG. 5 is a characteristic curve diagram of a conventional example. When the signal frequency in FIG. 4 is 30 GHz, the frequencies 0 to 5 of the path for supplying the DC bias from the pad 42 are shown.
The characteristic of 0 GHz is shown, and S31 is from the line 46 to the pad 4
2, S21 is the attenuation of the signal transmitted from the line 46 to the via hole 47, and S11 is the reflection loss of the signal in the thin film capacitor 43.

FIG. 6 is a characteristic curve diagram of a conventional example, where the signal frequency in FIG. 4 is 30 GHz and the effective short-circuit point of the via hole 37 from the connection point between the line 35 and the thin film capacitor 33 via the thin film capacitor 34. Is set to 1/4 of the signal wavelength, and a characteristic of a frequency of 0 to 50 GHz of a path for applying a DC voltage from the pad 32 to the drain terminal D is shown. S31 is a signal transmitted from the line 36 to the pad 32. , S21 is the attenuation of the signal transmitted from the line 36 to the via hole 37, and S11 is the reflection loss of the signal in the thin film capacitor 33.

[0009]

However, there is a problem such as parasitic oscillation due to a signal leaking from the pads 32 and 42 for connecting to an external bias circuit. For example, the signal leaking toward the pad 42 in the path for supplying the DC bias from the pad 42 in FIG. 4 is large over a wide band as shown in S31 of FIG. Therefore, there is a problem that low frequency parasitic oscillation is likely to occur due to the action with the DC bias power supply circuit connected to the pad 42 by a gold wire or the like.

To reduce such signal leakage,
It suffices if the capacitance of the thin film capacitor 43 is sufficiently large, but in order to increase the capacitance, the electrode area must be increased, which makes it difficult to form a high-density integrated circuit.

In the path for supplying the DC voltage from the pad 32, an extra thin film capacitor 34 is provided, and an effective short-circuit point of the via hole 37 from the contact point between the line 35 and the thin film capacitor 33 via the thin film capacitor 34. By setting the effective length up to 1/4 of the signal wavelength of the frequency of 30 GHz, the reflection (S11) at the frequency of 30 GHz becomes sufficiently smaller than the characteristic shown in FIG. Attenuation amount of signal to (S31)
Also, it can be increased by about 10 dB as compared with the characteristic shown in FIG. 5 (see FIG. 6).

However, although the characteristics around the frequency of 30 GHz are improved, higher frequency band and 5 GH are better than that.
Since a sufficient amount of attenuation cannot be obtained in a low frequency band equal to or lower than z, there is a large possibility of parasitic oscillation. There is also a problem that the reflection loss (S11) also increases in the low frequency band. An object of the present invention is to improve characteristics over a wide band with a relatively simple structure.

[0013]

The high frequency integrated circuit of the present invention will be described with reference to FIG. 1. The high frequency integrated circuit includes a structure for supplying a DC bias for operating an active element such as an FET from a bias supply pad. In the high frequency integrated circuit, the first thin film capacitors 4 and 14 connected to the active element 1 and terminated at the first end
The lines shorted by the via holes 7 and 17 through the pads and the pads 2 and 12 are connected by the DC supply lines 5 and 15, and the DC supply lines 5 and 15 and the pads 2 and 12 are connected.
Is connected to the via holes 7 and 17 via the second thin film capacitors 3 and 13 at the connection point with the line 8 from the effective short-circuit point of the via holes 7 and 17 via the second thin film capacitors 3 and 13, The effective electrical length up to the connection point between 22 and the DC supply lines 5 and 15 was selected to be 1/4 of the signal wavelength, and thin film resistors 6 and 16 were provided in the DC supply lines 5 and 15.

[0014]

By selecting the effective electrical length of the DC supply lines 5 and 15 to be 1/4 of the signal wavelength, the pad 2 is connected from the connection point between the lines 8 and 22 connected to the active element 1 and the DC supply lines 5 and 15. , 12 side becomes infinite in the vicinity of the operation center frequency, and signal leakage to the pads 2 and 12 side can be reduced. Further, by providing the thin film resistors 6 and 16 in the DC supply lines 5 and 15, attenuation is given to signals of frequencies other than the operation center frequency band, and therefore signals to the pads 2 and 12 side are attenuated. Leakage can be reduced over a wide band.

[0015]

FIG. 1 is an explanatory view of an embodiment of the present invention, in which FE
The case where T (field effect transistor) is used as the active element 1 is shown, G is a gate terminal, S is a source terminal, and D is a drain terminal. 2, 12 are pads, 3, 13 are second thin film capacitors, 4, 14 are first thin film capacitors, 5,
15 is a DC supply line, 6 and 16 are thin film resistors, 7 and 10,
11, 17 are via holes, 9 are output terminals, 8, 1
8, 19, 22, 23 are lines 3a, 3b, 4a, 4
b, 13a, 13b, 14a and 14b are electrodes 3c and 4
Reference numerals c, 13c and 14c are dielectric thin films.

The thin film capacitors 3, 4, 13, 14 have electrodes 3a, 3b, 4a, 4b, 13a, 13b, respectively.
Dielectric thin films 3c, 4c, 13c, 1 between 14a, 14b
4c is interposed, the lower electrodes 3b, 4b,
13b and 14b are connected to the ground electrode under the substrate through the via holes 7 and 17, respectively. The upper electrode 3a,
4a, 13a, 14a and lower electrodes 3b, 4b, 13
In general, the areas of b and 14b are the same, but the area of the lower electrode is shown large in order to show the arrangement configuration of the electrodes.

In the path for supplying the DC bias from the pad terminal 2 to the drain D, the case where the linear DC supply line 5 is provided is shown, and the path for supplying the DC bias from the pad 12 to the gate terminal G is shown. In this case, the case where the meandering DC supply line 15 is provided is shown, but the DC supply lines having the same configuration can be used for both. Also active element 1
Of the balanced type source terminal S is connected to the via holes 10 and 11 via the lines 18 and 19, and the line 23 connected to the drain terminal D of the active element 1 is connected to the via 8 and the first thin film capacitor 4. To the via hole 7 and the line 8 is connected to the DC supply line 5 described above. Also, the connection point between the pad 2 and the DC supply line 5 is connected to the via hole 7 via the second thin film capacitor 3.

The line 22 connected to the gate terminal G of the active element 1 is connected to the via hole 17 via the first thin film capacitor 14, and the DC supply line 15 described above is connected to this line.
Connect. The connection point between the DC supply line 15 and the pad 12 is connected to the via hole 17 via the second thin film capacitor 13. Then, from the pad 2 to the active element 1
A DC bias to the drain terminal D of the active element via the DC supply line 5 and the line 8, and a DC bias from the pad 12 to the gate terminal G of the active element 1 via the DC supply line 15 and the line 22. Thus, it can operate as an oscillator. In this case, for example, it is possible to oscillate at 30 GHz, and add the oscillation output to a multiplier (not shown) in the subsequent stage to perform multiplication.

2A and 2B are explanatory views of a main part of the embodiment of the present invention. FIG. 2A shows a main part of a path for supplying a DC bias from the pad 2 to the drain terminal D, and FIG. The cross section of the main part with the via hole 7 is shown (C)
Shows an equivalent circuit.

The DC bias from the pad 2 is applied to the drain terminal D of the active element 1 via the DC supply line 5 and the line 8.
The thin film capacitors 3 and 4 are connected to the connection point between the DC supply line 5 and the pad 2 and the connection point between the DC supply line 5 and the line 8, respectively.
A thin film resistor 6 is provided inside.

As shown in (B), the thin film capacitor 3 is composed of a lower electrode 3b on the substrate 20, a dielectric thin film 3c and an upper electrode 3a, and the electrode 3a is connected to the pad 2 and the DC supply line 5. To do. Further, the lower electrode 3b is connected to the lower ground electrode 21 of the substrate 20 through the via hole 7.

Therefore, the equivalent circuit is as shown in FIG.
Both ends of the DC supply line 5 are connected to the ground via the first and second thin film capacitors 4 and 3 to form a circuit configuration, and an effective short-circuit point A and a connection point B between the line 8 and the DC supply line 5 are provided. Between the effective electrical length L and the signal wavelength of the operating center frequency
Select / 4. As a result, the impedance seen from the connection point B between the line 8 and the DC supply line 5 to the pad 2 side becomes infinite near the operation center frequency. Therefore, signal leakage can be reduced.

Outside the operation center frequency band, since the thin film resistor 6 is provided in the DC supply line 5, the thin film resistor 6 attenuates the signal. The connection position of the thin film resistor 6 can be an arbitrary position of the DC supply line 5. If the value of the thin film resistor 6 is increased, the signal leaking to the pad 2 side can be greatly attenuated, but it is necessary to increase the DC bias voltage supplied. Therefore, the signal in the frequency band other than the operation center frequency band is set to a value that attenuates without increasing the DC bias voltage.

Further, in FIG. 1, also in the path for supplying a DC bias from the pad 12 to the gate terminal G of the active element 1, the DC supply line 15 has a meandering shape and has a desired length in a narrow space. The characteristics similar to those of the configuration in which a DC bias is supplied from the pad 2 to the drain terminal D of the active element 1 are obtained except for the configuration in which the.

FIG. 3 is a characteristic curve diagram of an embodiment of the present invention. In the configuration shown in FIG. 1, the operation center frequency is 30 GH.
In the case of z, S11, S21, and S31 are, as in FIGS. 5 and 6, reflection loss from the connection point between the line and the thin film capacitor to the line, attenuation of the signal from the line to the via hole, and Represents the amount of signal attenuation to the pad side.

As is clear from the comparison between the characteristics of FIG. 3 and the characteristics of FIG. 6, according to the embodiment of the present invention, the reflection (S11) at the operating center frequency of 30 GHz has substantially the same attenuation amount. However, 2 in the frequency band lower than the operating center frequency
At 0 GHz, it is improved by about 5 dB, and at 10 GHz, it is improved by about 12 dB. Further, it is improved by about 4 dB at 40 GHz, which is a frequency band higher than the operation center frequency, and is improved by about 10 dB at 50 GHz.

Further, the attenuation amount (S31) of the signal toward the pads 2 and 12 is improved by about 1 dB at the operation center frequency of 30 GHz, and about 5 dB at 20 GHz of the frequency band lower than the operation center frequency. Improved,
It is improved by about 8 dB at 10 GHz. Further, it is improved by about 8 dB at 40 GHz which is a frequency band higher than the operation center frequency, and is improved by about 12 dB at 50 GHz.

As described above, the characteristics can be improved over a wide band, and therefore the possibility of parasitic oscillation due to the connection of the DC bias supply circuit to the pads 2 and 12 can be greatly reduced. Also, the above-mentioned embodiment is 3
Although an oscillator of 0 GHz is shown, it can be applied to a high frequency integrated circuit provided with various active elements such as an oscillator or an amplifier having a frequency other than this. Further, the active element 1 is not only the FET (field effect transistor) as described above, but also the HEM.
High frequency active elements such as T and HBT can be applied.

[0029]

As described above, the present invention relates to an FET
Is connected to an active element 1 such as a HEMT or a HEMT, and the terminating ends are via holes 7 and 1 via first thin film capacitors 4 and 14.
The line short-circuited by 7 and the pads 2 and 12 are connected by the DC supply lines 5 and 15, and the second thin film capacitors 3 and 3 are connected to the connection points between the DC supply lines 5 and 15 and the pads 2 and 12. Via holes 7 and 17 are connected via 13, and the effective electrical length from the effective short-circuit point of the via holes 7 and 17 to the connection point between the line and the DC supply lines 5 and 15 is set to 1/4 of the signal wavelength. Set this DC supply line 5,1
By providing thin film resistors 6 and 16 in 5, the impedance seen from the line connected to the active element 1 to the pads 2 and 12 becomes infinite near the operation center frequency, and the impedance goes to the pads 2 and 12 direction. It is possible to reduce the leakage of the signal. Further, in the frequency band other than the operation center frequency, the signals can be attenuated by the thin film resistors 6 and 16, so that the characteristics can be improved over a wide band and the possibility of parasitic oscillation can be greatly reduced.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of an embodiment of the present invention.

FIG. 2 is an explanatory view of a main part of the embodiment of the present invention.

FIG. 3 is a characteristic curve diagram of an example of the present invention.

FIG. 4 is an explanatory diagram of a conventional example.

FIG. 5 is a characteristic curve diagram of a conventional example.

FIG. 6 is a characteristic curve diagram of a conventional example.

[Explanation of symbols]

 1 Active Element 2,12 Pad 3,13 Second Thin Film Capacitor 4,14 First Thin Film Capacitor 5,15 DC Supply Line 6,16 Thin Film Resistor 7,17 Via Hole

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tamio Saito 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Kazuo Shirakawa 1015, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited ( 72) Inventor Toshihiro Shimura 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (1)

[Claims] 1. A high frequency integrated circuit including a structure for supplying a DC bias for operating an active element from a bias supply pad, wherein the termination is connected to the active element via a first thin film capacitor. The line short-circuited by the via hole and the pad are connected by a direct current supply line, and the connection point between the direct current supply line and the pad is connected to the via hole via a second thin film capacitor. The effective electrical length from the effective short-circuit point of the via hole through the thin film capacitor of 2 to the connection point of the line and the DC supply line,
A high frequency integrated circuit characterized in that it is selected to be 1/4 of a signal wavelength and a thin film resistor is provided in the DC supply line.