JPH08236609A - Isolation method for semiconductor device - Google Patents
Isolation method for semiconductor deviceInfo
- Publication number
- JPH08236609A JPH08236609A JP4030895A JP4030895A JPH08236609A JP H08236609 A JPH08236609 A JP H08236609A JP 4030895 A JP4030895 A JP 4030895A JP 4030895 A JP4030895 A JP 4030895A JP H08236609 A JPH08236609 A JP H08236609A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- recess
- groove
- oxide film
- trench
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
Landscapes
- Local Oxidation Of Silicon (AREA)
- Drying Of Semiconductors (AREA)
- Element Separation (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、半導体装置の素子分
離方法の改良に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in an element isolation method for semiconductor devices.
【０００２】[0002]
【従来の技術】従来、素子分離技術として、長い間ＬＯ
ＣＯＳ（Ｌocal Ｏxidation of Ｓilicon）法が用いら
れてきた。しかし、ＬＯＣＯＳ法では、バーズビークと
呼ばれる酸化膜の横広がり現象が生じる為、分離領域が
大きくなってしまうという問題があった。2. Description of the Related Art Conventionally, as element isolation technology, LO
The COS (Local Oxidation of Silicon) method has been used. However, the LOCOS method has a problem that the isolation region becomes large because a lateral spreading phenomenon of an oxide film called bird's beak occurs.
【０００３】この問題を解決するためにトレンチ分離技
術が開発された。これは、シリコン等からなる基板に該
基板面と垂直な穴を掘るもので、バーズビークがないた
め分離領域を設計どおりに形成できるという利点を有す
る。つまり、微細化に適した素子分離方法である。しか
し、０．６μｍルールのデバイスが市販されている現在
でも素子分離の主役はＬＯＣＯＳ法である。Trench isolation techniques have been developed to solve this problem. This is to dig a hole perpendicular to the substrate surface in a substrate made of silicon or the like, and has an advantage that the isolation region can be formed as designed because there is no bird's beak. That is, it is an element isolation method suitable for miniaturization. However, the LOCOS method still plays a major role in element isolation even when a device having a rule of 0.6 μm is commercially available.
【０００４】トレンチ法には、掘った穴を絶縁膜等で埋
め込むこと及び埋め込み部以外の絶縁膜等をエッチバッ
ク等で除去し、平坦化する必要がある。この絶縁膜等の
埋め込みでは、トレンチ穴エッジ（開孔上部）にオーバ
ハングによるボイドの発生等が問題であり、例えばＵＳ
Ｐ４６２６３１７では、これを回避する為、膜堆積→エ
ッチバック→膜堆積という繰り返しでオーバーハング部
を削りながらトレンチを埋め込んでいくという方法が提
案されている。In the trench method, it is necessary to fill the dug hole with an insulating film or the like and to remove the insulating film or the like other than the buried portion by etching back or the like to flatten the surface. The embedding of the insulating film or the like has a problem that voids are generated due to overhang at the trench hole edge (upper part of the hole).
In order to avoid this, P4626317 proposes a method of burying the trench while removing the overhang portion by repeating film deposition → etchback → film deposition.
【０００５】また、一方では、制御の難しいエッチバッ
クプロセスを避けるため、例えばＵＳＰ５１３０２６８
（図８参照）のように選択エピタキシャルシリコン法を
用い、トレンチ内のみにシリコンをトレンチ深さの〜４
０％だけ堆積し、続く熱酸化によるシリコンの体積膨張
を利用してトレンチ埋込みと平坦化を同時に達成しよう
とする提案がある。図８において、図中の符号81は表面
にＰウェル82，Ｎウェル83を形成したｐ- 型の基板であ
る。前記Ｐウェル82はＮウェル83の表面に開孔部が形成
されており、この開孔部にはアモルファスＳｉ84を介し
てＳｉＯ2 からなる絶縁物85が埋め込まれている。前記
絶縁物85で囲まれたＰウェル82はＮウェル83の表面に
は、ＳｉＯ2 膜86，多結晶Ｓｉ層87及びＳｉＮ膜88が順
次積層された積層膜が設けられている。なお、前記アモ
ルファスＳｉ84の上部はこの積層膜の上部まで達してい
る。また、図中の符号89は酸化物フィラメントである。On the other hand, in order to avoid an etchback process which is difficult to control, for example, USP 5130268 is used.
As shown in FIG. 8, the selective epitaxial silicon method is used to add silicon only within the trench to a depth of about 4 mm.
There is a proposal to achieve trench filling and planarization at the same time by depositing 0% and utilizing the volume expansion of silicon due to the subsequent thermal oxidation. In FIG. 8, reference numeral 81 in the drawing is a p − type substrate having a P well 82 and an N well 83 formed on the surface. The P well 82 has an opening formed in the surface of the N well 83, and an insulator 85 made of SiO 2 is embedded in the opening through amorphous Si 84. The P well 82 surrounded by the insulator 85 is provided on the surface of the N well 83 with a laminated film in which a SiO 2 film 86, a polycrystalline Si layer 87 and a SiN film 88 are sequentially laminated. The upper part of the amorphous Si 84 reaches the upper part of this laminated film. Further, reference numeral 89 in the drawing is an oxide filament.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、上記従
来技術は、下記に述べる問題点を有する。However, the above-mentioned prior art has the following problems.
【０００７】（１）前者の場合、堆積→エッチング→堆
積を繰り返すため、プロセスが複雑になるとともに、基
板に与える損傷も大きくなってしまう。(1) In the former case, since the process of deposition → etching → deposition is repeated, the process becomes complicated and the damage given to the substrate also becomes large.
【０００８】（２）後者の場合、埋め込まれたシリコン
の酸化の際、体積膨張はトレンチ上方だけでなく横方向
にも進もうとするため、トレンチ部全体が大きな応力を
受け、欠陥が発生しやすくなる。また、これ以外にも、
トレンチ開孔部での欠陥発生がトレンチ法で解決される
べき大きな問題である。(2) In the latter case, when the buried silicon is oxidized, the volume expansion tends to proceed not only above the trench but also laterally, so that the entire trench is subjected to a large stress and a defect occurs. It will be easier. Also, besides this,
The generation of defects at the trench opening is a major problem to be solved by the trench method.
【０００９】この発明はこうした事情を考慮してなされ
たもので、プロセスを簡略化できるとともに、基板に与
える損傷を軽減でき、更にトレンチ部全体に受ける応力
を小さくして欠陥を発生を素子分離方法を提供すること
を目的とする。The present invention has been made in consideration of such circumstances, and can simplify the process, reduce damage to the substrate, and reduce the stress applied to the entire trench portion to generate a defect. The purpose is to provide.
【００１０】[0010]
【課題を解決するための手段】本発明者は、バーズビー
クが大きくなりすぎない程度のＬＯＣＯＳを形成し、Ｌ
ＯＣＯＳ部の酸化膜を除去し、絶縁膜等を堆積した後、
スペーサエッチでＬＯＣＯＳリセス（凹部）内にスペー
サを形成し、スペーサをマスクにＬＯＣＯＳ凹部内にト
レンチを形成し、このトレンチを絶縁膜等で埋め込んで
形成するようにした。DISCLOSURE OF THE INVENTION The inventor of the present invention formed LOCOS to such an extent that the bird's beak does not become too large.
After removing the oxide film of the OCOS portion and depositing an insulating film and the like,
A spacer was formed in the LOCOS recess (recess) by spacer etching, a trench was formed in the LOCOS recess using the spacer as a mask, and the trench was filled with an insulating film or the like.
【００１１】即ち、本願第１の発明は、基板上に耐酸化
膜パターンを形成する工程と、この耐酸化膜パターンを
マスクとして前記基板を酸化させ、酸化膜を形成する工
程と、この酸化膜を除去し、前記基板に該酸化膜の除去
部分に対応する凹部を形成する工程と、この凹部を含む
全面に絶縁膜を堆積する工程と、この絶縁膜をエッチン
グし、前記凹部の側壁にのみ前記絶縁膜を残存させる工
程と、前記凹部が位置する基板に溝を形成する工程と、
この溝を絶縁物質で埋め込む工程とを具備することを特
徴とする半導体装置の素子分離方法である。That is, the first invention of the present application is a step of forming an oxidation resistant film pattern on a substrate, a step of oxidizing the substrate using the oxidation resistant film pattern as a mask to form an oxide film, and the oxide film. To form a concave portion corresponding to the removed portion of the oxide film on the substrate, depositing an insulating film on the entire surface including the concave portion, and etching the insulating film so that only the sidewall of the concave portion is formed. A step of leaving the insulating film, a step of forming a groove in the substrate in which the concave portion is located,
And a step of filling the groove with an insulating material.
【００１２】また、本願第２の発明は、基板上に耐酸化
膜パターンを形成する工程と、この耐酸化膜パターンを
マスクとして前記基板を酸化させ、酸化膜を形成する工
程と、この酸化膜を除去し、前記基板に該酸化膜の除去
部分に対応する凹部を形成する工程と、この凹部を含む
全面に絶縁膜を堆積する工程と、この絶縁膜をエッチン
グし、前記凹部の側壁にのみ前記絶縁膜を残存させる工
程と、前記凹部が位置する基板に溝を形成する工程と、
この溝の底部及び側壁に熱酸化膜を形成し、更に前記溝
に半導体物質又は導電物質を埋め込む工程とを具備する
ことを特徴とする半導体装置の素子分離方法である。A second invention of the present application is a step of forming an oxidation resistant film pattern on a substrate, a step of oxidizing the substrate using the oxidation resistant film pattern as a mask to form an oxide film, and the oxide film. To form a concave portion corresponding to the removed portion of the oxide film on the substrate, depositing an insulating film on the entire surface including the concave portion, and etching the insulating film so that only the sidewall of the concave portion is formed. A step of leaving the insulating film, a step of forming a groove in the substrate in which the concave portion is located,
And a step of forming a thermal oxide film on the bottom and side walls of the groove and further burying a semiconductor material or a conductive material in the groove.
【００１３】この発明において、前記耐酸化膜パターン
を形成した後、前記基板表面に該基板と同導電型の不純
物をイオン注入することが好ましい。ここで、基板の表
面にウェルを形成した場合は、ウェルと同導電型の不純
物をイオン注入する。In the present invention, it is preferable that after forming the oxidation resistant film pattern, an impurity of the same conductivity type as that of the substrate is ion-implanted into the surface of the substrate. Here, when a well is formed on the surface of the substrate, impurities of the same conductivity type as the well are ion-implanted.
【００１４】この発明において、絶縁物質は、前記基板
に溝を形成し、更に溝の底部及び側壁に熱酸化膜を形成
した後、前記溝にＴＥＯＳ膜等の絶縁物質を埋め込むこ
とにより形成される。In the present invention, the insulating material is formed by forming a groove in the substrate, further forming a thermal oxide film on the bottom and side walls of the groove, and then filling the groove with an insulating material such as a TEOS film. .
【００１５】この発明において、前記基板に溝を形成し
た後、溝の側壁に熱酸化膜を形成し、更にエピタキシャ
ル法で溝に溝底部で基板と接触するようにシリコンを埋
め込むことができる。In the present invention, after forming the groove in the substrate, a thermal oxide film may be formed on the side wall of the groove, and further silicon may be embedded in the groove by an epitaxial method so as to contact the substrate at the groove bottom.
【００１６】[0016]
【作用】この発明によれば、トレンチ上部になだらかな
開孔部があるため、ステップカバレッジの改善，埋込み
多結晶シリコン等の酸化の際の応力緩和が行われる。Ｌ
ＯＣＯＳ時に拡散したボロンがトレンチ周囲に均一なド
ーピングを与える。According to the present invention, since there is a gentle opening in the upper portion of the trench, the step coverage is improved and the stress is relaxed when the buried polycrystalline silicon or the like is oxidized. L
Boron diffused during OCOS provides uniform doping around the trench.
【００１７】[0017]
【実施例】以下、この発明の一実施例について図１〜図
６を参照して工程順に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in the order of steps with reference to FIGS.
【００１８】(1) まず、ｐ- 型のＳｉ基板１に９２０
℃，Ｏ2 雰囲気で厚さ２０nmの酸化膜（ＳｉＯ2 膜）２
を形成した。つづいて、この酸化膜２上に、ＬＰＣＶＤ
法を用い７９０℃，ＳｉＨ2 Ｃｌ2 ／ＮＨ3 の雰囲気で
厚さ１５０nmの窒化膜（Ｓｉ3Ｎ4 膜）を形成した。次
に、フォトリソグラフィ技術を用いてレジスト３を形成
した後、このレジスト３をマスクとして前記窒化膜をパ
ターニングし、窒化膜パターン４を形成した。更に、フ
ィールドイオン注入として知られる寄生ＮＭＯＳ分離用
のＢ（ボロン）イオン注入を、加速電圧３０ＫｅＶ，ド
ーズ量４×１０13／cm2 と加速電圧１８０ＫｅＶ，ドー
ズ量８×１０11／cm2 の条件で２段階で行なった（図１
参照）。(1) First, 920 is formed on the p − type Si substrate 1.
Oxide film (SiO 2 film) with a thickness of 20 nm in O 2 atmosphere
Was formed. Then, LPCVD is performed on the oxide film 2.
Method was used to form a nitride film (Si 3 N 4 film) having a thickness of 150 nm in the atmosphere of SiH 2 Cl 2 / NH 3 at 790 ° C. Next, a resist 3 was formed by using a photolithography technique, and then the nitride film was patterned using the resist 3 as a mask to form a nitride film pattern 4. Further, B (boron) ion implantation for parasitic NMOS isolation known as field ion implantation is performed under the conditions of an acceleration voltage of 30 KeV, a dose amount of 4 × 10 13 / cm 2 and an acceleration voltage of 180 KeV, and a dose amount of 8 × 10 11 / cm 2 . In two steps (Fig. 1
reference).
【００１９】(2) 次に、前記レジスト３を剥離した後、
９８０℃，Ｏ2 ／Ｈ2 雰囲気でＬＯＣＯＳ酸化を行な
い、酸化膜（ＳｉＯ2 膜）５を形成した（図２参照）。
ここで、バーズビークを抑制するため、酸化膜５の膜厚
は６００nm以下とするが、望ましくは２００nm〜４００
nmが良い。但し、続くトレンチ形成で深いトレンチを用
いる場合には、酸化膜の膜厚はさらに薄くできる。つづ
いて、前記酸化膜５をＨＦを含むエッチング液を用いて
エッチング除去した。その結果、酸化膜５が除去された
基板部分に凹部６が形成された（図３参照）。(2) Next, after peeling off the resist 3,
LOCOS oxidation was performed at 980 ° C. in an O 2 / H 2 atmosphere to form an oxide film (SiO 2 film) 5 (see FIG. 2).
Here, in order to suppress the bird's beak, the thickness of the oxide film 5 is set to 600 nm or less, preferably 200 nm to 400 nm.
nm is good. However, when a deep trench is used in the subsequent trench formation, the film thickness of the oxide film can be further reduced. Subsequently, the oxide film 5 was removed by etching using an etching solution containing HF. As a result, the recess 6 was formed in the substrate portion where the oxide film 5 was removed (see FIG. 3).
【００２０】(3) 次に、全面にＬＰＣＶＤ法により膜厚
３００nmの酸化膜（ＬＴＤ：low temperature oxide ）
７を３８０℃，ＳｉＨ4 ／Ｏ2 の条件で堆積した（図４
参照）。ここで、前記酸化膜７は、ＬＰＣＶＤの代わり
に、ＴＥＯＳ，ＨＴＯ（highteperature oxide)，スパ
ッタ，プラズマＣＶＤ等を用いて行なって形成してもよ
い。つづいて、前記酸化膜７をＲＩＥ（Ｒeactive ion
etching ）を用いて、Ａｒ／ＣＨＦ3 混合ガスで異方性
エッチングを行ない、凹部６の側壁に酸化膜（スペー
サ）７′を残存させた（図５参照）。(3) Next, a 300 nm-thick oxide film (LTD: low temperature oxide) is formed on the entire surface by LPCVD.
7 was deposited under the conditions of 380 ° C. and SiH 4 / O 2 (FIG. 4).
reference). Here, the oxide film 7 may be formed by using TEOS, HTO (high temperature oxide), sputtering, plasma CVD or the like instead of LPCVD. Then, the oxide film 7 is removed by RIE (Reactive ion).
Etching) was used to perform anisotropic etching with a mixed gas of Ar / CHF 3 to leave an oxide film (spacer) 7'on the sidewall of the recess 6 (see FIG. 5).
【００２１】(4) 次に、ＲＩＥを用いてＣｌ2 ／ＣＨＦ
3 4 混合ガスで前記Ｓｉ基板１を異方性エッチングし、
トレンチ（溝）８を形成した。ここで、トレンチ８の深
さは素子分離用としては１．０μｍ以下とし、望ましく
は２００nm〜４００nmが良い。つづいて、トレンチ８の
底部の分離能を高めるため、ボロンを加速電圧３０Ｋｅ
Ｖ，ドーズ量３×１０12／cm2 の条件で前記Ｓｉ基板１
にイオン注入した。更に、トレンチ８の表面を軽く熱酸
化して酸化膜９を形成した後、ＴＥＯＳ膜10ａ，10ｂ，
10ｃの埋込みを行ない、素子分離領域11を形成した（図
６参照）。(4) Next, by using RIE, Cl 2 / CHF
3 4 the Si substrate 1 in a mixed gas is anisotropically etched,
A trench (groove) 8 was formed. Here, the depth of the trench 8 is 1.0 μm or less for element isolation, and preferably 200 nm to 400 nm. Subsequently, in order to enhance the separating ability of the bottom of the trench 8, boron is accelerated at an accelerating voltage of 30 Ke.
The Si substrate 1 under the conditions of V and dose of 3 × 10 12 / cm 2.
Ion-implanted into. Further, after lightly oxidizing the surface of the trench 8 to form an oxide film 9, the TEOS films 10a, 10b,
A device isolation region 11 was formed by embedding 10c (see FIG. 6).
【００２２】上記実施例では、図１で基板１にイオン注
入したボロンがＬＯＣＯＳ酸化で酸化膜５を形成する
際、ボロンが酸化膜５から所定距離離れて基板１に均一
に拡散されており（図２参照）、その内にトレンチ８を
形成しているので、トレンチが深くない場合は、追加の
Ｂイオン注入は不要である。また、Ｂイオン注入を行な
う場合でも、低エネルギー，低ドーピングレベルで良い
という特徴がある。In the above embodiment, when the boron ion-implanted into the substrate 1 in FIG. 1 forms the oxide film 5 by LOCOS oxidation, the boron is uniformly diffused into the substrate 1 at a predetermined distance from the oxide film 5 ( (See FIG. 2), since the trench 8 is formed therein, if the trench is not deep, additional B ion implantation is unnecessary. Further, even when B ion implantation is performed, low energy and a low doping level are required.
【００２３】これに対し、一般にトレンチ分離ではトレ
ンチのまわりにＢドープ層を形成するため、トレンチ側
壁に斜めにイオン注入などを行なうが、チャネリングや
シャドウイング効果で一様なドーピングが難しい。On the other hand, generally, in the trench isolation, since the B-doped layer is formed around the trench, ion implantation is performed obliquely on the sidewall of the trench, but uniform doping is difficult due to channeling and shadowing effects.
【００２４】また、上記実施例の場合、次のような利点
を有する。図６から分かるように、トレンチ８の上部は
なだらかな開口部となっている。良く知られているよう
に、コンタクトホールやビアホールは、メタルのステッ
プカバレッジを高めるためラウンドエッチングを行な
う。ここでは、ＬＯＣＯＳ凹部を利用してラウンド部を
形成している。また、ＬＯＣＯＳ凹部があるため、トレ
ンチ深さはトレンチだけの場合より浅くできるため、ト
レンチにおけるアスペクト比を小さくできる。つまり、
図６に示すようにボイドフリーな絶縁膜埋込みに適した
構造になっている。これに対し、従来例（ＵＳＰ４６２
６３１７）では、ボイド等の欠陥が生じることが確認さ
れている。Further, the above embodiment has the following advantages. As can be seen from FIG. 6, the upper portion of the trench 8 has a gentle opening. As is well known, contact holes and via holes are round-etched to improve the step coverage of metal. Here, the LOCOS concave portion is used to form the round portion. Further, since the LOCOS concave portion is provided, the trench depth can be made shallower than in the case of only the trench, so that the aspect ratio in the trench can be reduced. That is,
As shown in FIG. 6, the structure is suitable for embedding a void-free insulating film. In contrast, the conventional example (USP462
6317), it has been confirmed that defects such as voids occur.
【００２５】なお、上記実施例では、トレンチに酸化膜
を介してＴＥＯＳ膜を埋め込んだ場合について述べた
が、これに限らず、図７に示すようにエピタキシャルシ
リコン（Ｓｉ）71を堆積してもよい。具体的には、例え
ばまずトレンチ部を３０nm程度酸化した後、ＨＴＯを堆
積する。つづいて、異方性ドライエッチングを行ない、
トレンチ底面のＳｉ基板１を露出させる。次いで、選択
エピタキシャルＳｉ71を堆積し、トレンチ部にのみＳｉ
を成長させる。図７に示すようにＳｉがＬＯＣＯＳ凹部
まで成長した後、酸化を行なう。酸化は、酸化後のエピ
タキシャルＳｉ酸化膜面が基板面に達する程度で良い。
この場合、エピタキシャルＳｉは前記凹部のラウンド部
（なだらかな面）にあるため、酸化によるエピタキシャ
ルＳｉの体積膨張はこの開放系で吸収され、応力による
欠陥発生が妨げる。また、上記実施例において、特許請
求の範囲の請求項１の絶縁物質がＳｉＯ2 の場合はトレ
ンチ内が全て（Ｓｉの）酸化物となるが、トレンチ内が
Ｓｉ3 Ｎ4 の場合は、Ｓｉ3Ｎ4 の表面にトラップされ
た電荷が表面をつたってリークする恐れがあるので熱酸
化膜がある方が好ましい。In the above embodiment, the case where the TEOS film is buried in the trench via the oxide film has been described, but the present invention is not limited to this, and epitaxial silicon (Si) 71 may be deposited as shown in FIG. Good. Specifically, for example, the trench portion is first oxidized to about 30 nm, and then HTO is deposited. Subsequently, anisotropic dry etching is performed,
The Si substrate 1 on the bottom surface of the trench is exposed. Next, selective epitaxial Si71 is deposited, and Si is formed only in the trench portion.
Grow. As shown in FIG. 7, after Si grows up to the LOCOS recess, oxidation is performed. The oxidation may be performed so that the surface of the epitaxial Si oxide film after the oxidation reaches the surface of the substrate.
In this case, since the epitaxial Si is in the round portion (smooth surface) of the recess, the volume expansion of the epitaxial Si due to oxidation is absorbed by this open system, and the generation of defects due to stress is prevented. Further, in the above embodiment, when the insulating material of claim 1 is SiO 2 , the inside of the trench is entirely (Si) oxide, but when the inside of the trench is Si 3 N 4 , Si It is preferable to have a thermal oxide film because charges trapped on the surface of 3 N 4 may leak across the surface.
【００２６】これに対し、図８の従来例（ＵＳＰ５１３
０２６８）の場合、エピタキシャルＳｉは完全にトレン
チで囲まれており、体積膨張の応力をまともに受けてし
まう。 なお、本例ではエピタキシャルＳｉにＢドープ
を行ない、そこからトレンチ底部にＢドープ層を作成し
ている。このような応力緩和は選択エピタキシャルシリ
コンに限らない。On the other hand, the conventional example of FIG. 8 (USP513
In the case of (0268), the epitaxial Si is completely surrounded by the trench and is directly subjected to the stress of volume expansion. In this example, the epitaxial Si is doped with B, and the B-doped layer is formed on the bottom of the trench from the epitaxial Si. Such stress relaxation is not limited to selective epitaxial silicon.
【００２７】また、本例では、トレンチはＬＯＣＯＳ凹
部の中にあり、直接トランジスタなどのデバイスと接触
しないが、デバイスと接触するＬＯＣＯＳに関しても、
犠牲酸化等の欠陥対策が確立してので、トレンチ起因の
欠陥によるデバイス特性劣化は抑制できる。In this example, the trench is in the LOCOS recess and does not directly contact the device such as a transistor.
Since measures against defects such as sacrificial oxidation have been established, deterioration of device characteristics due to defects due to trenches can be suppressed.
【００２８】更に、本例では、Ｓｉ基板を用いた場合に
つて述べたが、これに限らず、Ｇｅ基板でもよい。ま
た、本例では、基板と同導電型の不純物（ボロン）をイ
オン注入した場合について述べたが、基板表面にウェル
を形成し、該ウェルと同導電型の不純物を導入する場合
でも同様に適用できる。Further, in this example, the case where the Si substrate is used has been described, but the present invention is not limited to this, and a Ge substrate may be used. Further, in this example, the case where the impurity (boron) of the same conductivity type as that of the substrate is ion-implanted is described, but the same applies to the case of forming a well on the surface of the substrate and introducing the impurity of the same conductivity type as the well it can.
【００２９】ところで、素子の微細化に伴ないトランジ
スタの狭チャネル効果が問題になっている。ＬＯＣＯＳ
分離にしろ、トレンチ分離にしろ、電気的分離に用いて
いるドーパントの横広がりがこの原因の１つである。By the way, the narrow channel effect of transistors has become a problem with the miniaturization of devices. LOCOS
Whether it is isolation or trench isolation, the lateral spread of the dopant used for electrical isolation is one of the causes.
【００３０】例えば、ＬＯＣＯＳ後イオン注入のように
ＬＯＣＯＳ直下に高エネルギーでドーパントを注入し、
チャネル部まで広がらないようにすることができる。し
かし、高エネルギーイオン注入によるダメージや、イオ
ンとして実用的なのはＢ（ボロン）のみである、という
問題がある。For example, by implanting a dopant with high energy just below LOCOS, such as ion implantation after LOCOS,
It is possible not to spread to the channel part. However, there is a problem that damage due to high energy ion implantation and that only B (boron) is practical as an ion.
【００３１】一方、本発明を用いると、ＬＯＣＯＳ凹部
にスペーサー形成後又はトレンチ形成後に低エネルギー
で種々のドーパントを目的に応じてイオン注入したり、
またドープト多結晶Ｓｉからの拡散でドーポアントを拡
散でき、しかもチャネル部から離れたＬＯＣＯＳ凹部内
のトレンチでこれが行われるため、上記狭チャネル効果
を抑制することができる。On the other hand, according to the present invention, after forming spacers or trenches in the LOCOS recesses, various dopants are ion-implanted at low energy depending on the purpose, or
Further, since the dopant can be diffused by the diffusion from the doped polycrystalline Si, and this is performed in the trench in the LOCOS concave portion apart from the channel portion, the narrow channel effect can be suppressed.
【００３２】[0032]
【発明の効果】以上詳述した如くこの発明によれば、プ
ロセスを簡略化できるとともに、基板に与える損傷を軽
減でき、更にトレンチ部全体に受ける応力を小さくして
欠陥を発生を抑制しえる半導体装置の素子分離方法を提
供できる。As described above in detail, according to the present invention, the process can be simplified, the damage to the substrate can be reduced, and the stress applied to the entire trench portion can be reduced to suppress the generation of defects. An element isolation method of the device can be provided.
【図１】この発明の一実施例に係る素子分離方法の一工
程を示す断面図で、基板表面にボロンを注入した状態ま
でを示す。FIG. 1 is a cross-sectional view showing one step of an element isolation method according to an embodiment of the present invention, showing up to a state where boron is implanted into a substrate surface.
【図２】この発明の一実施例に係る素子分離方法の一工
程を示す断面図で、基板表面に凹部用の酸化膜を形成入
した状態までを示す。FIG. 2 is a cross-sectional view showing one step of an element isolation method according to an embodiment of the present invention, showing a state where an oxide film for a recess is formed and formed on the surface of a substrate.
【図３】この発明の一実施例に係る素子分離方法の一工
程を示す断面図で、凹部用の酸化膜を除去した状態まで
を示す。FIG. 3 is a cross-sectional view showing one step of an element isolation method according to an embodiment of the present invention, showing up to a state where the oxide film for the recess is removed.
【図４】この発明の一実施例に係る素子分離方法の一工
程を示す断面図で、スペーサ用の酸化膜を基板全面に形
成した状態までを示す。FIG. 4 is a cross-sectional view showing one step of an element isolation method according to an embodiment of the present invention, showing up to a state where an oxide film for a spacer is formed on the entire surface of the substrate.
【図５】この発明の一実施例に係る素子分離方法の一工
程を示す断面図で、基板表面に形成した凹部にスペーサ
を形成した状態までを示す。FIG. 5 is a cross-sectional view showing one step of an element isolation method according to an embodiment of the present invention, showing up to a state where spacers are formed in the recesses formed on the substrate surface.
【図６】この発明の一実施例に係る素子分離方法の一工
程を示す断面図で、基板表面おトレンチにＴＥＯＳ膜を
形成して素子分離領域を形成した状態までを示す。FIG. 6 is a cross-sectional view showing one step of an element isolation method according to an embodiment of the present invention, showing up to a state where a TEOS film is formed in a trench on a substrate surface to form an element isolation region.
【図７】この発明の他の実施例に係る素子分離方法の例
を示す概略断面図。FIG. 7 is a schematic sectional view showing an example of an element isolation method according to another embodiment of the present invention.
【図８】従来の素子分離方法の一例を示す断面図。FIG. 8 is a sectional view showing an example of a conventional element isolation method.
１…Ｓｉ基板、 ２，５，７，７′，９…酸化膜、
３…窒化膜、４…レジスト、 ６…凹部
８…トレンチ、10ａ，10ｂ，10ｃ…ＴＥＯ
Ｓ膜、 11…素子分離領域、71…エ
ピタキシャルＳｉ。1 ... Si substrate, 2, 5, 7, 7 ', 9 ... Oxide film,
3 ... Nitride film, 4 ... Resist, 6 ... Recess
8 ... Trench, 10a, 10b, 10c ... TEO
S film, 11 ... Element isolation region, 71 ... Epitaxial Si.
フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/76 Ｓ 21/94 Ｚ Continuation of front page (51) Int.Cl. 6 Identification code Office reference number FI Technical display area H01L 21/76 S 21/94 Z
Claims (5)
程と、この耐酸化膜パターンをマスクとして前記基板を
酸化させ、酸化膜を形成する工程と、この酸化膜を除去
し、前記基板に該酸化膜の除去部分に対応する凹部を形
成する工程と、この凹部を含む全面に絶縁膜を堆積する
工程と、この絶縁膜をエッチングし、前記凹部の側壁に
のみ前記絶縁膜を残存させる工程と、前記凹部が位置す
る基板に溝を形成する工程と、この溝を絶縁物質で埋め
込む工程とを具備することを特徴とする半導体装置の素
子分離方法。1. A step of forming an oxidation resistant film pattern on a substrate, a step of oxidizing the substrate using the oxidation resistant film pattern as a mask to form an oxide film, and removing the oxide film to form a substrate. A step of forming a recess corresponding to the removed portion of the oxide film, a step of depositing an insulating film on the entire surface including the recess, and a step of etching the insulating film to leave the insulating film only on the sidewall of the recess. And a step of forming a groove in the substrate in which the recess is located, and a step of filling the groove with an insulating material.
記基板表面に該基板と同導電型の不純物をイオン注入す
ることを特徴とする請求項１記載の半導体装置の素子分
離方法。2. The element isolation method for a semiconductor device according to claim 1, wherein after forming the oxidation resistant film pattern, impurities of the same conductivity type as the substrate are ion-implanted into the surface of the substrate.
底部及び側壁に熱酸化膜を形成し、更に前記溝に絶縁物
質を埋め込むことを特徴とする請求項１記載の半導体装
置の素子分離方法。3. The semiconductor device according to claim 1, wherein after forming the groove in the substrate, a thermal oxide film is formed on a bottom portion and a side wall of the groove, and an insulating material is embedded in the groove. Element isolation method.
壁に熱酸化膜を形成し、更にエピタキシャル法で前記溝
に溝底部で基板と接触するシリコンを埋め込むことを特
徴とする請求項１記載の素子分離方法。4. A thermal oxide film is formed on the side wall of the groove after the groove is formed in the substrate, and silicon which is in contact with the substrate at the groove bottom is embedded in the groove by an epitaxial method. 1. The element isolation method as described in 1.
程と、この耐酸化膜パターンをマスクとして前記基板を
酸化させ、酸化膜を形成する工程と、この酸化膜を除去
し、前記基板に該酸化膜の除去部分に対応する凹部を形
成する工程と、この凹部を含む全面に絶縁膜を堆積する
工程と、この絶縁膜をエッチングし、前記凹部の側壁に
のみ前記絶縁膜を残存させる工程と、前記凹部が位置す
る基板に溝を形成する工程と、この溝の底部及び側壁に
熱酸化膜を形成し、更に前記溝に半導体物質又は導電物
質を埋め込む工程とを具備することを特徴とする半導体
装置の素子分離方法。5. A step of forming an oxidation resistant film pattern on a substrate, a step of oxidizing the substrate using the oxidation resistant film pattern as a mask to form an oxide film, and removing the oxide film to form a substrate on the substrate. A step of forming a recess corresponding to the removed portion of the oxide film, a step of depositing an insulating film on the entire surface including the recess, and a step of etching the insulating film to leave the insulating film only on the sidewall of the recess. And a step of forming a groove in the substrate where the recess is located, a step of forming a thermal oxide film on the bottom and side walls of the groove, and further embedding a semiconductor material or a conductive material in the groove. Element isolation method for semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04030895A JP4384269B2 (en) | 1995-02-28 | 1995-02-28 | Element isolation method for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04030895A JP4384269B2 (en) | 1995-02-28 | 1995-02-28 | Element isolation method for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08236609A true JPH08236609A (en) | 1996-09-13 |
| JP4384269B2 JP4384269B2 (en) | 2009-12-16 |
Family
ID=12576997
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP04030895A Expired - Lifetime JP4384269B2 (en) | 1995-02-28 | 1995-02-28 | Element isolation method for semiconductor device |
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| Country | Link |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6043135A (en) * | 1997-02-06 | 2000-03-28 | Nec Corporation | Process of fabricating a semiconductor device having trench isolation allowing pattern image to be exactly transferred to photo-resist layer extending thereon |
-
1995
- 1995-02-28 JP JP04030895A patent/JP4384269B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6043135A (en) * | 1997-02-06 | 2000-03-28 | Nec Corporation | Process of fabricating a semiconductor device having trench isolation allowing pattern image to be exactly transferred to photo-resist layer extending thereon |
| CN1094256C (en) * | 1997-02-06 | 2002-11-13 | 日本电气株式会社 | Technology for making semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4384269B2 (en) | 2009-12-16 |
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